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OX16C950-PLBG

型号：

OX16C950-PLBG

品牌：

OXFORD[ OXFORD SEMICONDUCTOR ]

页数：

50 页

PDF大小：

280 K

下载PDF手册
OX16C950 rev B  
High Performance UART  
with 128 byte FIFOs  
FEATURES  
•
•
Single full-duplex asynchronous channel  
128-byte deep transmitter / receiver FIFO  
•
Automated out-of-band flow control using CTS# / RTS#  
and DSR# / DTR#  
•
•
•
Readable in-band and out-of-band flow control status  
Programmable special character detection  
•
Fully software compatible with industry standard  
16C550 type UARTs  
•
Pin compatible with TL16C550B/C, ST16C650 and  
TL16C750  
Arbitrary trigger levels for receiver and transmitter FIFO  
interrupts and automatic in-band and out-of-band flow  
control  
•
•
IBM PC/AT compatible  
•
•
Transmitter idle interrupt (shift register and FIFO both  
empty)  
Baud rates up to 15 Mbps in normal mode and  
60Mbps in external 1x clock mode  
Optional Infra-red (IrDA) receiver and transmitter  
operation  
•
•
Readable FIFO levels  
Flexible clock prescaler from 1 to 31.875  
•
•
•
•
•
•
•
RS-485 buffer enable signals  
Software channel reset  
•
Isochronous mode using external 1x baud rate clock  
up to 60Mbps  
•
•
•
9-bit data framing as well as 5,6,7 and 8  
Detection of bad data in the receiver FIFO  
Four byte device ID  
Sleep mode (low operating current)  
Automated in-band flow control using programmable  
Xon/Xoff characters  
System clock up to 60 MHz (at 5V), 50 MHz at 3.3V  
44 PLCC and 48 TQFP packages  
5 volts operation (PLCC), 3.3/ 5V operation TQFP  
•
Transmitter and receiver can be disabled  
REV B ENHANCEMENTS  
The OX16C950B is an enhanced, fully backward-compatible revision of the OX16C950 rev A. The chief enhancements are as  
follows –  
•
•
All known errata fixed  
Enhanced features first offered in OX16PCI954 added – these include controls for sleep-mode sensitivity, ability to  
read FCR and Good Data Status  
•
•
•
•
3V operation possible with 48 pin TQFP  
Enhanced isochronous clocking options (optional inversions)  
Enhanced system clock selection options (use of CLKSEL as a clock input)  
Readable TxRdy, RxRdy status and forcing TxRdy or RxRdy inactive  
Hereafter OX16C950 rev B is simply referred to as OX16C950.  
External–Free Release  
© Oxford Semiconductor 2005  
OX16C950 rev B DS-0031 Sep 05  
Part Nos. OX16C950-PCC60-B  
OX16C950-TQC60-B  
Oxford Semiconductor Ltd.  
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK  
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141  
OX16C950-PLBG  
OX16C950-TQBG  
DESCRIPTION  
The OX16C950 is a single-channel ultra-high performance  
UART offering data rates up to 15Mbps and 128-deep  
transmitter and receiver FIFOs. Deep FIFOs reduce CPU  
overhead and allow utilisation of higher data rates.  
performance of their system. FIFO levels are readable to  
facilitate fast driver applications.  
The addition of software reset enables recovery from  
unforeseen error condition allowing drivers to restart  
gracefully. The OX16C950 supports 9-bit data frames  
used in multi-drop industrial protocols. It also offers multiple  
external clock options for isochronous applications, e.g.  
ISDN, xDSL.  
It is software compatible with the widely used industry-  
standard 16C550 type devices and compatibles, as well as  
other OX16C95x family devices. It is pin-compatible with  
the TL16C550, ST16C650 devices.  
In addition to increased performance and FIFO size, the  
OX16C950 also provides enhanced features including  
improved flow control. Automated software flow control  
using Xon/Xoff and automated hardware flow control using  
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow  
control and interrupt thresholds are fully programmable and  
readable, enabling programmers to fine-tune the  
The OX16C950 is ideally suited to PC applications, such  
as high-speed COM port add-in cards which enable PC  
users to take advantage of the maximum performance of  
analogue modems or ISDN terminal adapters. It is also  
suitable for any equipment requiring high speed  
RS232/RS422/RS485 interfaces. Fabricated in 0.6μm  
process, OX16C950 also has a low operating current and  
sleep mode for battery powered applications.  
External–Free Release  
© Oxford Semiconductor 2005  
OX16C950 rev B DS-0031 Sep 05  
Part Nos. OX16C950-PCC60-B  
OX16C950-TQC60-B  
Oxford Semiconductor Ltd.  
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK  
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141  
OX16C950-PLBG  
OX16C950-TQBG  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
CONTENTS  
FEATURES....................................................................................................................................................................................... 1  
REV B ENHANCEMENTS................................................................................................................................................................ 1  
DESCRIPTION ................................................................................................................................................................................. 2  
CONTENTS ...................................................................................................................................................................................... 3  
1
2
3
PERFORMANCE COMPARISON.............................................................................................................................................. 6  
BLOCK DIAGRAM..................................................................................................................................................................... 7  
PIN INFORMATION.................................................................................................................................................................... 8  
4
PIN DESCRIPTIONS.................................................................................................................................................................. 9  
4.1  
FURTHER PIN INFORMATION ................................................................................................................................................. 12  
5
MODE SELECTION.................................................................................................................................................................. 14  
450 MODE........................................................................................................................................................................... 14  
550 MODE........................................................................................................................................................................... 14  
EXTENDED 550 MODE.......................................................................................................................................................... 14  
750 MODE........................................................................................................................................................................... 14  
650 MODE........................................................................................................................................................................... 14  
950 MODE........................................................................................................................................................................... 15  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
6
REGISTER DESCRIPTION TABLES....................................................................................................................................... 16  
7
7.1  
7.2  
RESET CONFIGURATION....................................................................................................................................................... 20  
HARDWARE RESET............................................................................................................................................................... 20  
SOFTWARE RESET ............................................................................................................................................................... 20  
8
TRANSMITTER & RECEIVER FIFOS...................................................................................................................................... 21  
8.1  
FIFO CONTROL REGISTER ‘FCR’ ......................................................................................................................................... 21  
9
LINE CONTROL & STATUS.................................................................................................................................................... 22  
FALSE START BIT DETECTION............................................................................................................................................... 22  
LINE CONTROL REGISTER ‘LCR’........................................................................................................................................... 22  
LINE STATUS REGISTER ‘LSR’.............................................................................................................................................. 23  
9.1  
9.2  
9.3  
10 INTERRUPTS & SLEEP MODE............................................................................................................................................... 24  
10.1 INTERRUPT ENABLE REGISTER ‘IER’..................................................................................................................................... 24  
10.2 INTERRUPT STATUS REGISTER ‘ISR’..................................................................................................................................... 25  
10.3 INTERRUPT DESCRIPTION ..................................................................................................................................................... 25  
10.4 SLEEP MODE ....................................................................................................................................................................... 26  
11 MODEM INTERFACE............................................................................................................................................................... 26  
11.1 MODEM CONTROL REGISTER ‘MCR’ ..................................................................................................................................... 26  
11.2 MODEM STATUS REGISTER ‘MSR’........................................................................................................................................ 27  
12 OTHER STANDARD REGISTERS .......................................................................................................................................... 28  
12.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’ ............................................................................................................................. 28  
12.2 SCRATCH PAD REGISTER ‘SPR’ ........................................................................................................................................... 28  
13 AUTOMATIC FLOW CONTROL.............................................................................................................................................. 29  
13.1 ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................................ 29  
13.2 SPECIAL CHARACTER DETECTION......................................................................................................................................... 30  
13.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................................... 30  
13.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL........................................................................................................................... 30  
14 BAUD RATE GENERATION.................................................................................................................................................... 31  
14.1 GENERAL OPERATION .......................................................................................................................................................... 31  
14.2 CLOCK PRESCALER REGISTER ‘CPR’.................................................................................................................................... 32  
14.3 TIMES CLOCK REGISTER ‘TCR’............................................................................................................................................. 32  
14.4 INPUT CLOCK OPTIONS ........................................................................................................................................................ 34  
14.5 TTL CLOCK MODULE ........................................................................................................................................................... 34  
DS-0031 Sep 05  
External—Free Release  
Page 3  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
14.6 EXTERNAL 1X CLOCK MODE ................................................................................................................................................. 34  
14.7 CRYSTAL OSCILLATOR CIRCUIT ............................................................................................................................................ 34  
15 ADDITIONAL FEATURES ....................................................................................................................................................... 35  
15.1 ADDITIONAL STATUS REGISTER ‘ASR’................................................................................................................................... 35  
15.2 FIFO FILL LEVELS ‘TFL & RFL’ ............................................................................................................................................ 35  
15.3 ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................................ 35  
15.4 TRANSMITTER TRIGGER LEVEL ‘TTL’..................................................................................................................................... 37  
15.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ....................................................................................................................... 37  
15.6 FLOW CONTROL LEVELS ‘FCL & FCH’.................................................................................................................................. 37  
15.7 DEVICE IDENTIFICATION REGISTERS...................................................................................................................................... 37  
15.8 CLOCK SELECT REGISTER ‘CKS’.......................................................................................................................................... 38  
15.9 NINE-BIT MODE REGISTER ‘NMR’......................................................................................................................................... 38  
15.10  
15.11  
15.12  
15.13  
15.14  
15.15  
MODEM DISABLE MASK ‘MDM’......................................................................................................................................... 39  
READABLE FCR ‘RFC’..................................................................................................................................................... 39  
GOOD-DATA STATUS REGISTER ‘GDS’ .............................................................................................................................. 40  
DMA STATUS REGISTER ‘DMS’ ....................................................................................................................................... 40  
PORT INDEX REGISTER ‘PIX’............................................................................................................................................ 40  
CLOCK ALTERATION REGISTER ‘CKA’............................................................................................................................... 40  
16 OPERATING CONDITIONS..................................................................................................................................................... 41  
17 DC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 41  
17.1 5V OPERATION .................................................................................................................................................................... 41  
17.2 3V OPERATION .................................................................................................................................................................... 42  
18 AC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 43  
18.1 5V OPERATION .................................................................................................................................................................... 43  
18.2 3V OPERATION .................................................................................................................................................................... 44  
19 TIMING WAVEFORMS............................................................................................................................................................. 45  
20 PACKAGE INFORMATION...................................................................................................................................................... 47  
21 ORDERING INFORMATION .................................................................................................................................................... 48  
NOTES............................................................................................................................................................................................ 49  
CONTACT DETAILS...................................................................................................................................................................... 50  
REVISION HISTORY  
REV  
DATE  
REASON FOR CHANGE / SUMMARY OF CHANGE  
Sep 2005 30/8/2005  
Revision for additional green order code for both TQFP & PLCC packages  
DS-0031 Sep 05  
External—Free Release  
Page 4  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
DS-0031 Sep 05  
External—Free Release  
Page 5  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PERFORMANCE COMPARISON  
1
Feature  
External 1x baud rate clock  
Max baud rate in normal mode  
Max baud rate in 1x clock mode  
FIFO depth  
OX16C950  
Yes  
15 Mbps  
60 Mbps  
128  
16C450  
No  
115 kbps  
n/a  
1
16C550  
No  
115 kbps  
n/a  
16  
16C650  
No  
1.5 Mbps  
n/a  
32  
16C750  
No  
1 Mbps  
n/a  
64  
Sleep mode  
Auto Xon/Xoff flow  
Yes  
Yes  
Yes  
Yes  
127  
128  
128  
Yes  
Yes  
Yes  
248  
Yes  
No  
No  
No  
No  
1
1
n/a  
No  
n/a  
n/a  
n/a  
No  
No  
No  
No  
No  
4
1
n/a  
No  
No  
Yes  
Yes  
Yes  
No  
4
4
4
No  
No  
No  
Yes  
No  
Yes  
No  
4
1
n/a  
No  
No  
No  
n/a  
No  
Auto CTS#/RTS# flow  
Auto DSR#/DTR# flow  
No. of Rx interrupt thresholds  
No. of Tx interrupt thresholds  
No. of flow control thresholds  
Transmitter empty interrupt  
Readable status of flow control  
Readable FIFO levels  
Clock prescaler options  
Rx/Tx disable  
No  
n/a  
No  
2
No  
Software reset  
Yes  
No  
No  
No  
No  
Device ID  
Yes  
No  
No  
No  
No  
9-bit data frames  
Yes  
No  
No  
No  
No  
RS485 buffer enable  
Infra-red (IrDA)  
Yes  
Yes  
No  
No  
No  
No  
No  
Yes  
No  
No  
Table 1 OX16C950 performance compared with 16C450, 16C550, 16C650 and 16C750 devices  
Improvements of the OX16C950 over previous generations of PC UART:  
Deeper FIFOs:  
OX16C950 offers 128-byte deep FIFOs for the transmitter  
Special character detection:  
and receiver.  
The receiver can be programmed to generate an interrupt  
upon reception of a particular character value.  
Higher data rates:  
Transmission and reception baud rates up to 15Mbps. A  
flexible clock prescaler offers division ratios of 1 to 31 7/8  
in steps of 1/8 using a divide-by-“M N/8” circuitry. The  
flexible prescaler allows users to select from a wide variety  
of input clock frequencies as well as access to higher baud  
rates whilst maintaining compatibility with existing software  
drivers (see section 14.2).  
Power-down:  
The device can be placed in ‘sleep mode’ to conserve  
power.  
Readable FIFO levels:  
Driver efficiency can be improved by using readable FIFO  
levels.  
External clock options:  
Selectable trigger levels:  
The receiver can accept an external 1x clock on the DSR#  
input. The transmitter can accept a 1x clock on the RI#  
input and/or assert its own (Nx) clock on the DTR# output.  
In 1x mode, asynchronous data may be transmitted and  
received at speeds up to 60Mbps (see section 14.6).  
The receiver FIFO threshold can be arbitrarily  
programmed. The transmitter FIFO threshold and  
thresholds for automatic flow control can be programmed  
to operate at a variety of trigger levels.  
Additional control:  
Automatic flow control:  
The transmitter and receiver can be independently  
The UART automatically handles either or both in-band  
(software) flow control (transmitting and receiving Xon/Xoff  
characters) and out-of-band (hardware) flow control using  
the RTS#/CTS# or DSR#/DTR# modem control lines.  
disabled.  
DS-0031 Sep 05  
External—Free Release  
Page 6  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
Additional status:  
Device ID:  
Software drivers are able to read the status of in-band and  
out-of-band automatic flow control, and distinguish  
between Xoff and special character received interrupts.  
Four bytes of device ID are available to identify the  
OX16C950 device to software drivers.  
Infra-red ‘IrDA’ interface:  
Software reset:  
The UART contains an IrDA compliant modulator and  
The software driver may reset the device to recover from  
demodulator.  
unforeseen or unusual error conditions.  
9-bit data framing:  
Transmitter empty interrupt:  
The transmitter can generate an interrupt when the FIFO  
and shift register are both empty.  
The OX16C950 may be configured to use in 9-bit character  
framing for multi-drop protocols where a tag ID (9th bit)  
differentiates address and data characters.  
RS485 buffer enable:  
The DTR# pin may be re-assigned as a buffer-enable  
signal for RS485 line driver in half-duplex mode (see  
ACR[4:3] in section 15.3).  
2
BLOCK DIAGRAM  
A[2:0]  
D[7:0]  
Transmitter  
SOUT  
SIN  
128 Byte  
FIFO  
CS0  
CS1  
Receiver  
Bus  
CS2#  
IOR  
Interface  
128 Byte  
FIFO  
IOR#  
IOW  
VDD  
GND  
IOW#  
ADS#  
Power  
supply  
Control  
and  
Status  
Registers  
FIFOSEL  
RESET  
RTS#  
DTR#  
OUT1  
OUT2  
Control  
and DMA  
Interface  
RXRDY#  
TXRDY#  
DDIS  
Modem  
Control  
Interface  
CTS#  
DSR#  
DCD#  
RI#  
XTLI  
XTLO  
Clock &  
Baud Rate  
Generator  
CLKSEL  
BDOUT#  
RCLK  
Interrupt  
Control  
Logic  
INTSEL  
INT  
Figure 1: OX16C950 Block Diagram  
DS-0031 Sep 05  
External—Free Release  
Page 7  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PIN INFORMATION  
3
44 Pin Plastic Leaded Chip Carrier  
6
5
4
3
2
1
44  
43  
42  
41  
40  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
DB5  
RESET  
OUT1#  
DTR#  
RTS#  
OUT2#  
INTSEL#  
INT  
8
DB6  
9
DB7  
10  
RCLK  
11  
SIN  
OX16C950-PCC60-B  
12  
NC  
13  
SOUT  
14  
CS0  
RXRDY#  
A0  
15  
CS1  
16  
CS2#  
A1  
17  
BDOUT#  
A2  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
48 Pin Thin Quad Flat Pack  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
NC  
DB5  
1
36  
INTSEL#  
RESET  
OUT1#  
DTR#  
RTS#  
OUT2#  
INT  
2
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DB6  
3
DB7  
4
RCLK  
NC  
5
6
O
X
1
6
C
9
5
0
-
T
Q
C
6
0-B  
SIN  
7
SOUT  
CS0  
8
RXRDY#  
A0  
9
CS1  
10  
11  
12  
A1  
CS2#  
BDOUT#  
A2  
NC  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DS-0031 Sep 05  
External—Free Release  
Page 8  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PIN DESCRIPTIONS  
4
PLCC  
Clock  
18  
TQFP  
14  
Dir1 Name  
Description  
I
XTLI  
Crystal oscillator input or external clock pin.  
Maximum frequency 60 MHz @ 5V, 50 MHz @ 3.3V  
19  
23  
15  
O
IU  
XTLO  
CLKSEL  
Crystal oscillator output. Not used when an alternative TTL level clock is  
applied to XTLI and can be left unconnected.  
21  
The state of this pin on power up configures the internal clock prescaler. This  
pin has an internal pull-up. When CLKSEL pin is high the pre-scalar is  
bypassed. Connect this pin to GND to enable the internal clock prescaler  
(see section 14.2). The complement of this pin is loaded in MCR[7] after a  
hardware reset.  
This pin can also be used as an alternative external clock pin under software  
control (replacing XTLI and thus reducing noise/power due to XTLO) for  
embedded applications  
Processor Interface  
39  
35  
I
I
RESET  
Active-high hardware reset. Hardware reset is described in section 7.1. This  
pin must be tied inactive when not in use.  
14, 15  
16  
29 -31 26 – 28  
28  
9,  
10  
11  
CS0,CS1 Active-high chip select. All chip select pins must be active for the device to  
be selected.  
CS2#  
A[2:0]  
ADS#  
I
I
I
Active-low chip select.  
Address lines to select channel registers.  
24  
Active-low address strobe. When ADS# signal is low, the address (A[2:0])  
and chip select signal (CS0, CS1, CS2#) drive the internal logic, otherwise  
they are latched at the level they were when low-to-high transition of ADS#  
signal occurred. This pin is used when address and chip selects are not  
stable during read or write cycles. If this functionality is not required, this pin  
can be permanently tied to GND.  
9 - 2  
26  
4 – 2,  
47 – 43  
22  
I/O  
O
I
DB[7:0]  
DDIS  
Eight-bit 3-state data bus.  
Drive Disable. This pin goes active (high) when CPU is not reading from  
OX16C950. This signal can be used to disable an external transceiver.  
Active-low write strobe. When IOW# is used to write the chip, IOW should be  
tied low (inactive).  
20  
16  
IOW#  
21  
24  
17  
19  
I
I
IOW  
Active-high write strobe. When IOW is used to write the chip, IOW# should be  
tied high (inactive).  
Active-low read strobe. When IOR# is used to read from the chip, IOR should  
be tied low (inactive).  
IOR#  
25  
20  
I
IOR  
Active-high read strobe. When IOR is used to read from the chip, IOR#  
should be tied high (inactive).  
DS-0031 Sep 05  
External—Free Release  
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OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PLCC TQFP Dir1 Name  
Serial port pins  
Description  
13  
8
O
SOUT  
Transmitter serial data output.  
IrDA_Out  
This pin is re-defined to IrDA output when IrDA mode is enabled, i.e. MCR[6]  
set in Enhanced mode.  
O
O
36  
32  
RTS#  
DTR#  
Active-low Request-To-Send output. Whenever the automated RTS# flow  
control is enabled, the RTS# pin is de-asserted and re-asserted if the receiver  
FIFO reaches or falls below a pair of programmed flow control thresholds,  
respectively. This pin’s state is controlled by bit 1 of the MCR. RTS may also  
be used as a general-purpose output.  
Active-low modem Data-Terminal-Ready output. Whenever the automated  
DTR# flow control is enabled, the DTR# pin is asserted and de-asserted if the  
receiver FIFO reaches or falls below a pair of programmed flow control  
thresholds, respectively. The state is set by bit 0 of the MCR. DTR may also  
be used as a general purpose output.  
37  
33  
O
O
485_EN  
In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the  
state of the transmitter empty bit (or it’s inverse) to automatically control the  
direction of the RS485 transceiver buffer (see ACR[4:3]).  
Tx_Clk_Out  
Transmitter 1x (or baud rate generator output) clock. For isochronous  
applications, the 1x (or Nx) transmitter clock may be asserted on the DTR#  
pin (see CKS[5:4]).  
O
I
11  
40  
7
SIN  
Receiver serial data input.  
I
IrDA_In  
This pin is re-defined to IrDA input when IrDA mode is enabled, i.e. MCR[6]  
set in Enhanced mode.  
38  
I
CTS#  
Active-low Clear-To-Send input. Whenever the automated CTS# flow control  
is enabled and the CTS# pin is de-asserted, the transmitter will complete the  
current character and enter the idle mode until the CTS# pin is re-asserted.  
However, flow control characters are transmitted regardless of the state of the  
CTS# pin. The state of this pin is reflected in bit 4 of the MSR. It can also be  
used as a general-purpose input.  
41  
39  
I
DSR#  
Active-low modem Data-Set-Ready input. Whenever the automated DSR#  
flow control is enabled and the DSR# pin is de-asserted, the transmitter will  
complete the current character and enter the idle mode until the DSR# pin is  
re-asserted. However, flow control characters are transmitted regardless of  
the state of the DSR# pin. The state of this pin is reflected in bit 5 of the  
MSR. It can also be used as a genera- purpose input.  
I
I
I
Rx_Clk_In External receiver clock for isochronous applications. The Rx_Clk_In is  
selected when CKS[1:0] = ‘01’.  
42  
43  
40  
41  
DCD#  
Active-low modem Data-Carrier-Detect input. The state of this pin is reflected  
in bit 7 of the MSR. It can also be used as a general-purpose input  
Active-low modem Ring-Indicator input. The state of this pin is reflected in bit  
6 of the MSR. It can also be used as a general-purpose input. RI can be  
configured as tx and rx for a 1x clock in isochronous operation.  
RI#  
I
Tx_Clk_In External transmitter clock. This clock can be used by the transmitter (and by  
the receiver indirectly) when CKS[6]=’1’.  
17  
10  
12  
5
O
BDOUT#  
Baud out. BDOUT# is a Nx (usually 16x, see TCR) clock signal for the  
transmitter. It is the output of the baud generator module. The receiver can  
use this clock by connecting BDOUT# to the RCLK pin or setting CKS[1:0] to  
’10’ where BDOUT# will be connected to RCLK internally. In this case setting  
CKS[2] to ‘1’ will disable the BDOUT# pin to conserve power.  
Receiver clock. RCLK is the Nx (usually 16x, see TCR) baud rate clock for  
the receiver.  
I
RCLK  
DS-0031 Sep 05  
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OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PLCC TQFP  
Interrupt & DMA Pins  
Dir1 Name  
Description  
33  
30  
O
INT  
The serial channel has a three-state interrupt output. This signal goes active  
(high) when an interrupt condition occurs. The three-state logic is controlled  
by INTSEL# and MCR[3] as described below.  
27  
32  
34  
23  
29  
36  
O
O
IU  
TXRDY#  
RXRDY#  
INTSEL#  
Signal for DMA transfer of transmitter data. There are two modes of DMA  
signalling described in section 8.1.  
Signal for DMA transfer of received data. There are two modes of DMA  
signalling described in section 8.1.  
Active-low interrupt select. This pin has an internal pull-up resistor. When  
INTSEL# is high or unconnected, the INT pin is enabled and MCR[3] is  
ignored. When INTSEL# is low, the tri-state control of INT is controlled by  
MCR[3]. In this case INT is enabled when MCR[3] is set and is high-  
impedance when MCR[3] is low.  
This pin is used to save the external three-state buffer for the interrupt pin.  
When using this facility, the INT output should be pulled down to GND using  
a 1KΩ resistor.  
Miscellaneous Pins  
38  
35  
1
34  
31  
37  
O
O
ID  
OUT1#  
OUT2#  
FIFOSEL  
This user defined output pin reflects the complement of MCR[2]. It is inactive  
(high) after a hardware reset or during loopback mode.  
This user defined output pin reflects the complement of MCR[3]. It is inactive  
(high) after a hardware reset or during loopback mode  
FIFO select. This pin has an internal pull-down. For backward compatibility  
with 16C550, 16C650 and 16C750 devices the FIFO depth is 16 when  
FIFOSEL is low or left open. The FIFO size is 128 when FIFOSEL is high.  
The unlatched state of this pin is readable by software. The FIFO size may  
be set to 128 by writing a 1 in FCR[5] when LCR[7] is set or by putting the  
device into Enhanced mode, thus overriding the state of the FIFOSEL pin.  
This pin is unconnected in 16C550 and 16C750 devices.  
-
48  
ID  
VSEL  
Voltage selector. This pin is used to control the voltage thresholds on all  
input pins. When low (or unconnected), 5V biased TTL thresholds are used.  
When high, 3V biased TTL thresholds are used. Generally should be tied  
high when the OX16C950 is being powered off 3 Volts, and low (or  
unconnected) when powered off 5 Volts. If tied high under 5V operation,  
CMOS compatible input thresholds are obtained.  
As this pin is not accessible in the PLCC, the PLCC is unsuitable for 3V  
applications.  
12  
1, 13,  
25, 6  
NC  
These pins are not connected.  
Power and Ground  
22  
18  
GND  
VDD  
Ground (0 Volts). The GND pin should be tied to ground.  
Power supply. The VDD pin should be tied to 5 Volts or 3.3 Volts  
Table 2: Pin Descriptions  
44  
42  
Note 1: Direction key:  
I
Input  
IU  
ID  
O
Input with pull-up  
Input with pull-down  
Output  
I/O  
Bi-directional  
Note: Attention should be given to high frequency decoupling of power and ground pins due to the high frequency internal switching that occurs  
under normal operation  
DS-0031 Sep 05  
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OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
4.1  
Further Pin Information  
Pin  
Description  
Action when used  
Bus Interface Pins  
Connect to active high chip select generation Tie high – All chip selects must be  
logic active in order to access the device  
Connect to active high chip select generation Tie high – All chip selects must be  
logic active in order to access the device  
Connect to active low chip select generation Tie low – All chip selects must be active  
Action when not used  
CS0  
CS1  
CS2#  
IOR  
Chip Select  
Chip Select  
Chip Select  
logic  
in order to access the device  
Tie low (IOR# will be used to control I/O  
read operations)  
Additional I/O Read Control Connect to processors active high I/O read  
line (and tie IOR# high)  
IOW  
Additional I/O Write Control Connect to processors active high I/O write Tie low (IOW# will be used to control  
line (and tie IOW# high) I/O read operations)  
Control Pins  
Tie low to allow software enable/disable of the Leave unconnected (Pulled high  
INTSEL# Interrupt Control Mode  
interrupt pin.  
internally to leave the interrupt pin  
permanently enabled).  
DMA Pins  
RXRDY# DMA Control signal output  
TXRDY# DMA Control signal output  
Connect direct to DMA control circuitry  
Connect direct to DMA control circuitry  
Clock Related Pins  
Leave unconnected  
Leave unconnected  
BDOUT# Baud rate generator output Connect direct to the RCLK pin in order to run Leave unconnected  
the receiver with the same clock as the  
transmitter  
RCLK  
Receiver clock input  
Connect directly to a suitable receiver clock  
source (Usually the BDOUT# pin)  
Connect to suitable clock input  
n/a  
n/a  
XTLI  
XTLO  
Crystal circuit input  
Crystal circuit output  
Connect to crystal oscillator circuit  
Leave unconnected  
Miscellaneous Pins  
DDIS  
ADS#  
Driver Disable output  
Address Strobe In  
Connect to active high bus transceiver drive Leave unconnected  
disable (goes high when device is not being  
read from)  
Connect direct to external control circuitry  
(Low-High transition on this pin latches CS0-2  
and A0-2)  
Tie low  
OUT1#  
OUT2#  
User defined output  
User defined output  
Connect direct to TTL input of external circuit Leave unconnected  
to control  
Connect direct to TTL input of external circuit Leave unconnected  
to control  
Common Channel Pins  
SOUT  
SIN  
Serial data output  
Serial data input  
Connect to a suitable line driver  
Connect to a suitable line receiver  
Connect to a suitable line driver  
Leave unconnected  
(Serial data can not be transmitted)  
Leave unconnected  
(Serial data can not be received)  
Leave unconnected  
RTS#  
CTS#  
DTR#  
DSR#  
Request-To-Send Modem  
signal output  
Clear-To-Send Modem signal Connect to a suitable line receiver  
input  
Data-Terminal-Ready  
Modem signal output  
Data-Set-Ready  
Tie high  
Connect to a suitable line driver  
Leave unconnected  
Tie high  
Connect to a suitable line receiver  
Modem signal input  
DS-0031 Sep 05  
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OXFORD SEMICONDUCTOR LTD.  
Pin  
Description  
Action when used  
Action when not used  
DCD#  
Data-Carrier-Detect  
Modem signal input  
Ring-Indicator  
Connect to a suitable line receiver  
Tie high  
RI#  
Connect to a suitable line receiver  
Tie high  
Modem signal input  
INT  
Interrupt Output  
Connect to an available processor interrupt Leave unconnected  
line (Interrupts can not be used)  
DS-0031 Sep 05  
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OXFORD SEMICONDUCTOR LTD.  
MODE SELECTION  
5
The OX16C950 device is a single channel device software compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs.  
The operation of the OX16C950 depends on a number of mode settings. These modes are referred to throughout this data  
sheet. The FIFO depth and compatibility modes are tabulated below:  
UART Mode  
FIFO  
size  
1
FCR[0]  
Enhanced mode  
(EFR[4]=1)  
X
FCR[5]  
(guarded with LCR[7] = 1)  
FIFOSEL  
pin  
X
450  
0
X
550  
Extended 550  
650  
16  
1
1
1
1
1
0
0
1
0
1
0
X
X
1
0
1
X
0
X
128  
128  
128  
128  
750  
950*  
X
Table 3: UART Mode Configuration  
* Note that 950 mode configuration is identical to 650 configuration  
guard. Once FCR[5] is set, the software should clear  
LCR[7] for normal operation.  
5.1  
450 Mode  
After a hardware reset bit 0 of the FIFO Control Register  
(‘FCR’) is cleared, hence OX16C950 is compatible with the  
16C450. The transmitter and receiver FIFOs (referred to as  
the ‘Transmit Holding Register’ and ‘Receiver Holding  
Register’ respectively) have a depth of one. This is referred  
to as ‘Byte mode’. When FCR[0] is cleared, all other mode  
selection parameters are ignored.  
The 16C750 additional features over the 16C550 are  
available as long as the UART is not put into Enhanced  
mode (i.e. EFR[4] should be ‘0’). These features are:  
1. Deeper FIFOs  
2. Automatic RTS/CTS out-of-band flow control  
3. Sleep mode  
5.2  
550 Mode  
5.5  
650 Mode  
Connect FIFOSEL to GND or leave it unconnected. After a  
hardware reset, writing a 1 to FCR[0] will increase the FIFO  
size to 16, providing compatibility with 16C550 devices.  
Since this pin is a no-connect in 16C550 devices, replacing  
a 16C550 with OX16C950 would result in a 550 compatible  
device with 16 byte deep FIFOs.  
The OX16C950 is compatible with the 16C650 when  
EFR[4] is set, i.e. the device is in Enhanced mode. As 650  
software drivers usually put the device into Enhanced  
mode, running 650 drivers on the OX16C950 device will  
result in 650 compatibility with 128 deep FIFOs, as long as  
FCR[0] is set. This is regardless of the state of the  
FIFOSEL pin or package option. Note that the 650  
emulation mode of the OX16C950 provides 128 byte deep  
FIFOs whereas the standard 16C650 has only 32 byte  
FIFOs.  
5.3  
Extended 550 Mode  
Connect FIFOSEL to VDD. Writing a 1 to FCR[0] will now  
increase the FIFO size to 128, thus providing a 550 device  
with 128 deep FIFOs.  
650 mode has the same enhancements as the 16C750  
over the 16C550, but these are enabled using different  
registers.  
5.4  
750 Mode  
For compatibility with 16C750, leave FIFOSEL  
unconnected.  
There are also additional enhancements over those of the  
16C750 in this mode, these are:  
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a  
similar fashion to 16C750, the FIFO size can be further  
increased to 128 by writing a 1 to FCR[5]. Note that access  
to FCR[5] is protected by LCR[7]. I.e., to set FCR[5],  
software should first set LCR[7] to temporarily remove the  
1. Automatic in-band flow control  
2. Special character detection  
3. Infra-red “IrDA-format” transmit and receive mode  
4. Transmit trigger levels  
5. Optional clock prescaler  
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OXFORD SEMICONDUCTOR LTD.  
5.6  
950 Mode  
The UART has a flexible prescaler capable of dividing the  
system clock by any value between 1 and 31.875 in steps  
of 0.125. It divides the system clock by an arbitrary value in  
“M N/8” format, where M and N are 5 and 3-bit binary  
numbers programmed in CPR[7:3] and CPR[2:0]  
respectively. This arrangement offers a great deal of  
flexibility when choosing an input clock frequency to  
synthesize arbitrary baud rates. The default division value  
is 4 to provide backward compatibility with 16C650  
devices.  
The additional features offered in OX16C950 (950 mode)  
generally only apply when the UART is in Enhanced mode  
(EFR[4]=’1’). Provided FCR[0] is set, in Enhanced mode  
the FIFO size is 128 regardless of the state of FIFOSEL.  
Note that 950 mode configuration is identical to that of 650  
mode, however additional 950 specific features are  
enabled using the Additional Control Register ‘ACR’ (see  
section 15.3). In addition to larger FIFOs and higher baud  
rates, the enhancements of the 16C950 over the 16C654  
are:  
The user may apply an external 1x (or Nx) clock for the  
transmitter and receiver to the RI# and DSR# pin  
respectively. The transmitter clock may be asserted on the  
DTR# pin. The external clock options are selected through  
the CKS register (offset 0x02 of ICR).  
•
•
Selectable arbitrary trigger levels for the receiver and  
transmitter FIFO interrupts  
Improved automatic flow control using selectable  
arbitrary thresholds  
•
•
•
•
•
•
•
DSR#/DTR# automatic flow control  
Transmitter and receiver can be optionally disabled  
Software reset of device  
It is also possible to define the over-sampling rate used by  
the transmitter and receiver clocks. The 16C450/16C550  
and compatible devices employ 16 times over-sampling,  
i.e. There are 16 clock cycles per bit. However, OX16C950  
can employ any over-sampling rate from 4 to 16 by  
programming the TCR register. This allows the data rates  
to be increased to 460.8 Kbps using a 1.8432MHz clock, or  
15 Mbps using a 60 MHz clock. The default value after a  
reset for this register is 0x00, which corresponds to a 16  
cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also  
result in a 16 cycle sampling clock. To program the value to  
any value from 4 to 15 it is necessary to write this value  
into TCR i.e. to set the device to a 13 cycle sampling clock  
it would be necessary to write 0x0D to TCR. For further  
information see sections 14.3.  
Readable FIFO fill levels  
Optional generation of an RS-485 buffer enable signal  
Four-byte device identification (0x16C95003)  
Readable status for automatic in-band and out-of-  
band flow control  
External 1x clock modes (see section 14.4)  
Flexible “M N/8” clock prescaler (see section 14.2)  
Programmable sample clock to allow data rates up to  
15 Mbps (see section 14.3)  
•
•
•
•
9-bit data mode  
The 950 trigger levels are enabled when ACR[5] is set (bits  
4 to 7 of FCR are ignored). Then arbitrary trigger levels can  
be defined in RTL, TTL, FCL and FCH registers (see  
section 15). The Additional Status Register (‘ASR’) offers  
flow control status for the local and remote transmitters.  
FIFO levels are readable using RFL and TFL registers.  
The OX16C950 also offers 9-bit data frames for multi-drop  
industrial applications.  
DS-0031 Sep 05  
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OXFORD SEMICONDUCTOR LTD.  
REGISTER DESCRIPTION TABLES  
6
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers  
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:  
1. LCR[7]=1 enables the divider latch registers DLL and DLM.  
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables  
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the  
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.  
3. ACR[7]=1 enables access to the 950 specific registers.  
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 18.  
Register Address R/W  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1
THR  
RHR  
000  
000  
W
R
Data to be transmitted  
Data received  
1
1,2  
IER  
CTS  
interrupt  
mask  
RTS  
interrupt  
mask  
Special  
Char.  
Detect  
650/950  
Mode  
Modem  
Sleep  
Rx Stat  
interrupt interrupt  
mask  
THRE  
RxRDY  
interrupt  
mask  
001  
010  
R/W  
W
interrupt  
mode  
Alternate  
sleep  
mode  
THR Trigger  
Level  
FIFO  
Size  
mask  
mask  
550/750  
Mode  
Unused  
3
FCR  
RHR Trigger  
Level  
RHR Trigger  
Level  
DMA  
Mode /  
Tx  
Trigger  
Enable  
650 mode  
Flush  
THR  
Flush  
RHR  
Enable  
FIFO  
750 mode  
Unused  
950 mode  
Unused  
FIFOs  
enabled  
Interrupt priority  
(Enhanced mode)  
Interrupt priority  
(All modes)  
Interrupt  
pending  
3
ISR  
010  
011  
R
Divisor  
Odd /  
Number  
of stop  
bits  
Tx  
break  
Force  
even  
Parity  
enable  
4
LCR  
R/W  
latch  
Data length  
parity  
parity  
access  
CTS &  
RTS  
Flow  
3,4  
MCR  
Internal  
Loop  
Back  
550/750  
Mode  
Unused  
OUT2  
(Int En)  
100  
101  
R/W  
R
OUT1  
RTS  
DTR  
Control  
Enable  
650/950  
Mode  
Baud  
IrDA  
XON-Any  
prescale  
mode  
3,5  
LSR  
Data  
Error  
THR  
Empty  
Rx  
Break  
Framing  
Error  
Parity  
Error  
Overrun  
Error  
Tx Empty  
RxRDY  
Normal  
9-bit data  
mode  
9th Rx  
data bit  
Delta  
DCD  
Trailing  
RI edge  
Delta  
DSR  
Delta  
CTS  
3
MSR  
110  
111  
R
DCD  
RI  
DSR  
CTS  
3
SPR  
Temporary data storage register and  
Indexed control register offset value bits  
Normal  
R/W  
9-bit data  
mode  
9th Tx  
data bit  
Unused  
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.  
DLL  
000  
001  
R/W  
R/W  
Divisor latch bits [7:0] (Least significant byte)  
Divisor latch bits [15:8] (Most significant byte)  
DLM  
Table 4: Standard 550 Compatible Registers  
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OXFORD SEMICONDUCTOR LTD.  
Register Address R/W  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
To access these registers LCR must be set to 0xBF  
EFR  
010  
100  
101  
110  
111  
R/W  
R/W  
R/W  
R/W  
R/W  
CTS  
flow  
control  
RTS  
Flow  
control  
Special  
char  
detect  
Enhanced  
mode  
In-band flow control mode  
XON1  
XON Character 1  
Special character 1  
XON Character 2  
Special Character 2  
XOFF Character 1  
Special character 3  
XOFF Character 2  
Special character 4  
9-bit mode  
XON2  
9-bit mode  
XOFF1  
9-bit mode  
XOFF2  
9-bit mode  
Table 5: 650 Compatible Registers  
Register Address R/W  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1,6,7  
7
ASR  
001  
R/W  
Tx  
Idle  
FIFO  
size  
FIFO-  
SEL  
Special  
Char  
DTR  
RTS  
Remote  
Tx  
Tx  
Disabled  
Detect  
Disabled  
6
RFL  
TFL  
011  
100  
101  
R
R
Number of characters in the receiver FIFO  
Number of characters in the transmitter FIFO  
3,6  
3,8,9  
ICR  
R/W  
Data read/written depends on the value written to the SPR prior to  
the access of this register (see Table 7)  
Table 6: 950 Specific Registers  
Register access notes:  
Note 1: Requires LCR[7] = 0  
Note 2: Requires ACR[7] = 0  
Note 3: Requires that last value written to LCR was not 0xBF  
Note 4: To read this register ACR[7] must be = 0  
Note 5: To read this register ACR[6] must be = 0  
Note 6: Requires ACR[7] = 1  
Note 7: Only bits 0 and 1 of this register can be written  
Note 8: To read this register ACR[6] must be = 1  
Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set  
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OXFORD SEMICONDUCTOR LTD.  
Register  
Name  
SPR  
R/W  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Offset 10  
Indexed Control Register Set  
ACR  
0x00  
R/W  
Addit-  
ional  
Status  
Enable  
ICR  
Read  
Enable  
950  
Trigger  
Level  
DTR definition and  
control  
Auto  
DSR  
Flow  
Control  
Enable  
Tx  
Disable  
Rx  
Disable  
Enable  
CPR  
TCR  
CKS  
TTL  
0x01  
0x02  
0x03  
0x04  
0x05  
R/W  
R/W  
R/W  
R/W  
R/W  
5 Bit “integer” part of  
clock prescaler  
Unused  
3 Bit “fractional” part of  
clock prescaler  
4 Bit N-times clock  
selection bits [3:0]  
Tx 1x  
Mode  
Unused  
Tx CLK  
Select  
BDOUT  
on DTR  
DTR 1x  
Tx CLK  
Rx 1x  
Mode  
Disable  
BDOUT  
Receiver  
Clock Sel[1:0]  
Transmitter Interrupt Trigger Level (0-127)  
RTL  
Unused  
Unused  
Unused  
Receiver Interrupt Trigger Level (1-127)  
FCL  
0x06  
R/W  
Automatic Flow Control Lower Trigger Level (0-127)  
FCH  
ID1  
ID2  
ID3  
0x07  
0x08  
0x09  
0x0A  
R/W  
R
Automatic Flow Control Higher Trigger level (1-127)  
Hardwired ID byte 1 (0x16)  
R
Hardwired ID byte 1 (0xC9)  
R
Hardwired ID byte 1 (0x50)  
REV  
0x0B  
R
Hardwired revision byte (0x03)  
CSR  
NMR  
MDM  
0x0C  
0x0D  
0x0E  
W
Writing 0x00 to this register will  
reset the UART (Except the CKS and CKA registers)  
R/W  
R/W  
Unused  
9th Bit  
9th Bit  
Schar 3  
9th Bit  
SChar 2  
Δ DCD  
Wakeup  
disable  
FCR[3]  
9th Bit  
SChar 1  
Trailing  
RI edge  
disable  
9th-bit Int.  
En.  
Δ DSR  
Wakeup  
disable  
FCR[1]  
9 Bit  
Enable  
SChar 4  
Δ CTS  
Wakeup  
disable  
FCR[0]  
Good  
Unused  
RFC  
GDS  
0X0F  
0X10  
R
R
FCR[7]  
FCR[6]  
FCR[5]  
FCR[4]  
Unused  
FCR[2]  
Data  
Status  
RxRdy  
status  
( R )  
DMS  
0x11  
R/W  
Force  
TxRdy  
inactive  
Force  
RxRdy  
inactive  
TxRdy  
status  
( R )  
Unused  
Hardwired Port Index ( 0x00 )  
PIDX  
CKA  
0x12  
0x13  
R
R/W  
Unused  
Output  
sys-clk  
on txrdy  
Use  
CLKSEL  
pin for  
Invert  
DTR  
signal  
Invert  
internal  
tx clock  
Invert  
internal  
rx clock  
sys-clk  
Table 7: Indexed Control Register Set  
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers  
via ICR. Offset values not listed in the table are reserved for future use and must not be used.  
To read or write to any of the Indexed Control Registers use the following procedure.  
Writing to ICR registers:  
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).  
Write the desired offset to SPR (address 1112).  
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Write the desired value to ICR (address 1012).  
Reading from ICR registers:  
Ensure that the last value written to LCR was not 0xBF (see above).  
Write 0x00 offset to SPR to select ACR.  
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxx2 to address 1012. Ensure that other bits in ACR are not changed.  
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)  
Write the desired offset to SPR (address 1112).  
Read the desired value from ICR (address 1012).  
Write 0x00 offset to SPR to select ACR.  
Clear bit 6 of ACR bye writing x0xxxxxx2 to ICR, thus enabling access to standard registers again.  
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RESET CONFIGURATION  
7
7.1  
Hardware Reset  
7.2  
Software Reset  
After a hardware reset, all writable registers are reset to  
0x00, with the following exceptions:  
An additional feature available in the OX16C950 device is  
software resetting of the serial channel. The software reset  
is available using the CSR register. Software reset has the  
same effect as a hardware reset except it does not reset  
the clock source selections (i.e. CKS register and CKA  
register). To reset the UART write 0x00 to the Channel  
Software Reset register ‘CSR’.  
1. DLL which is reset to 0x01.  
2. MCR[7] is reset to the complement of the CLKSEL  
input pin value (see section 11.1).  
3. CPR is reset to 0x20.  
The state of read-only registers following a hardware reset  
is as follows:  
RHR[7:0]: Indeterminate  
RFL[6:0]: 00000002  
TFL[6:0]: 00000002  
LSR[7:0]: 0x60 signifying that both the transmitter and the  
transmitter FIFO are empty  
MSR[3:0]: 00002  
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR  
and CTS respectively  
ISR[7:0]: 0x01, i.e. no interrupts are pending  
ASR[7:0]: 1xx000002  
RFC[7:0]: 000000002  
GDS[7:0]: 000000012  
DMS[7:0]: 000000102  
CKA[7:0]: 000000002  
The reset state of output signals for are tabulated below:  
Signal  
SOUT  
RTS#  
DTR#  
INT  
Reset state  
Inactive High  
Inactive High  
Inactive High  
Inactive low when INTSEL# pin is high or  
floating, otherwise high-impedance  
Inactive High  
RXRDY#  
TXRDY#  
Active low (THR is able to receive data).  
Table 8: Output Signal Reset State  
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8
TRANSMITTER & RECEIVER FIFOS  
Both the transmitter and receiver have associated holding  
registers (FIFOs), referred to as the transmitter holding  
register (THR) and receiver holding register (RHR)  
respectively.  
FCR[2]: Flush THR  
logic 0 ⇒ No change.  
logic 1 ⇒ Flushes the contents of the THR, in the same  
manner as FCR[1] does for the RHR.  
In normal operation, when the transmitter finishes  
transmitting a byte it will remove the next data from the top  
of the THR and proceed to transmit it. If the THR is empty,  
it will wait until data is written into it. If THR is empty and  
the last character being transmitted has been completed  
(i.e. the transmitter shift register is empty) the transmitter is  
said to be idle. Similarly, when the receiver finishes  
receiving a byte, it will transfer it to the bottom of the RHR.  
If the RHR is full, an overrun condition will occur (see  
section 9.3).  
DMA Transfer Signalling:  
FCR[3]: DMA signalling mode / Tx trigger level enable  
logic 0 ⇒ DMA mode '0'.  
logic 1 ⇒ DMA mode '1'.  
Note: In DMA mode 0, the transmitter trigger level is  
ALWAYS set to 1, thus ignoring FCR[5:4] and TTL.  
DMA Control signals can be generated using the TXRDY#  
and RXRDY# pins. Their operation is defined as follows:  
Data is written into the bottom of the THR queue and read  
from the top of the RHR queue completely asynchronously  
to the operation of the transmitter and receiver.  
The TXRDY# pin has no hysteresis and is simply activated  
using a comparison operation. When the UART is in DMA  
mode 0 (or in Byte mode), the TXRDY# output pin is active  
(low) whenever THR is empty, otherwise it is inactive.  
When in DMA mode 1, the TXRDY# pin is inactive (high)  
when the THR is full, otherwise it is active, signifying that  
there is room in the transmit FIFO.  
The size of the FIFOs is dependent on the setting of the  
FCR register. When in Byte mode, these FIFOs only  
accept one byte at a time before indicating that they are  
full; this is compatible with the 16C450. When in a FIFO  
mode, the size of the FIFOs is either 16 (compatible with  
the 16C550) or 128.  
The RXRDY# pin can operate with hysteresis. In DMA  
mode 0 (or in Byte mode), RXRDY# is only active (low)  
when RHR contains data. When in DMA mode 1 however,  
the operation is as follows:  
Data written to the THR when it is full is lost. Data read  
from the RHR when it is empty is invalid. The empty or full  
status of the FIFOs are indicated in the Line Status  
Register ‘LSR’ (see section 9.3). Interrupts can be  
generated or DMA signals can be used to transfer data  
to/from the FIFOs. The number of items in each FIFO may  
also be read back from the transmitter FIFO level (TFL)  
and receiver FIFO level (RFL) registers (see section 15.2).  
1. RXRDY# is set active when RFL has reached the  
receiver interrupt trigger level or a time-out event has  
occurred (see section 10.3) It remains active as long  
as RHR is not empty.  
2. RXRDY# is set inactive when RHR is empty. It  
remains in this state until condition 1 occurs.  
8.1  
FIFO Control Register ‘FCR’  
FCR[5:4]: THR trigger level  
Generally in 450, 550, extended 550 and 950 modes these  
bits are unused (see section 5 for mode definition). In 650  
mode they define the transmitter interrupt trigger levels and  
in 750 mode FCR[5] increases the FIFO size.  
FCR[0]: Enable FIFO mode  
logic 0 ⇒ Byte mode.  
logic 1 ⇒ FIFO mode.  
This bit should be enabled before setting the FIFO trigger  
levels.  
450, 550 and extended 550 modes:  
The transmitter interrupt trigger levels are set to 1 and  
FCR[5:4] are ignored.  
FCR[1]: Flush RHR  
logic 0 ⇒ No change.  
logic 1 ⇒ Flushes the contents of the RHR  
This is only operative when already in a FIFO mode. The  
RHR is automatically flushed whenever changing between  
Byte mode and a FIFO mode. This bit will return to zero  
after clearing the FIFOs.  
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650 mode:  
In 650 mode the transmitter interrupt trigger levels are set  
to the following values:  
In Byte mode (450 mode) the trigger levels are all set to 1.  
In all cases, a receiver data interrupt will be generated (if  
enabled) if the Receiver FIFO Level (‘RFL’) reaches the  
upper trigger level L2.  
FCR[5:4]  
Transmit Interrupt Trigger level  
00  
01  
10  
11  
16  
32  
64  
950 Mode:  
When 950 trigger levels are enabled (ACR[5]=1), more  
flexible trigger levels can be set by writing to the TTL, RTL,  
FCL and FCH (see section 15) hence ignoring FCR[7:6].  
112  
Table 9: Transmit Interrupt Trigger Levels  
These levels only apply when in Enhanced mode and in  
DMA mode 1 (FCR[3] = 1), otherwise the trigger level is set  
to 1. A transmitter empty interrupt will be generated (if  
enabled) if the TFL falls below the trigger level.  
9
LINE CONTROL & STATUS  
9.1  
False Start Bit Detection  
750 Mode:  
On the falling edge of a start bit, the receiver will wait for  
1/2 bit and re-synchronise the receiver’s sampling clock  
onto the centre of the start bit. The start bit is valid if the  
SIN line is still low at this mid-bit sample and the receiver  
will proceed to read in a data character. Verifying the start  
bit prevents the receiver from assembling a false data  
character due to a low going noise spike on the SIN input.  
In 750 compatible non-Enhanced (EFR[4]=0) mode,  
transmitter trigger level is set to 1, FCR[4] is unused and  
FCR[5] defines the FIFO depth as follows:  
FCR[5]=0 Transmitter and receiver FIFO size is 16 bytes.  
FCR[5]=1 Transmitter and receiver FIFO size is 128 bytes.  
In non-Enhanced mode and when FIFOSEL pin is low,  
FCR[5] is only writable when LCR[7] is set. Note that in  
Enhanced mode, the FIFO size is also increased to 128  
bytes when FCR[0] is set.  
Once the first stop bit has been sampled, the received data  
is transferred to the RHR and the receiver will then wait for  
a low transition on SIN signifying the next start bit.  
The receiver will continue receiving data even if the RHR is  
full or the receiver has been disabled (see section 15.3) in  
order to maintain framing synchronisation. The only  
difference is that the received data does not get transferred  
to the RHR.  
950 mode:  
Setting ACR[5]=1 enables arbitrary transmitter trigger level  
setting using the TTL register (see section 15.4), hence  
FCR[5:4] are ignored.  
FCR[7:6]: RHR trigger level  
9.2  
Line Control Register ‘LCR’  
In 550, extended 550, 650 and 750 modes, the receiver  
FIFO trigger levels are defined using FCR[7:6]. The  
interrupt trigger level and upper flow control trigger level  
where appropriate are defined by L2 in the table below. L1  
defines the lower flow control trigger level where  
applicable. Separate upper and lower flow control trigger  
levels introduce a hysteresis element in in-band and out-of-  
band flow control (see section 13).  
The LCR specifies the data format that is common to both  
transmitter and receiver. Writing 0xBF to LCR enables  
access to the EFR, XON1, XOFF1, XON2 and XOFF2,  
DLL and DLM registers. This value (0xBF) corresponds to  
an unused data format. Writing the value 0xBF to LCR will  
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the  
data format of the transmitter and receiver data is not  
affected. Write the desired LCR value to exit from this  
selection.  
FCR  
[7:6]  
Mode  
650  
Ext. 550 / 750  
FIFO Size 128 FIFO Size 128  
550  
FIFO Size 16  
L1  
1
16  
32  
L2  
16  
32  
L1  
1
1
1
1
L2  
1
32  
64  
112  
L1  
n/a  
n/a  
n/a  
n/a  
L2  
1
4
8
14  
00  
01  
10  
11  
112  
112 120  
Table 10: Receiver Trigger Levels  
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LCR[1:0]: Data length  
LCR[1:0] Determines the data length of serial characters.  
Note however, that these values are ignored in 9-bit data  
framing mode, i.e. when NMR[0] is set.  
9.3  
Line Status Register ‘LSR’  
This register provides the status of data transfer to CPU.  
LSR[0]: RHR data available  
logic 0 ⇒ RHR is empty: no data available  
logic 1 ⇒ RHR is not empty: data is available to be read.  
LCR[1:0]  
Data length  
5 bits  
00  
01  
10  
11  
6 bits  
7 bits  
8 bits  
LSR[1]: RHR overrun error  
logic 0 ⇒ No overrun error.  
logic 1 ⇒ Data was received when the RHR was full. An  
overrun error has occurred. The error is  
flagged when the data would normally have  
been transferred to the RHR.  
Table 11: LCR Data Length Configuration  
LCR[2]: Number of stop bits  
LCR[2] defines the number of stop bits per serial character.  
LSR[2]: Received data parity error  
LCR[2]  
Data length  
No. stop  
bits  
logic 0 ⇒ No parity error in normal mode or 9th bit of  
received data is ‘0’ in 9-bit mode.  
0
1
1
5,6,7,8  
5
6,7,8  
1
1.5  
2
logic 1 ⇒ Data has been received that did not have  
correct parity in normal mode or 9th bit of  
received data is ‘1’ in 9-bit mode.  
Table 12: LCR Stop Bit Number Configuration  
The flag will be set when the data item in error is at the top  
of the RHR and cleared following a read of the LSR. In 9-  
bit mode LSR[2] is no longer a flag and corresponds to the  
9th bit of the received data in RHR.  
LCR[5:3]: Parity type  
The selected parity type will be generated during  
transmission and checked by the receiver, which may  
produce a parity error as a result. In 9-bit mode parity is  
disabled and LCR[5:3] is ignored.  
LSR[3]: Received data framing error  
logic 0 ⇒ No framing error.  
logic 1 ⇒ Data has been received with an invalid stop  
LCR[5:3]  
xx0  
Parity type  
No parity bit  
bit.  
001  
011  
101  
111  
Odd parity bit  
Even parity bit  
Parity bit forced to 1  
Parity bit forced to 0  
This status bit is set and cleared in the same manner as  
LSR[2]. When a framing error occurs, the UART will try to  
re-synchronise by assuming that the error was due to  
sampling the start bit of the next data item.  
Table 13: LCR Parity Configuration  
LSR[4]: Received break error  
logic 0 ⇒ No receiver break error.  
logic 1 ⇒ The receiver received a break.  
LCR[6]: Transmission break  
logic 0 ⇒ Break transmission disabled.  
logic 1 ⇒ Forces the transmitter data output SOUT low  
to alert the communication terminal, or send  
zeros in IrDA mode.  
A break condition occurs when the SIN line goes low  
(normally signifying a start bit) and stays low throughout  
the start, data, parity and first stop bit. (Note that the SIN  
line is sampled at the bit rate). One zero character with  
associated break flag set will be transferred to the RHR  
and the receiver will then wait until the SIN line returns  
high. The LSR[4] break flag will be set when this data item  
gets to the top of the RHR and it is cleared following a read  
of the LSR.  
It is the responsibility of the software driver to ensure that  
the break duration is longer than the character period for it  
to be recognised remotely as a break rather than data.  
LCR[7]: Divisor latch enable  
logic 0 ⇒ Access to DLL and DLM registers disabled.  
logic 1 ⇒ Access to DLL and DLM registers enabled.  
LSR[5]: THR empty  
logic 0 ⇒ Transmitter FIFO (THR) is not empty.  
logic 1 ⇒ Transmitter FIFO (THR) is empty.  
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LSR[6]: Transmitter and THR empty  
In 9-bit mode (i.e. when NMR[0] is set) reception of a  
character with the address-bit (9th bit) set can generate a  
level 1 interrupt if IER[2] is set.  
logic 0 ⇒ The transmitter is not idle  
logic 1 ⇒ THR is empty and the transmitter has  
completed the character in shift register and is  
in idle mode. (I.e. set whenever the transmitter  
shift register and the THR are both empty.)  
IER[3]: Modem status interrupt mask  
logic 0 ⇒ Disable the modem status interrupt.  
logic 1 ⇒ Enable the modem status interrupt.  
LSR[7]: Receiver data error  
logic 0 ⇒ Either there are no receiver data errors in the  
FIFO or it was cleared by an earlier read of  
LSR.  
logic 1 ⇒ At least one parity error, framing error or break  
indication in the FIFO.  
IER[4]: Sleep mode  
logic 0 ⇒ Disable sleep mode.  
logic 1 ⇒ Enable sleep mode whereby the internal clock  
of the channel is switched off.  
In 450 mode LSR[7] is permanently cleared, otherwise this  
bit will be set when an erroneous character is transferred  
from the receiver to the RHR. It is cleared when the LSR is  
read. Note that in 16C550 this bit is only cleared when  
all of the erroneous data are removed from the FIFO. In  
9-bit data framing mode parity is permanently disabled, so  
this bit is not affected by LSR[2].  
Sleep mode is described in section 10.4.  
IER[5]: Special character interrupt mask or alternate  
sleep mode  
9-bit data framing mode:  
logic 0 ⇒ Disable the special character receive interrupt.  
logic 1 ⇒ Enable the special character receive interrupt.  
In 9-bit data mode, The receiver can detect up to four  
special characters programmed in Special Character 1 to  
4. When IER[5] is set, a level 5 interrupt is asserted when a  
match is detected.  
10 INTERRUPTS & SLEEP MODE  
The serial channel interrupts are asserted on the INT pin.  
When INTSEL# is high or unconnected, the INT pin is  
forcing logic and MCR[3] is ignored. When INTSEL# is low,  
the tri-state control of INT is controlled by MCR[3]. In this  
case the INT pin is forcing when MCR[3] is set. It is in high-  
impedance state when MCR[3] is cleared.  
650/950 modes (non-9-bit data framing):  
logic 0 ⇒ Disable the special character receive interrupt.  
logic 1 ⇒ Enable the special character receive interrupt.  
In 16C650 compatible mode when the device is in  
Enhanced mode (EFR[4]=1), this bit enables the detection  
of special characters. It enables both the detection of  
XOFF characters (when in-band flow control is enabled via  
EFR[3:0]) and the detection of the XOFF2 special  
character (when enabled via EFR[5]).  
10.1 Interrupt Enable Register ‘IER’  
Serial channel interrupts are enabled using the Interrupt  
Enable Register (‘IER’).  
IER[0]: Receiver data available interrupt mask  
logic 0 ⇒Disable the receiver ready interrupt.  
logic 1 ⇒Enable the receiver ready interrupt.  
750 mode (non-9-bit data framing):  
logic 0 ⇒ Disable alternate sleep mode.  
logic 1 ⇒ Enable alternate sleep mode whereby the  
internal clock of the channel is switched off.  
IER[1]: Transmitter empty interrupt mask  
logic 0 ⇒Disable the transmitter empty interrupt.  
logic 1 ⇒Enable the transmitter empty interrupt.  
In 16C750 compatible mode (i.e. non-Enhanced mode),  
this bit is used an alternate sleep mode and has the same  
effect as IER[4]. (See section 10.4)  
IER[2]: Receiver status interrupt  
Normal mode:  
logic 0 ⇒ Disable the receiver status interrupt.  
logic 1 ⇒ Enable the receiver status interrupt.  
9-bit data mode:  
logic 0 ⇒ Disable receiver status and address bit  
interrupt.  
logic 1 ⇒ Enable receiver status and address bit  
interrupt.  
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IER[6]: RTS interrupt mask  
logic 0 ⇒ Disable the RTS interrupt.  
logic 1 ⇒ Enable the RTS interrupt.  
10.3 Interrupt Description  
Level 1:  
Receiver status error interrupt (ISR[5:0]=’000110’):  
Normal (non-9-bit) mode:  
This interrupt is active whenever any of LSR[1], LSR[2],  
LSR[3] or LSR[4] are set. These flags are cleared following  
a read of the LSR. This interrupt is masked with IER[2].  
This enable is only operative in Enhanced mode  
(EFR[4]=1). In non-Enhanced mode, RTS interrupt is  
permanently enabled.  
IER[7]: CTS interrupt mask  
logic 0 ⇒ Disable the CTS interrupt.  
logic 1 ⇒ Enable the CTS interrupt.  
9-bit mode:  
This interrupt is active whenever any of LSR[1], LSR[2],  
LSR[3] or LSR[4] are set. The receiver error interrupt due  
to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The  
‘address-bit’ received interrupt is masked with NMR[1]. The  
software driver can differentiate between receiver status  
error and received address-bit (9th data bit) interrupt by  
examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only  
set when LSR[3] or LSR[4] is set and it is not affected by  
LSR[2] (i.e. 9th data bit).  
This enable is only operative in Enhanced mode  
(EFR[4]=1). In non-Enhanced mode, CTS interrupt is  
permanently enabled.  
10.2 Interrupt Status Register ‘ISR’  
The source of the highest priority interrupt pending is  
indicated by the contents of the Interrupt Status Register  
‘ISR’. There are nine sources of interrupt at six levels of  
priority (1 is the highest) as tabulated below:  
Level 2a:  
Receiver data available interrupt (ISR[5:0]=’000100’):  
This interrupt is active whenever the receiver FIFO level is  
above the interrupt trigger level.  
Level  
Interrupt source  
ISR[5:0]  
see note 3  
Level 2b:  
-
1
No interrupt pending 1  
Receiver status error or  
Address-bit detected in 9-bit mode  
Receiver data available  
000001  
000110  
Receiver time-out interrupt (ISR[5:0]=’001100’):  
A receiver time-out event, which may cause an interrupt,  
will occur when all of the following conditions are true:  
2a  
2b  
3
4
5 2  
000100  
001100  
000010  
000000  
010000  
Receiver time-out  
Transmitter THR empty  
Modem status change  
•
•
•
The UART is in a FIFO mode  
There is data in the RHR.  
There has been no read of the RHR for a period of  
time greater than the time-out period.  
In-band flow control XOFF or  
Special character (XOFF2) or  
Special character 1, 2, 3 or 4 or  
bit 9 set in 9-bit mode  
•
There has been no new data received and written into  
the RHR for a period of time greater than the time-out  
period. The time-out period is four times the character  
period (including start and stop bits) measured from  
the centre of the first stop bit of the last data item  
received.  
6 2  
CTS or RTS change of state  
100000  
Table 14: Interrupt Status Identification Codes  
Note1:  
Note2:  
ISR[0] indicates whether any interrupts are pending.  
Interrupts of priority levels 5 and 6 cannot occur unless  
the UART is in Enhanced mode.  
ISR[5] is only used in 650 & 950 modes. In 750 mode, it  
is ‘0’ when FIFO size is 16 and ‘1’ when FIFO size is  
128. In all other modes it is permanently set to ‘0’.  
Reading the first data item in RHR clears this interrupt.  
Level 3:  
Note3:  
Transmitter empty interrupt (ISR[5:0]=’000010’):  
This interrupt is set when the transmit FIFO level falls  
below the trigger level. It is cleared on an ISR read of a  
level 3 interrupt or by writing more data to the THR so that  
the trigger level is exceeded. Note that when 16C950 mode  
trigger levels are enabled (ACR[5]=1) and the transmitter  
trigger level of zero is selected (TTL=0x00), a transmitter  
empty interrupt will only be asserted when both the  
transmitter FIFO and transmitter shift register are empty  
and the SOUT line has returned to idle marking state.  
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11 MODEM INTERFACE  
Level 4:  
Modem change interrupt (ISR[5:0]=’000000’):  
This interrupt is set by a modem change flag (MSR[0],  
MSR[1], MSR[2] or MSR[3]) becoming active due to  
changes in the input modem lines. This interrupt is cleared  
following a read of the MSR.  
11.1 Modem Control Register ‘MCR’  
MCR[0]: DTR  
logic 0 ⇒ Force DTR# output to inactive (high).  
logic 1 ⇒ Force DTR# output to active (low).  
Level 5:  
Receiver in-band flow control (XOFF) detect interrupt,  
Receiver special character (XOFF2) detect interrupt,  
Receiver special character 1, 2, 3 or 4 interrupt or  
9th Bit set interrupt in 9-bit mode (ISR[5:0]=’010000’):  
A level 5 interrupt can only occur in Enhanced-mode when  
any of the following conditions are met:  
Note that DTR# can be used for automatic out-of-band flow  
control when enabled using ACR[4:3] (see section 15.3).  
MCR[1]: RTS  
logic 0 ⇒ Force RTS# output to inactive (high).  
logic 1 ⇒ Force RTS# output to active (low).  
•
•
•
A valid XOFF character is received while in-band flow  
control is enabled.  
A received character matches XOFF2 while special  
character detection is enabled.  
A received character matches special character 1, 2, 3  
or 4 in 9-bit mode (see section 15.9).  
Note that RTS# can be used for automatic out-of-band flow  
control when enabled using EFR[6] (see section 13.4).  
MCR[2]: OUT1  
logic 0 ⇒ Force OUT1# output low when loopback mode  
is disabled.  
logic 1 ⇒ Force OUT1# output high.  
It is cleared on an ISR read of a level 5 interrupt.  
Level 6:  
CTS or RTS changed interrupt (ISR[5:0]=’100000’):  
This interrupt is set whenever either of the CTS# or RTS#  
pins changes state from low to high. It is cleared on an ISR  
read of a level 6 interrupt.  
MCR[3]: OUT2/External interrupt enable  
logic 0 ⇒ Force OUT2# output low when loopback mode  
is disabled. If INTSEL# is low the external  
interrupt is in high-impedance state when  
MCR[3] is cleared. If INTSEL# is high MCR[3]  
does not affect the interrupt.  
logic 1 ⇒ Force OUT2# output high. If INTSEL# is low  
the external interrupt is enabled and operating  
in normal active (forcing) mode when MCR[3]  
is high. If INTSEL# is high MCR[3] does not  
affect the interrupt.  
10.4 Sleep Mode  
For a channel to go into sleep mode, all of the following  
conditions must be met:  
•
•
Sleep mode enabled (IER[4]=1 in 650/950 modes, or  
IER[5]=1 in 750 mode):  
The transmitter is idle, i.e. the transmitter shift register  
and FIFO are both empty.  
•
•
•
•
•
SIN is high.  
The receiver is idle.  
MCR[4]: Loopback mode  
logic 0 ⇒ Normal operating mode.  
logic 1 ⇒ Enable local loop-back mode (diagnostics).  
The receiver FIFO is empty (LSR[0]=0).  
The UART is not in loopback mode (MCR[4]=0).  
Changes on modem input lines have been  
acknowledged (i.e. MSR[3:0]=0000).  
No interrupts are pending.  
In local loop-back mode, the transmitter output (SOUT) and  
the four modem outputs (DTR#, RTS#, OUT1# and  
OUT2#) are set in-active (high), and the receiver inputs  
SIN, CTS#, DSR#, DCD#, and RI# are all disabled.  
Internally the transmitter output is connected to the receiver  
input and DTR#, RTS#, OUT1# and OUT2# are connected  
to modem status inputs DSR#, CTS#, RI# and DCD#  
respectively.  
•
A read of IER[4] (or IER[5] if a 1 was written to that bit  
instead) shows whether the power-down request was  
successful. The UART will fully retain its programmed state  
whilst in power-down mode.  
The channel will automatically exit power-down mode when  
any of the conditions 1 to 7 becomes false. It may be  
woken manually by clearing IER[4] (or IER[5] if the  
alternate sleep mode is enabled).  
Sleep mode operation is not available in IrDA mode.  
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In this mode, the receiver and transmitter interrupts are  
fully operational. The modem control interrupts are also  
operational, but the interrupt sources are now the lower  
four bits of the Modem Control Register instead of the four  
modem status inputs. The interrupts are still controlled by  
the IER.  
11.2 Modem Status Register ‘MSR’  
MSR[0]: Delta CTS#  
Indicates that the CTS# input has changed since the last  
time the MSR was read.  
MSR[1]: Delta DSR#  
Indicates that the DSR# input has changed since the last  
time the MSR was read.  
MCR[5]: Enable XON-Any in Enhanced mode or enable  
out-of-band flow control in non-Enhanced mode  
650/950 modes (Enhanced mode):  
logic 0 ⇒ XON-Any is disabled.  
logic 1 ⇒ XON-Any is enabled.  
MSR[2]: Trailing edge RI#  
Indicates that the RI# input has changed from low to high  
since the last time the MSR was read.  
In enhanced mode (EFR[4]=1), this bit enables the Xon-  
Any operation. When Xon-Any is enabled, any received  
data will be accepted as a valid XON (see in-band flow  
control, section 13.3).  
MSR[3]: Delta DCD#  
Indicates that the DCD# input has changed since the last  
time the MSR was read.  
MSR[4]: CTS  
750 mode (Non-Enhanced mode):  
logic 0 ⇒ CTS/RTS flow control disabled.  
logic 1 ⇒ CTS/RTS flow control enabled.  
This bit is the complement of the CTS# input. It is  
equivalent to RTS (MCR[1]) during internal loop-back  
mode.  
In non-enhanced mode, this bit enables the CTS/RTS out-  
of-band flow control.  
MSR[5]: DSR  
This bit is the complement of the DSR# input. It is  
equivalent to DTR (MCR[0]) during internal loop-back  
mode.  
MCR[6]: IrDA mode  
logic 0 ⇒ Standard serial receiver and transmitter data  
format.  
MSR[6]: RI  
This bit is the complement of the RI# input. In internal loop-  
back mode it is equivalent to the internal OUT1.  
logic 1 ⇒ Data will be transmitted and received in IrDA  
format.  
MSR[7]: DCD  
This function is only available in Enhanced mode. It  
requires a 16x clock to function correctly.  
This bit is the complement of the DCD# input. In internal  
loop-back mode it is equivalent to the internal OUT2.  
MCR[7]: Baud rate prescaler select  
logic 0 ⇒ Normal (divide by 1) baud rate generator  
prescaler selected.  
logic 1 ⇒ Divide-by-“M N/8” baud rate generator  
prescaler selected.  
Where M & N are programmed in CPR (ICR offset 0x01).  
After a hardware reset, CPR defaults to 0x20 (divide-by-4)  
and MCR[7] is loaded with the complement of the CLKSEL  
pin. User writes to this flag will only take effect in enhanced  
mode. See section 13.1.  
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12 OTHER STANDARD REGISTERS  
12.1 Divisor Latch Registers ‘DLL & DLM’  
12.2 Scratch Pad Register ‘SPR’  
The divisor latch registers are used to program the baud  
rate divisor. This is a value between 1 and 65535 by which  
the input clock is divided by in order to generate serial  
baud rates. After a hardware reset, the baud rate used by  
the transmitter and receiver is given by:  
The scratch pad register does not affect operation of the  
rest of the UART in any way and can be used for  
temporary data storage. The register may also be used to  
define an offset value to access the registers in the  
Indexed Control Register set. For more information on  
Indexed Control registers see Table 7 and section 15.  
InputClock  
Baudrate =  
16* Divisor  
Where divisor is given by DLL + ( 256 x DLM ). More  
flexible baud rate generation options are also available.  
See section 14 for full details.  
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13 AUTOMATIC FLOW CONTROL  
Automatic in-band flow control, automatic out-of-band flow  
control and special character detection features can be  
used when in Enhanced mode and are software compatible  
with the 16C654. Alternatively, 16C750 compatible  
automatic out-of-band flow control can be enabled when in  
non-Enhanced mode. In 950 mode, in-band and out-of-  
band flow controls are compatible with 16C654, with the  
addition of fully programmable flow control thresholds.  
EFR[3:2]: In-band transmit flow control mode  
When in-band transmit flow control is enabled, an  
XON/XOFF character is inserted into the data stream  
whenever the RFL passes the upper trigger level and falls  
below the lower trigger level respectively.  
For automatic in-band flow control, bit 4 of EFR must be  
set. The combinations of software transmit flow control can  
then be selected by programming EFR[3:2] as follows:  
13.1 Enhanced Features Register ‘EFR’  
logic [00] ⇒ In-band transmit flow control is disabled.  
logic [01] ⇒ Single character in-band transmit flow  
control enabled, using XON2 as the XON  
character and XOFF2 as the XOFF  
character.  
logic [10] ⇒ Single character in-band transmit flow  
control enabled, using XON1 as the XON  
character and XOFF1 as the XOFF  
character.  
Writing 0xBF to LCR enables access to the EFR and other  
Enhanced mode registers. This value corresponds to an  
unused data format. Writing 0xBF to LCR will set LCR[7]  
but leaves LCR[6:0] unchanged. Therefore, the data format  
of the transmitter and receiver data is not affected. Write  
the desired LCR value to exit from this selection.  
Note: In-band transmit and receive flow control is disabled  
in 9-bit mode.  
Logic[11] ⇒ The value EFR[3:2] = “11” is reserved for  
future use and should not be used  
EFR[1:0]: In-band receive flow control mode  
When in-band receive flow control is enabled, the UART  
compares the received data with the programmed XOFF  
character. When this occurs, the UART will disable  
transmission as soon as any current character  
transmission is complete. The UART then compares the  
received data with the programmed XON character. When  
a match occurs, the UART will re-enable transmission (see  
section 15.6).  
EFR[4]: Enhanced mode  
logic 0 ⇒ Non-Enhanced mode. Disables IER bits 4-7,  
ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and  
in-band flow control. Whenever this bit is  
cleared, the setting of other bits of EFR are  
ignored.  
logic 1 ⇒ Enhanced mode. Enables the Enhanced Mode  
functions. These functions include enabling  
IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For  
in-band flow control the software driver must  
set this bit first. If this bit is set, out-of-band  
flow control is configured with EFR bits 6-7,  
otherwise out-of-band flow control is  
compatible with 16C750.  
For automatic in-band flow control, bit 4 of EFR must be  
set. The combinations of software receive flow control can  
be selected by programming EFR[1:0] as follows:  
logic [00] ⇒ In-band receive flow control is disabled.  
logic [01] ⇒ Single character in-band receive flow control  
enabled, recognising XON2 as the XON  
character and XOFF2 as the XOFF  
character.  
logic [10] ⇒ Single character in-band receive flow control  
enabled, recognising XON1 as the XON  
character and XOFF1 and the XOFF  
character.  
logic [11] ⇒ The behavior of the receive flow control is  
dependent on the configuration of EFR[3:2].  
single character in-band receive flow control  
is enabled, accepting both XON1 and XON2  
as valid XON characters and both XOFF1  
and XOFF2 as valid XOFF characters when  
EFR[3:2] = “01” or “10”. EFR[1:0] should not  
be set to “11” when EFR[3:2] is either “00”.  
EFR[5]: Enable special character detection  
logic 0 ⇒ Special character detection is disabled.  
logic 1 ⇒ While in Enhanced mode (EFR[4]=1), the  
UART compares the incoming receiver data  
with the XOFF2 value. Upon a correct match,  
the received data will be transferred to the  
RHR and a level 5 interrupt (XOFF or special  
character) will be asserted if level 5 interrupts  
are enabled (IER[5] set to 1).  
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EFR[6]: Enable automatic RTS flow control.  
logic 0 ⇒ RTS flow control is disabled (default).  
logic 1 ⇒ RTS flow control is enabled in Enhanced mode  
(i.e. EFR[4] = 1), where the RTS# pin will be  
forced inactive high if the RFL reaches the  
upper flow control threshold. This will be  
released when the RFL drops below the lower  
threshold. The 650 and 950 software drivers  
should use this bit to enable RTS flow control.  
The 750 compatible driver uses MCR[5] to  
enable RTS flow control.  
When the 'XON Any' flag (MCR[5]) is set, any received  
character is accepted as a valid XON condition and the  
transmitter will be re-enabled. The received data will be  
transferred to the RHR.  
When in-band transmit flow control is enabled, the RFL will  
be sampled whenever the transmitter is idle (briefly,  
between characters, or when the THR is empty) and an  
XON/XOFF character may be inserted into the data stream  
if needed. Initially, remote transmissions are enabled and  
hence ASR[1] is clear. If ASR[1] is clear and the RFL has  
passed the upper trigger level (i.e. is above the trigger  
level), XOFF will be sent and ASR[1] will be set. If ASR[1]  
is set and the RFL falls below the lower trigger level, XON  
will be sent and ASR[1] will be cleared.  
EFR[7]: Enable automatic CTS flow control.  
logic 0 ⇒ CTS flow control is disabled (default).  
logic 1 ⇒ CTS flow control is enabled in Enhanced mode  
(i.e. EFR[4] = 1), where the data transmission  
is prevented whenever the CTS# pin is held  
inactive high. The 650 and 950 software  
drivers should use this bit to enable CTS flow  
control. The 750 compatible driver uses  
MCR[5] to enable CTS flow control.  
If transmit flow control is disabled after an XOFF has been  
sent, an XON will be sent automatically.  
13.4 Automatic Out-of-band Flow Control  
Automatic RTS/CTS flow control is selected by different  
means, depending on whether the UART is in Enhanced or  
non-Enhanced mode. When in non-Enhanced mode,  
MCR[5] enables both RTS and CTS flow control. When in  
Enhanced mode, EFR[6] enables automatic RTS flow  
control and EFR[7] enables automatic CTS flow control.  
This allows software compatibility with both 16C650 and  
16C750 drivers.  
13.2 Special Character Detection  
In Enhanced mode (EFR[4]=1), when special character  
detection is enabled (EFR[5]=1) and the receiver matches  
received data with XOFF2, the 'received special character'  
flag ASR[4] will be set and a level 5 interrupt is asserted, (if  
enabled by IER[5]). This flag will be cleared following a  
read of ASR. The received status (i.e. parity and framing)  
of special characters does not have to be valid for these  
characters to be accepted as valid matches.  
When automatic CTS flow control is enabled and the CTS#  
input becomes active, the UART will disable transmission  
as soon as any current character transmission is complete.  
Transmission is resumed whenever the CTS# input  
becomes inactive.  
13.3 Automatic In-band Flow Control  
When in-band receive flow control is enabled, the UART  
will compare the received data with XOFF1 or XOFF2  
characters to detect an XOFF condition. When this occurs,  
the UART will disable transmission as soon as any current  
character transmission is complete. Status bits ISR[4] and  
ASR[0] will be set. A level 5 interrupt will occur if enabled  
by IER[5]. The UART will then compare all received data  
with XON1 or XON2 characters to detect an XON  
condition. When this occurs, the UART will re-enable  
transmission and status bits ISR[4] and ASR[0] will be  
cleared.  
When automatic RTS flow control is enabled, the RTS# pin  
will be forced inactive when the RFL reaches the upper  
trigger level and will return to active when the RFL falls  
below the lower trigger level. The automatic RTS# flow  
control is ANDed with MCR[1] and hence is only  
operational when MCR[1]=1. This allows the software  
driver to override the automatic flow control and disable the  
remote transmitter regardless by setting MCR[1]=0 at any  
time.  
Automatic DTR/DSR flow control behaves in the same  
manner as RTS/CTS flow control but is enabled by  
ACR[3:2], regardless of whether or not the UART is in  
Enhanced mode.  
Any valid XON/XOFF characters will not be written into the  
RHR. An exception to this rule occurs if special character  
detection is enabled and an XOFF2 character is received  
that is a valid XOFF. In this instance, the character will be  
written into the RHR.  
The received status (i.e. parity and framing) of XON/XOFF  
characters does not have to be valid for these characters to  
be accepted as valid matches.  
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14 BAUD RATE GENERATION  
DLM:DLL  
Divisor Word  
0x0900  
0x0300  
0x0180  
0x00C0  
0x0060  
0x0030  
0x0018  
0x000C  
0x0006  
0x0004  
0x0003  
0x0002  
0x0001  
Baud Rate  
(bits per second)  
14.1  
General Operation  
The UART contains a programmable baud rate generator  
that is capable of taking any clock input from DC to 60MHz  
(at 5V) and dividing it by any 16-bit divisor number from 1  
to 65535 written into the DLM (MSB) and DLL (LSB)  
registers. In addition to this, a clock prescaler register is  
provided which can further divide the clock by values in the  
range 1.0 to 31.875 in steps of 0.125. Also, a further  
feature is the Times Clock Register ‘TCR’ which allows the  
sampling clock to be set to any value between 4 and 16.  
50  
110  
300  
600  
1,200  
2,400  
4,800  
9,600  
19,200  
28,800  
38,400  
57,600  
115,200  
These clock options allow for highly flexible baud rate  
generation capabilities from almost any input clock  
frequency (up to 60MHz). The actual transmitter and  
receiver baud rate is calculated as follows:  
InputClock  
BaudRate =  
Table 15: Standard PC COM Port Baud Rate Divisors  
(assuming a 1.8432MHz crystal)  
SC * Divisor * prescaler  
Where:  
SC  
= Sample clock values defined in TCR[3:0]  
Divisor = DLL + ( 256 x DLM )  
Prescaler = 1 when MCR[7] = ‘0’ else:  
= M + ( N / 8 ) where:  
M
N
= CPR[7:3] (Integer part – 1 to 31)  
= CPR[2:0] (Fractional part – 0.000 to 0.875 )  
See next section for a discussion of the clock prescaler and  
times clock register.  
After a hardware reset, the prescaler is bypassed (set to 1)  
and TCR is set to 0x00 (i.e. SC = 16). Assuming this  
default configuration, the following table gives the divisors  
required to be programmed into the DLL and DLM registers  
in order to obtain various standard baud rates:  
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14.3 Times Clock Register ‘TCR’  
The TCR register is located at offset 0x02 of the ICR  
14.2 Clock Prescaler Register ‘CPR’  
The CPR register is located at offset 0x01 of the ICR  
The 16C550 and other compatible devices such as 16C650  
and 16C750 use a 16 times (16x) over-sampling channel  
clock. The 16x over-sampling clock means that the channel  
clock runs at 16 times the selected serial bit rate. It limits  
the highest baud rate to 1/16 of the system clock when  
using a divisor latch value of unity. However, the 16C950  
UART is designed in a manner to enable it to accept other  
multiplications of the bit rate clock. It can use values from  
4x to 16x clock as programmed in the TCR as long as the  
clock (oscillator) frequency error, stability and jitter are  
within reasonable parameters. Upon hardware reset the  
TCR is reset to 0x00 which means that a 16x clock will be  
used, for compatibility with the 16C550 and compatibles.  
The prescaler divides the system clock by any value in the  
range of 1 to “31 7/8” in steps of 1/8. The divisor takes the  
form “M + N/8”, where M is the 5 bit value defined in  
CPR[7:3] and N is the 3 bit value defined in CPR[2:0].  
The prescaler is by-passed and a prescaler value of ‘1’ is  
selected by default when MCR[7] = 0.  
MCR[7] is set to the complement of CLKSEL pin after a  
hardware reset but may be overwritten by software. Note  
however that since access to MCR[7] is restricted to  
Enhanced mode only, EFR[4] should first be set and then  
MCR[7] set or cleared as required.  
The maximum baud-rates available for various system  
clock frequencies at all of the allowable values of TCR are  
indicated in Table 18 on the following page. These are the  
values in bits-per-second (bps) that are obtained if the  
divisor latch = 0x01 and the Prescaler is set to 1.  
If CLKSEL is connected to ground or MCR[7] is set by  
software, the internal clock prescaler is enabled.  
Upon a hardware reset, CPR defaults to 0x20 (division-by-  
4). Compatibility with existing 16C550 baud rate divisors is  
maintained using either a 1.8432MHz clock with CLKSEL  
pin connected to VDD, or a 7.372MHz clock with CLKSEL  
connected to GND. In the latter case, clearing MCR[7]  
would bypass the prescaler and hence quadruple all  
selected baud rates (providing a maximum of 460.8kbps as  
opposed to 115.2kbps)  
The OX16C950 has the facility to operate at baud-rates up  
to 15 Mbps at 5V.  
The table below indicates how the value in the register  
corresponds to the number of clock cycles per bit. TCR[3:0]  
is used to program the clock. TCR[7:4] are unused and will  
return “0000” if read.  
For higher baud rates use a higher frequency clock, e.g.  
14.7456MHz, 18.432MHz, 32MHz, 40MHz or 60.0MHz.  
The flexible prescaler allows system designers to generate  
popular baud rates using clocks that are not integer  
multiples of the required rate. When using a non-standard  
clock frequency, compatibility with existing 16C550  
software drivers may be maintained with a minor software  
patch to program the on-board prescaler to divide the high  
frequency clock down to 1.8432MHz.  
TCR[3:0]  
Clock cycles per bit  
0000 to 0011  
0100 to 1111  
16  
4-15  
Table 16: TCR Sample Clock Configuration  
The use of TCR does not require the device to be in 650 or  
950 mode although only drivers that have been written to  
take advantage of the 950 mode features will be able to  
access this register. Writing 0x01 to the TCR will not switch  
the device into 1x isochronous mode, this is explained in  
the following section. (TCR has no effect in isochronous  
mode). If 0x01, 0x10 or 0x11 is written to TCR the device  
will operate in 16x mode.  
Table 17 on the following page gives the prescaler values  
required to operate the UARTs at compatible baud rates  
with various different crystal frequencies. Also given is the  
maximum available baud rates in TCR = 16 and TCR = 4  
modes with CPR = 1.  
Reading TCR will always return the last value that was  
written to it irrespective of mode of operation.  
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Clock  
Frequency  
(MHz)  
CPR value  
Effective Error from Max. Baud rate  
Max. Baud rate  
with CPR = 1,  
crystal  
frequency  
1.8432  
1.8432  
1.8432  
1.8432  
1.8417  
1.8462  
1.8391  
1.8433  
1.8824  
1.8432MHz  
with CPR = 1,  
TCR = 16  
115,200  
(%)  
0.00  
0.00  
0.00  
0.00  
0.08  
0.16  
0.22  
TCR = 4  
460,800  
1.8432  
7.3728  
14.7456  
18.432  
32.000  
33.000  
40.000  
50.000  
60.000*  
0x08 (1.000)  
0x20(4.000)  
460,800  
921,600  
1,843,200  
3,686,400  
4,608,000  
8,000,000  
8,250,000  
10,000,000  
12,500,000  
15,000,000  
0x80 (8.000)  
0x50 (10.000)  
0x8B(17.375)  
0x8F (17.875)  
0xAE (21.750)  
0xD9 (27.125)  
0xFF (31.875)  
1,152,000  
2,000,000  
2,062,500  
2,500,000  
3,125,000  
3,750,000  
0.01  
2.13  
Table 17: Example clock options and their assosiacted maximum baud rates  
Sampling TCR  
Clock Value  
System Clock (MHz)  
18.432  
1.8432  
7.372  
14.7456  
32  
40  
50  
60  
3.75M  
4.00M  
16  
15  
14  
13  
12  
11  
10  
9
0x00 115,200  
0x0F 122,880  
0x0E 131,657  
0x0D 141,785  
0x0C 153,600  
0x0B 167,564  
0x0A 184,320  
0x09 204,800  
0x08 230,400  
460,750 921,600  
1.152M  
2.00M  
2.50M 3.125M  
491,467 983,040 1,228,800 2,133,333 2,666,667 3,333,333  
526,571 1,053,257 1,316,571 2,285,714 2,857,143 3,571,429 4,285,714  
567,077 1,134,277 1,417,846 2,461,538 3,076,923 3,846,154 4,615,384  
614,333 1,228,800 1,536,000 2,666,667 3,333,333 4,166,667  
670,182 1,340,509 1,675,636 2,909,091 3,636,364 4,545,455 5,454545  
737,200 1,474,560 1,843,200 3.20M 4.00M 5.00M 6.00M  
819,111 1,638,400 2,048,000 3,555,556 4,444,444 5,555,556 6,666,667  
921,500 1,843,200 2,304,000 4.00M 5.00M 6.25M 7.50M  
5.00M  
8
7
0x07 263,314 1,053,143 2,106,514 2,633,143 4,571,429 5,714,286 7,142,857 8,571428  
0x06 307,200 1,228,667 2,457,600 3,072,000 5,333,333 6,666,667 8,333,333 10.00M  
6
5
0x05 368,640 1,474,400 2,949,120 3,686,400  
0x04 460,800 1,843,000 3,686,400 4,608,000  
6.40M  
8.00M 10.00M 12.00M  
4
8.00M 10.00M 12.50M 15.00M  
Table 18: Maximum Baud Rates Available at all ‘TCR’ Sampling Clock Values  
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14.4 Input Clock Options  
A system clock must be applied to XTLI pin on the device  
(or CLKSEL if selected by software). The speed of this  
clock determines the maximum baud rate at which the  
device can receive and transmit serial data. This maximum  
is equal to one sixteenth of the frequency of the system  
clock (Increasing to one quarter of this value if TCR=4 is  
used).  
necessarily an external source) where asynchronous  
framing is maintained using start, parity and stop-bits.  
However serial transmission and reception is synchronised  
to the 1x clock. In this mode asynchronous data may be  
transmitted at baud rates up to 60Mbps. The local 1x clock  
source can be asserted on the DTR# pin.  
Note that line drivers need to be capable of transmission at  
data rates twice the system clock used (as one cycle of the  
system clock corresponds to 1 bit of serial data). Also note  
that enabling modem interrupts is illegal in isochronous  
mode, as the clock signal will cause a continuous change  
to the modem status (unless masked in MDM register, see  
section 15.10).  
The industry standard system clock for PC COM ports is  
1.8432 MHz, limiting the maximum baud rate to 115.2  
Kbps. The OX16C95x UARTs support system clocks up to  
50MHz (60MHz for the OX16C950 at 5V) and its flexible  
baud rate generation hardware means that almost any  
frequency can be optionally scaled down for compatibility  
with standard devices.  
14.7 Crystal Oscillator Circuit  
The OX16C950 may be clocked by a crystal connected to  
XTLI and XTLO or directly from a clock source connected  
to the XTLI pin (or CLKSEL if selected by software). The  
circuit required to use the on-chip oscillator is shown  
opposite.  
Designers have the option of using either TTL clock  
modules or crystal oscillator circuits for system clock input,  
with minimal additional components. The following two  
sections describe how each can be connected.  
XTLO  
14.5 TTL Clock Module  
R2  
C1  
Using a TTL module for the system clock simply requires  
the module to be supplied with +5v power and GND  
connections. The clock output can then be connected  
directly to XTLI. XTLO should be left unconnected.  
R1  
XTLI  
C2  
VDD  
Figure 3: Crystal Oscillator Circuit  
CLOCK  
Frequency C1 (pF) C2 (pF)  
Range  
XTLI  
R1 (Ω)  
R2 (Ω)  
(MHz)  
1.8432 – 8  
8-60  
Figure 2: TTL Clock Module Connectivity  
68  
33-68  
22  
220K  
470R  
470R  
33 – 68 220K-2M2  
14.6 External 1x Clock Mode  
Table 19: Component Values  
The transmitter and receiver can accept an external clock  
applied to the RI# and DSR# pins respectively. The clock  
options are selected using the clock select register (CKS -  
see section 15.8). The transmitter and receiver may be  
configured to operate in 1x (Isochronous) mode by setting  
CKS[7] and CKS[3], respectively. In Isochronous mode,  
transmitter or receiver will use the 1x clock (usually but not  
Note:  
For better stability use a smaller value of R1. Increase  
R1 to reduce power consumption.  
The total capacitive load (C1 in series with C2) should  
be that specified by the crystal manufacturer (nominally  
16pF)  
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15 ADDITIONAL FEATURES  
ASR[5]: FIFOSEL  
This bit reflects the unlatched state of the FIFOSEL pin.  
15.1 Additional Status Register ‘ASR’  
ASR[0]: Transmitter disabled  
logic 0 ⇒ The transmitter is not disabled by in-band flow  
control.  
logic 1 ⇒ The receiver has detected an XOFF, and has  
disabled the transmitter.  
ASR[6]: FIFO size  
logic 0 ⇒ FIFOs are 16 deep if FCR[0] = 1.  
logic 1 ⇒ FIFOs are 128 deep if FCR[0] = 1.  
Note: If FCR[0] = 0, the FIFOs are 1 deep.  
This bit is cleared after a hardware reset or channel  
software reset. The software driver may write a 0 to this bit  
to re-enable the transmitter if it was disabled by in-band  
flow control. Writing a 1 to this bit has no effect.  
ASR[7]: Transmitter Idle  
logic 0 ⇒ Transmitter is transmitting.  
logic 1 ⇒ Transmitter is idle.  
ASR[1]: Remote transmitter disabled  
logic 0 ⇒ The remote transmitter is not disabled by in-  
band flow control.  
This bit reflects the state of the internal transmitter. It is set  
when both the transmitter FIFO and shift register are  
empty.  
logic 1 ⇒ The transmitter has sent an XOFF character,  
to disable the remote transmitter. (Cleared  
when a subsequent XON is sent).  
15.2 FIFO Fill levels ‘TFL & RFL’  
The number of characters stored in the THR and RHR can  
be determined by reading the TFL and RFL registers  
respectively. As the UART clock is asynchronous with  
respect to the processor, it is possible for the levels to  
change during a read of these FIFO levels. It is therefore  
recommended that the levels are read twice and compared  
to check that the values obtained are valid. The values  
should be interpreted as follows:  
This bit is cleared after a hardware reset or channel  
software reset. The software driver may write a 0 to this bit  
to re-enable the remote transmitter (an XON is  
transmitted). Writing a 1 to this bit has no effect.  
Note: The remaining bits (ASR[7:2]) of this register are read only  
ASR[2]: RTS  
This is the complement of the actual state of the RTS# pin  
when the device is not in loopback mode. The driver  
software can determine if the remote transmitter is disabled  
by RTS# out-of-band flow control by reading this bit. In  
loopback mode this bit reflects the flow control status rather  
than the pin’s actual state.  
1. The number of characters in the THR is no greater  
than the value read back from TFL.  
2. The number of characters in the RHR is no less than  
the value read back from RFL.  
15.3 Additional Control Register ‘ACR’  
ASR[3]: DTR  
The ACR register is located at offset 0x00 of the ICR  
This is the complement of the actual state of the DTR# pin  
when the device is not in loopback mode. The driver  
software can determine if the remote transmitter is disabled  
by DTR# out-of-band flow control by reading this bit. In  
loopback mode this bit reflects the flow control status rather  
than the pin’s actual state.  
ACR[0]: Receiver disable  
logic 0 ⇒ The receiver is enabled, receiving data and  
storing it in the RHR.  
logic 1 ⇒ The receiver is disabled. The receiver  
continues to operate as normal to maintain the  
framing synchronisation with the receive data  
stream but received data is not stored into the  
RHR. In-band flow control characters continue  
to be detected and acted upon. Special  
characters will not be detected.  
ASR[4]: Special character detected  
logic 0 ⇒ No special character has been detected.  
logic 1 ⇒ A special character has been received and is  
stored in the RHR.  
Changes to this bit will only be recognised following the  
completion of any data reception pending.  
This can be used to determine whether a level 5 interrupt  
was caused by receiving a special character rather than an  
XOFF. The flag is cleared following the read of the ASR.  
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ACR[1]: Transmitter disable  
ACR[5]: 950 mode trigger levels enable  
logic 0 ⇒ The transmitter is enabled, transmitting any  
data in the THR.  
logic 1 ⇒ The transmitter is disabled. Any data in the  
THR is not transmitted but is held. However,  
in-band flow control characters may still be  
transmitted.  
logic 0 ⇒  
Interrupts and flow control trigger levels are  
as described in FCR register and are  
compatible with 16C650/16C750 modes.  
16C950 specific enhanced interrupt and flow  
control trigger levels defined by RTL, TTL,  
FCL and FCH are enabled.  
logic 1 ⇒  
Changes to this bit will only be recognised following the  
completion of any data transmission pending.  
ACR[6]: ICR read enable  
logic 0 ⇒  
logic 1 ⇒  
The Line Status Register is readable.  
The Indexed Control Registers are readable.  
ACR[2]: Enable automatic DSR flow control  
logic 0 ⇒ Normal. The state of the DSR# line does not  
affect the flow control.  
logic 1 ⇒ Data transmission is prevented whenever the  
DSR# pin is held inactive high.  
Setting this bit will map the ICR set to the LSR location for  
reads. During normal operation this bit should be cleared.  
ACR[7]: Additional status enable  
This bit provides another automatic out-of-band flow control  
facility using the DSR# line.  
logic 0 ⇒  
Access to the ASR, TFL and RFL registers  
is disabled.  
logic 1 ⇒  
Access to the ASR, TFL and RFL registers  
is enabled.  
ACR[4:3]: DTR# line configuration  
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the  
transmitter 1x clock or the output of the baud rate  
generator (Nx clock) are asserted on the DTR# pin,  
otherwise the DTR# pin is defined as follows:  
When ACR[7] is set, the MCR and LCR registers are no  
longer readable but remain writable, and the TFL and RFL  
registers replace them in the memory map for read  
operations. The IER register is replaced by the ASR  
register for all operations. The software driver may leave  
this bit set during normal operation, since MCR, LCR and  
IER do not generally need to be read.  
logic [00] ⇒ DTR# is compatible with 16C450, 16C550,  
16C650 and 16C750 (i.e. normal).  
logic [01] ⇒ DTR# pin is used for out-of-band flow  
control. It will be forced inactive high if the  
Receiver FIFO Level (‘RFL’) reaches the  
upper flow control threshold. DTR# line will  
be re-activated when the RFL drops below  
the lower threshold (see FCL & FCH).  
logic [10] ⇒ DTR# pin is configured to drive the active  
low enable pin of an external RS485 buffer.  
In this configuration the DTR# pin will be  
forced low whenever the transmitter is not  
empty (LSR[6]=0), otherwise DTR# pin is  
high.  
logic [11] ⇒ DTR# pin is configured to drive the active-  
high enable pin of an external RS485 buffer.  
In this configuration, the DTR# pin will be  
forced high whenever the transmitter is not  
empty (LSR[6]=0), otherwise DTR# pin is  
low.  
If the user sets ACR[4], then the DTR# line is controlled by  
the status of the transmitter empty bit of LCR. When  
ACR[4] is set, ACR[3] is used to select active high or active  
low enable signals. In half-duplex systems using RS485  
protocol, this facility enables the DTR# line to directly  
control the enable signal of external 3-state line driver  
buffers. When the transmitter is empty the DTR# would go  
inactive once the SOUT line returns to it’s idle marking  
state.  
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receiver FIFO exceeds the upper trigger level defined by  
FCR[7:6] as described in section 8.1. An XON is then sent  
when the FIFO is read down to the lower fill level. The flow  
control is enabled and the appropriate mode selected using  
EFR[3:0].  
15.4 Transmitter Trigger Level ‘TTL’  
The TTL register is located at offset 0x04 of the ICR  
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4  
and 5 of FCR are ignored and an alternative arbitrary  
transmitter interrupt trigger level can be defined in the TTL  
register. This 7-bit value provides a fully programmable  
transmitter interrupt trigger facility. In 950 mode, a priority  
level 3 interrupt occurs indicating that the transmitter buffer  
requires more characters when the interrupt is not masked  
(IER[1]=1) and the transmitter FIFO level falls below the  
value stored in the TTL register. The value 0 (0x00) has a  
special meaning. In 950 mode when the user writes 0x00  
to the TTL register, a level 3 interrupt only occurs when the  
FIFO and the transmitter shift register are both empty and  
the SOUT line is in the idle marking state. This feature is  
particularly useful to report back the empty state of the  
transmitter after its FIFO has been flushed away.  
In 950 mode, the flow control thresholds defined by  
FCR[7:6] are ignored. In this mode threshold levels are  
programmed using FCL and FCH. When in-band flow  
control is enabled (defined by EFR[3:0]) and the receiver  
FIFO level (‘RFL’) reaches the value programmed in the  
FCH register, an XOFF is transmitted to stop the flow of  
serial data . The flow is resumed when the receiver FIFO  
fill level falls to below the value programmed in the FCL  
register, at which point an XON character is sent. The FCL  
value of 0x00 is illegal.  
For example if FCL and FCH contain 64 and 100  
respectively, XOFF is transmitted when the receiver FIFO  
contains 100 characters, and XON is transmitted when  
sufficient characters are read from the receiver FIFO such  
that there are 63 characters remaining.  
15.5 Receiver Interrupt. Trigger Level ‘RTL’  
The RTL register is located at offset 0x05 of the ICR  
CTS/RTS and DSR/DTR out-of-band flow control use the  
same trigger levels as in-band flow control. When out-of-  
band flow control is enabled, RTS# (or DTR#) line is de-  
asserted when the receiver FIFO level reaches the upper  
limit defined in the FCH and is re-asserted when the  
receiver FIFO is drained below the lower limit defined in  
FCL. When 950 trigger levels are enabled (ACR[5]=1), the  
CTS# flow control functions as in 650 mode and is  
configured by EFR[7]. However, when EFR[6] is set, RTS#  
is automatically de-asserted when RFL reaches FCH and  
re-asserted when RFL drops below FCL.  
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6  
and 7 of FCR are ignored and an alternative arbitrary  
receiver interrupt trigger level can be defined in the RTL  
register. This 7-bit value provides a fully programmable  
receiver interrupt trigger facility as opposed to the limited  
trigger levels available in 16C650 and 16C750 devices. It  
enables the system designer to optimise the interrupt  
performance hence minimising the interrupt overhead.  
In 950 mode, a priority level 2 interrupt occurs indicating  
that the receiver data is available when the interrupt is not  
masked (IER[0]=1) and the receiver FIFO level reaches the  
value stored in this register.  
DSR# flow control is configured with ACR[2]. DTR# flow  
control is configured with ACR[4:3].  
15.7 Device Identification Registers  
15.6 Flow Control Levels ‘FCL & FCH’  
The identification registers is located at offsets 0x08 to 0x0B  
of the ICR  
The FCL and FCH registers are located at offsets 0x06 and  
0x07 of the ICR respectively  
The OX16C950 offers four bytes of device identification.  
The device ID registers may be read using offset values  
0x08 to 0x0B of the Indexed Control Register. Registers  
ID1, ID2 and ID3 identify the device as an OX16C950 and  
return 0x16, 0xC9 and 0x50 respectively. The REV register  
resides at offset 0x0B of ICR and identifies the revision of  
950 core. This register returns 0x03 for revision B of the  
OX16C950.  
Enhanced software flow control using XON/XOFF and  
hardware flow control using RTS#/CTS# and DTR#/DSR#  
are available when 950 mode trigger levels are enabled  
(ACR[5]=1). Improved flow control threshold levels are  
offered using Flow Control Lower trigger level (‘FCL’) and  
Flow Control Higher trigger level (‘FCH’) registers to  
provide a greater degree of flexibility when optimising the  
flow control performance. Generally, these facilities are  
only available in Enhanced mode.  
In 650 mode, in-band flow control is enabled using the EFR  
register. An XOFF character is transmitted when the  
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CKS[6]: Transmitter clock source selector  
logic 0 ⇒  
The transmitter clock source is the output of  
the baud rate generator (550 compatibility).  
The transmitter uses an external clock  
applied to the RI# pin.  
15.8 Clock Select Register ‘CKS’  
The CKS register is located at offset 0x03 of the ICR  
logic 1 ⇒  
This register is cleared to 0x00 after a hardware reset to  
maintain compatibility with 16C550, but is unaffected by  
software reset. This allows the user to select a clock  
source and then reset the channel to work-around any  
timing glitches.  
CKS[7]: Transmitter 1x clock mode selector  
logic 0 ⇒  
The transmitter is in Nx clock mode as  
defined in the TCR register. After  
a
hardware reset the transmitter operates in  
16x clock mode, i.e. 16C550 compatibility.  
The transmitter is in isochronous 1x clock  
mode.  
CKS[1:0]: Receiver Clock Source Selector  
logic [00] ⇒ The RCLK pin is selected for the receiver  
clock (550 compatible mode).  
logic 1 ⇒  
logic [01] ⇒ The DSR# pin is selected for the receiver  
clock.  
15.9 Nine-bit Mode Register ‘NMR’  
logic [10] ⇒ The output of baud rate generator (internal  
BDOUT#) is selected for the receiver clock.  
logic [11] ⇒ The transmitter clock is selected for the  
receiver. This allows RI# to be used for both  
transmitter and receiver.  
The NMR register is located at offset 0x0D of the ICR  
The OX16C950 offers 9-bit data framing for industrial multi-  
drop applications. 9-bit mode is enabled by setting bit 0 of  
the Nine-bit Mode Register (NMR). In 9-bit mode the data  
length setting in LCR[1:0] is ignored. Furthermore as parity  
is permanently disabled, the setting of LCR[5:3] is also  
ignored.  
CKS[2]: Disable BDOUT# pin  
logic 0 ⇒  
The BDOUT# pin is enabled and connected  
to the output of the internal baud rate  
generator which is a Nx clock used by the  
UART. In 16C550 compatibility mode, the  
baud rate generator produces a 16x clock  
(See TCR, section 14.3).  
The receiver stores the 9th bit of the received data in  
LSR[2] (where parity error is stored in normal mode). Note  
that OX16C950 provides a 128-deep FIFO for LSR[3:1].  
The transmitter FIFO is 9-bit wide and 128 deep. The user  
should write the 9th (MSB) data bit in SPR[0] first and then  
write the other 8 bits to THR.  
logic 1 ⇒  
The BDOUT# pin is disabled and set  
permanently low.  
As parity mode is disabled, LSR[7] is set whenever there is  
an overrun, framing error or received break condition. It is  
unaffected by the contents of LSR[2] (Now the received 9th  
data bit).  
CKS[3]: Receiver 1x clock mode selector  
logic 0 ⇒  
The receiver is in Nx clock mode as defined  
in the TCR register. After a hardware reset  
the receiver operates in 16x clock mode, i.e.  
16C550 compatibility.  
In 9-bit mode, in-band flow control is disabled regardless of  
the setting of EFR[3:0] and the XON1/XON2/XOFF1 and  
XOFF2 registers are used for special character detection.  
logic 1 ⇒  
The receiver is in isochronous 1x clock  
mode.  
CKS[5:4]: Transmitter 1x clock or baud rate generator  
output (BDOUT) on DTR# pin  
logic [00] ⇒ The function of the DTR# pin is defined by  
the setting of ACR[4:3].  
logic [01] ⇒ The transmitter 1x clock (bit rate clock) is  
asserted on the DTR# pin and the setting of  
ACR[4:3] is ignored.  
logic [10] ⇒ The output of baud rate generator (Nx clock)  
is asserted on the DTR# pin and the setting  
of ACR[4:3] is ignored.  
Interrupts in 9-Bit Mode:  
While IER[2] is set, upon receiving a character with status  
error, a level 1 interrupt is asserted when the character and  
the associated status are transferred to the FIFO.  
The OX16C950 can assert an optional interrupt if a  
received character has its 9th bit set. As multi-drop systems  
often use the 9th bit as an address bit, the receiver is able  
to generate an interrupt upon receiving an address  
character. This feature is enabled by setting NMR[2]. This  
will result in a level 1 interrupt being asserted when the  
address character is transferred to the receiver FIFO.  
logic [11] ⇒ Reserved.  
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In this case, as long as there are no errors pending, i.e.  
LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back  
from LSR[7] and LSR[1], thus differentiating between an  
‘address’ interrupt and receiver error or overrun interrupt in  
9-bit mode. Note however that should an overrun or error  
interrupt actually occur, an address character may also  
reside in the FIFO. In this case, the software driver should  
examine the contents of the receiver FIFO as well as  
process the error.  
15.10 Modem Disable Mask ‘MDM’  
The MDM register is located at offset 0x0E of the ICR  
This register is cleared after a hardware reset to maintain  
compatibility with 16C550. It allows the user to mask  
interrupts and control sleep operation due to individual  
modem lines or the serial input line.  
MDM[0]: Disable delta CTS  
logic 0 ⇒ Delta CTS is enabled. It can generate a level 4  
interrupt when enabled by IER[3]. Delta CTS  
can wake up the UART when it is asleep under  
auto-sleep operation.  
logic 1 ⇒ Delta CTS is disabled. It can not generate an  
interrupt or wake up the UART.  
The above facility produces an interrupt for recognizing any  
‘address’ characters. Alternatively, the user can configure  
OX16C950 to match the receiver data stream with up to  
four programmable 9-bit characters and assert a level 5  
interrupt after detecting a match. The interrupt occurs when  
the character is transferred to the FIFO (See below).  
MDM[1]: Disable delta DSR  
logic 0 ⇒ Delta DSR is enabled. It can generate a level 4  
interrupt when enabled by IER[3]. Delta DSR  
can wake up the UART when it is asleep under  
auto-sleep operation.  
logic 1 ⇒ Delta DSR is disabled. In can not generate an  
interrupt or wake up the UART.  
NMR[0]: 9-bit mode enable  
logic 0 ⇒  
logic 1 ⇒  
9-bit mode is disabled.  
9-bit mode is enabled.  
NMR[1]: Enable interrupt when 9th bit is set  
MDM[2]: Disable Trailing edge RI  
logic 0 ⇒  
Receiver interrupt for detection of an  
‘address’ character (i.e. 9th bit set) is  
disabled.  
logic 0 ⇒ Trailing edge RI is enabled. It can generate a  
level 4 interrupt when enabled by IER[3].  
Trailing edge RI can wake up the UART when it  
is asleep under auto-sleep operation.  
logic 1 ⇒ Trailing edge RI is disabled. In can not generate  
an interrupt or wake up the UART.  
logic 1 ⇒  
Receiver interrupt for detection of an  
‘address’ character (i.e. 9th bit set) is  
enabled and a level 1 interrupt is asserted.  
MDM[3]: Disable delta DCD  
Special Character Detection  
logic 0 ⇒ Delta DCD is enabled. It can generate a level 4  
interrupt when enabled by IER[3]. Delta DCD  
can wake up the UART when it is asleep under  
auto-sleep operation.  
logic 1 ⇒ Delta DCD is disabled. In can not generate an  
interrupt or wake up the UART.  
While the UART is in both 9-bit mode and Enhanced mode,  
setting IER[5] will enable detection of up to four ‘address’  
characters. The least significant eight bits of these four  
programmable characters are stored in special characters  
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)  
registers and the 9th bit of these characters are  
programmed in NMR[5] to NMR[2] respectively.  
MDM[7:4]: Reserved  
These bits must be set to ‘0000’  
NMR[2]: Bit 9 of Special Character 1  
NMR[3]: Bit 9 of Special Character 2  
NMR[4]: Bit 9 of Special Character 3  
NMR[5]: Bit 9 of Special Character 4  
15.11 Readable FCR ‘RFC’  
The RFC register is located at offset 0x0F of the ICR  
This read-only register returns the current state of the FCR  
register (Note that FCR is write-only). This register is  
included for diagnostic purposes.  
NMR[7:6]: Reserved  
Bits 6 and 7 of NMR are always cleared and reserved for  
future use.  
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logic 1 ⇒  
RxRdy# is permanently inactive (high)  
regardless of FIFO thresholds  
DMA[7]: Force TxRdy Inactive  
15.12 Good-data status register ‘GDS’  
The GDS register is located at offset 0x10 of the ICR  
Good data status is set when the following conditions are  
true:  
logic 0 ⇒  
logic 1 ⇒  
TxRdy# acts normally  
TxRdy# is permanently inactive (high)  
regardless of FIFO thresholds.  
•
•
•
ISR reads level0 (no interrupt), level2 or 2a  
(receiver data) or level3 (THR empty) interrupt.  
LSR[7] is clear i.e. no parity error, framing error  
or break in the FIFO.  
15.14 Port Index Register ‘PIX’  
The PIX register is located at offset 0x12 of the ICR. This  
read-only register gives the UART index. For a single  
channel device such as the OX16C950 this reads ‘0’.  
LSR[1] is clear i.e. no overrun error has occurred.  
GDS[0]: Good Data Status  
GDS[7:1]: Reserved  
15.15 Clock Alteration Register ‘CKA’  
The CKA register is located at offset 0x13 of the ICR. This  
register adds additional clock control mainly for  
isochronous and embedded applications. The register is  
effectively an enhancement to the CKS register.  
This register is cleared to 0x00 after a hardware reset to  
maintain compatibility with 16C550, but is unaffected by  
software reset. This allows the user to select a clock mode  
and then reset the channel to work-around any timing  
glitches.  
15.13 DMA Status Register ‘DMS’  
The DMS register is located at offset 0x11 of the ICR. This  
allows the TXRDY# and RXRDY# lines to be permanently  
deasserted, and the current internal status to be monitored.  
This mainly has applications for testing.  
DMS[0]: RxRdy Status  
Read Only: set when RxRdy is asserted (pin driven low).  
DMS[1]: TxRdy Status  
Read Only: set when TxRdy is asserted (pin driven low).  
DMS[5:2] Reserved  
DMS[6]: Force RxRdy Inactive  
logic 0 ⇒  
RxRdy# acts normally  
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16 OPERATING CONDITIONS  
Symbol  
VDD  
VIN  
IIN  
TSTG  
Parameter  
Min.  
-0.3  
-0.3  
Max.  
Units  
V
V
mA  
°C  
DC supply voltage  
DC input voltage  
DC input current  
Storage temperature  
7.0  
VDD + 0.3  
+/- 10  
125  
-40  
Table 20: Absolute Maximum Ratings  
Symbol  
VDD  
Parameter  
DC supply voltage  
Operating Temperature range  
Min  
3
0
Max  
5.25  
70  
Units  
V
°C  
TO  
Table 21: Recommended Operating Conditions  
17 DC ELECTRICAL CHARACTERISTICS  
17.1 5V Operation  
.
Symbol  
VDD  
VIH  
Parameter  
Supply voltage  
Input high voltage  
Condition  
Commercial  
TTL Interface Note1  
TTL Schmitt trigger  
TTL Interface Note 1  
TTL Schmitt trigger  
Min.  
4.75  
2.0  
Max.  
5.25  
Units  
V
V
2.4  
VIL  
Input low voltage  
0.8  
0.6  
5.0  
10.0  
10  
V
CIL  
COL  
IIH  
Capacitance of input buffers  
Capacitance of output buffers  
Input high leakage current  
Input low leakage current  
Output high voltage  
Output high voltage  
Output low voltage  
Output low voltage  
3-state output leakage current  
pF  
pF  
μA  
μA  
V
V
V
V
Vin = VDD  
Vin = VSS  
-10  
-10  
DD – 0.05  
IIL  
10  
VOH  
VOH  
VOL  
VOL  
IOZ  
V
IOH = 1 μA  
IOH = 4 mA Note2  
IOL = 1 μA  
2.4  
0.05  
0.4  
10  
IOL = 4 mA Note2  
-10  
45  
μA  
μA  
mA  
IST  
ICC  
Static current  
Vin = VDD or VSS  
100  
Operating supply current in fCK = 1.8432 MHz  
normal mode Note3  
0.40  
1.50  
10.0  
0.35  
1.25  
3.5  
2.0  
5.0  
30.0  
0.5  
2.0  
5.0  
f
f
CK = 7.372 MHz  
CK = 60.00 MHz  
Operating supply current in sleep fCK = 1.8432 MHz  
mode Note3  
fCK = 7.372 MHz  
CK = 60.00 MHz  
f
Table 22: DC Electrical Characteristics  
Note 1: All input buffers are TTL with the exception of RESET which is a Schmitt trigger buffer.  
Note 2: and I are 12 mA for DB[7:0] and 4 mA for all other outputs.  
I
OH  
OL  
Note 3: For further details on operating current please refer to the’OX16C95x Test Document’.  
DS-0031 Sep 05  
External—Free Release  
Page 41  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
17.2 3V Operation  
These figures assume the TQFP package, with VSEL applied for 3V operation.  
Symbol  
VDD  
VIH  
Parameter  
Supply voltage  
Input high voltage  
Condition  
Commercial  
TTL Interface Note1  
TTL Schmitt trigger  
TTL Interface Note 1  
TTL Schmitt trigger  
Min.  
3.0  
0.7 VDD  
TBD  
-0.5  
Max.  
Units  
V
V
3.45  
VDD + 0.5  
TBD  
0.2 VDD  
TBD  
5.0  
10.0  
1
1
VIL  
Input low voltage  
V
TBD  
CIL  
COL  
IIH  
Capacitance of input buffers  
Capacitance of output buffers  
Input high leakage current  
Input low leakage current  
Output high voltage  
Output high voltage  
Output low voltage  
Output low voltage  
3-state output leakage current  
Static current  
pF  
pF  
μA  
μA  
V
V
V
V
Vin = VDD  
Vin = VSS  
-1  
-1  
IIL  
VOH  
VOH  
VOL  
VOL  
IOZ  
V
DD – 0.05  
2.4  
IOH = 1 μA  
IOH = 4 mA Note2  
IOL = 1 μA  
0.05  
0.4  
1
100  
TBD  
IOL = 4 mA Note2  
-1  
45  
TBD  
μA  
μA  
mA  
IST  
ICC  
Vin = VDD or VSS  
Operating supply current in fCK = 1.8432 MHz  
normal mode Note3  
f
f
CK = 7.372 MHz  
CK = 60.00 MHz  
Operating supply current in sleep fCK = 1.8432 MHz  
TBD  
TBD  
mode Note3  
fCK = 7.372 MHz  
CK = 60.00 MHz  
f
Table 23: DC Electrical Characteristics  
Note 1: All input buffers are TTL with the exception of RESET which is a Schmitt trigger buffer.  
Note 2: and I are 6 mA for DB[7:0] and 2 mA for all other outputs.  
I
OH  
OL  
Note 3: For further details on operating current please refer to the’OX16C95x Test Document’.  
DS-0031 Sep 05  
External—Free Release  
Page 42  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
18 AC ELECTRICAL CHARACTERISTICS  
18.1 5V Operation  
Symbol  
Parameter  
Min  
Max  
Units  
tsa  
Address set-up time to IOR# or IOW# falling  
Address set-up time to IOR or IOW rising  
Address hold time after IOR# or IOW# rising Note1  
Address hold time after IOR or IOW falling Note1  
Chip select set-up time to IOR# or IOW# falling  
Chip select set-up time to IOR or IOW rising  
Chip select hold time after IOR# or IOW# rising Note1  
Chip select hold time after IOR or IOW falling Note1  
Pulse duration of IOR# or IOR  
Delay between IOR# rising and IOR#/IOW# falling  
Delay between IOR falling and IOR/IOW rising  
Access time; Data valid after IOR# falling or IOR rising  
Data bus floating after IOR# rising or IOR rising  
Pulse duration of IOW# or IOW  
Delay between IOW# rising and IOR# /IOW# falling  
Delay between IOW falling and IOR/IOW rising  
Data set-up time to IOW# rising or IOW falling  
Data hold time after IOW# rising or IOW falling  
Address and chip select set-up time to ADS#  
rising Note2  
0
ns  
tha  
tsc  
thc  
0
0
0
ns  
ns  
ns  
ns  
tr1  
tr2  
25  
38  
tacc  
tdf  
tw1  
tw2  
20  
10  
ns  
ns  
ns  
ns  
25  
38  
tsd  
thd  
tsac  
0
3
0
ns  
ns  
ns  
thac  
Address and chip select hold time after ADS#  
2
2
1
3
0
ns  
rising Note2  
ta1  
thad  
tirs  
Pulse duration of ADS# Note2  
ns  
ns  
ns  
IOR#/IOW# rising or IOR/IOW falling to ADS# falling Note3  
SIN set-up time to Isochronous input clock ‘Rx_Clk_In  
rising Note4  
tirh  
tits  
SIN hold time after Isochronous input clock ‘Rx_Clk_In’  
rising Note4  
SOUT valid after Isochronous output clock ‘Tx_Clk_Out’  
falling Note4  
ns  
ns  
4
Table 24: AC Electrical Characteristics  
Note 1: tha and thc timing constrains only apply to non-multiplexed arrangement where ADS# is permanently tied low.  
Note 2: ADS# signal may be tied low if address is stable during read or write cycles.  
Note 3: thad, ta1 and tsac timing constrains only apply to multiplexed arrangement where ADS# is used.  
Note 4: In Isochronous mode, transmitter data is available after the falling edge of the x1 clock and the receiver data is sampled using the  
rising edge of the x1 clock. The system designer is should ensure that mark-to-space ratio of the x1 clock is such that the required  
set-up and hold timing constraint are met. One way of achieving this is to choose a crystal frequency which is twice the required data  
rate and then divide the clock by two using the on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of  
set-up and hold calculations.  
DS-0031 Sep 05  
External—Free Release  
Page 43  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
18.2 3V Operation  
N.B. Maximum frequency of operation is downgraded under 3V operation to 50 MHz.  
Symbol  
Parameter  
Min  
Max  
Units  
tsa  
Address set-up time to IOR# or IOW# falling  
Address set-up time to IOR or IOW rising  
Address hold time after IOR# or IOW# rising Note1  
Address hold time after IOR or IOW falling Note1  
Chip select set-up time to IOR# or IOW# falling  
Chip select set-up time to IOR or IOW rising  
Chip select hold time after IOR# or IOW# rising Note1  
Chip select hold time after IOR or IOW falling Note1  
Pulse duration of IOR# or IOR  
Delay between IOR# rising and IOR#/IOW# falling  
Delay between IOR falling and IOR/IOW rising  
Access time; Data valid after IOR# falling or IOR rising  
Data bus floating after IOR# rising or IOR rising  
Pulse duration of IOW# or IOW  
Delay between IOW# rising and IOR# /IOW# falling  
Delay between IOW falling and IOR/IOW rising  
Data set-up time to IOW# rising or IOW falling  
Data hold time after IOW# rising or IOW falling  
Address and chip select set-up time to ADS#  
rising Note2  
0
ns  
tha  
tsc  
thc  
0
0
0
ns  
ns  
ns  
ns  
tr1  
tr2  
35  
45  
tacc  
tdf  
tw1  
tw2  
28  
12  
ns  
ns  
ns  
ns  
35  
45  
tsd  
thd  
tsac  
0
4
0
ns  
ns  
ns  
thac  
Address and chip select hold time after ADS#  
2
ns  
rising Note2  
ta1  
thad  
tirs  
Pulse duration of ADS# Note2  
3
45  
2
ns  
ns  
ns  
IOR#/IOW# rising or IOR/IOW falling to ADS# falling Note3  
SIN set-up time to Isochronous input clock ‘Rx_Clk_In  
rising Note4  
tirh  
tits  
SIN hold time after Isochronous input clock ‘Rx_Clk_In’  
4
0
ns  
ns  
rising Note4  
SOUT valid after Isochronous output clock ‘Tx_Clk_Out’  
falling Note4  
6
Table 25: AC Electrical Characteristics  
Note 1: tha and thc timing constrains only apply to non-multiplexed arrangement where ADS# is permanently tied low.  
Note 2: ADS# signal may be tied low if address is stable during read or write cycles.  
Note 3: thad, ta1 and tsac timing constrains only apply to multiplexed arrangement where ADS# is used.  
Note 4: In Isochronous mode, transmitter data is available after the falling edge of the x1 clock and the receiver data is sampled using the  
rising edge of the x1 clock. The system designer is should ensure that mark-to-space ratio of the x1 clock is such that the required  
set-up and hold timing constraint are met. One way of achieving this is to choose a crystal frequency which is twice the required data  
rate and then divide the clock by two using the on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of  
set-up and hold calculations.  
DS-0031 Sep 05  
External—Free Release  
Page 44  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
19 TIMING WAVEFORMS  
ADS#  
ta1  
thad  
tsac  
A[2:0]  
Address Valid  
thac  
tha  
tsa  
CS0  
CS1  
CS2#  
tsc  
thc  
tr1  
IOR#  
IOR  
De-asserted  
Asserted  
De-asserted  
tr2  
tdh  
tacc  
DB[7:0]  
Data Valid  
tdf  
Figure 4: Read Cycle Timing  
ADS#  
A[2:0]  
ta1  
thad  
tsac  
Address Valid  
thac  
tha  
tsa  
CS0  
CS1  
CS2#  
tsc  
thc  
tw  
1
IOW#  
IOW  
De-asserted  
Asserted  
De-asserted  
tw  
2
tsd  
DB[7:0]  
Data Valid  
thd  
Figure 5: Write Cycle Timing  
DS-0031 Sep 05  
External—Free Release  
Page 45  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
SIN  
tirs  
tirh  
Rx_Clk_In  
(DSR#)  
SOUT  
tits  
Tx_Clk_Out  
(DTR#)  
Figure 6: Isochronous Mode Timing  
DS-0031 Sep 05  
External—Free Release  
Page 46  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
20 PACKAGE INFORMATION  
OX16C950-PCC60-B  
Figure 7: 44 Pin Plastic Leaded Chip Carrier  
OX16C950-TQC60-B  
Figure 8: 48 Pin Thin Quad Flat Pack (48 TQFP)  
DS-0031 Sep 05  
External—Free Release  
Page 47  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
21 ORDERING INFORMATION  
OX16C950-PCC60-B  
Revision  
Operating Conditions -Commercial  
Package Type - 44 PLCC  
OX16C950-TQC60-B  
OX16C950-PLBG  
Revision  
Package Material - Plastic  
Package Type - 48 TQFP  
RoHS Compliant  
Revision  
Package Type - 44 PLCC  
OX16C950-TQBG  
RoHS Compliant  
Revision  
Package Type – 48 TQFP  
DS-0031 Sep 05  
External—Free Release  
Page 48  
OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
NOTES  
This page has intentionally been left blank.  
DS-0031 Sep 05  
External—Free Release  
Page 49  
CONTACT DETAILS  
Oxford Semiconductor Ltd.  
25 Milton Park  
Abingdon  
Oxfordshire  
OX14 4SH  
United Kingdom  
Telephone:  
Fax:  
Sales e-mail:  
Web site:  
+44 (0)1235 824900  
+44 (0)1235 821141  
sales@oxsemi.com  
http://www.oxsemi.com  
©Copyright Oxford Semiconductor Ltd 1998-2001  
Oxford Semiconductor Ltd believes the information contained in this document to be accurate and reliable. However, it is subject  
to change without notice. No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or  
other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the  
prior consent of Oxford Semiconductor Ltd. Oxford Semiconductor’s terms and conditions of sale apply at all times.  
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