NWK914D
When N10/100 is held low the 10Mb/s driver is selected.
This 10Mb/s driver consists of a differential analog buffer
designed to take a fully cable conditioned 10Mb/s signal
from the filter output of existing 10BASE-T electronics. The
10BASE-T signal is input on pins 10TXIN and 10TXIP. The
output current of the buffer is determined by the same
external RREF resistor on pin TXREF as used for the 100Mb/
s driver.
Base Line Wander Correction
MLT-3 codes have significant low frequency components
in their spectrum which are not transmitted through the
transformers that couple the line to the board. This results in
'Base Line Wander', which can significantly reduce the
noise immunity of the receiver.
The purpose ot the correction circuit is to restore these
low frequency components through the use of a feedback
arrangement. The circuit will also correct any DC offset that
may exist on the receive signal.
The unselected driver is switched to a tristated power
save mode. A low voltage shutdown circuit turns off both TX
drivers when VCC voltage falls to a level below the specified
minimum.
Signal Detector
When operating in single 100Mb/s applications a 1:1
turn ratio magnetics will be used and therefore to attain the
desired line driving current of 40mA out of the secondary a
TXO output drive of 40mA is required. Using the above
formula it will be found that 1.3Ω is the nearest prefered
value to that required to give the 40mA.
A signal detect circuit is provided which continuously
monitors the amplitude of the input signal being received on
pins RXIP and RXIN. After the input signal reaches the
specified level which the equalizer can correctly equalize,
SDT is asserted high. Conversely if the signal level falls
below a limit for reliable operation then SDT will go low.
In the case of dual 10Mb/s and 100Mb/s applications a
2:1 turn ratio magnetics is recommended. The use of 2:1
magnetics enables a greater efficiency to be gained from
the 10Mb/s driver by using a lower output current. At the
same time this lower current is also true of the 100Mb/s
output where now only a 20mA drive is required. An RREF
value of 2.6KΩ is used to set this current. Internal current
ratioing within the device will ensure that the correct drive
current is chosen depending upon whether the drives are in
10Mb/s or 100Mb/s mode as selected by pin N10/100.
Comparators MLT-3 to NRZ Decoder
The equalized MLT-3 data is then passed to a set of
window comparators which are used to determine the signal
level. The comparator outputs are OR’ed together to
reconstitute the NRZI data.
PLL Clock Recovery
This function consists of a 125MHz PLL that is locked to
the incoming data stream. The PLL is first centred to the
transmit clock multiplier using an internal analog reference
signal. Once a valid input signal is present, the PLL will lock
to, and thus extract the clock from, the incoming data
stream. Pins LFRA and LFRB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
The RREF value can be adjusted to compensate for
different magnetics and board layouts. The object is to
achieve an output level of 2V p-p measured at the RJ45
socket in compliance with 802.3.
When the TXOE pin is held low the TXdrivers are tri-
stated regardless of the mode selected by the N10/100 pin.
125MHz Shifter to Parallel Data
Receiver Section
Equalizer
The 125Mb/s serial data stream with an accompanying
phase related 125MHz clock is output from the PLL.
This data stream is clocked into the serial to parallel
register using the 125MHz clock. This data is then latched
prior to being clocked out on pins RDAT0 to RDAT4. A
25MHz clock, derived from the 125MHz PLL by a divide by
5, is used to clock the parallel data and is output to pin RXC.
The equalizer circuit is necessary to compensate for
signal degradation due to cable losses, however over-
equalization must be avoided to prevent excessive overshoots
resulting in errors during the reception of MLT-3 data. Three
operating modes are therefore provided.
Loopback Logic
These three operating modes are controlled by the state
of tristate input 'EQSEL' and are described below:-
Pin ‘LBEN’ controls loopback operation. A low level on
this pin defines normal operation, a high level defines
loopback mode. In loopback mode, the transmit data is
internally routed to the receive circuitry, SDT is forced high
and the TXOP and TXON outputs are disabled.
1) Auto Equalization ('EQSEL' floating)
Fully automatic equalization is achieved through the
use of a feedback loop driven by a control signal derived
from the signal amplitude. This provides adaptive control
and prevents over-modulation of the signal when short
cable lengths are used.
Test Pins and No-Connects
Two pins are provided on the product to aid testing in
production. These pins TEST(38), and TESTIP(37) must be
left unconnected for normal operation in application circuits.
2) Full Equalization ('EQSEL' low)
In this mode, full equalization is applied to the input
signal irrespective of amplitude.
Additionally, there are four No-Connect pins (2,3,7,8)
which also mustt be left unconnected for normal operation.
3) No Equalization ('EQSEL high)
The equalization circuit is disabled completely during
this mode.
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