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4X16E83V

型号：

4X16E83V

描述：

4梅格×16 EDO DRAM[ 4 MEG x 16 EDO DRAM ]

品牌：

ETC[ ETC ]

页数：

24 页

PDF大小：

581 K

下载PDF手册
4 MEG x 16  
EDO DRAM  
4X16E43V  
EDO DRAM  
FEATURES  
PIN ASSIGNMENT (To p Vie w )  
50-Pin TSOP  
• Sin gle +3.3V ±0.3V power supply  
• In dustry-stan dard x16 pin out, tim in g, fun ction s,  
an d package  
• 12 row, 10 colum n addresses (4)  
13 row, 9 colum n addresses (8)  
VCC  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
NC  
VCC  
WE#  
RAS#  
NC  
NC  
NC  
NC  
A0  
A1  
A2  
A3  
A4  
A5  
VCC  
1
2
3
4
5
6
7
8
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
VSS  
DQ15  
DQ14  
DQ13  
DQ12  
VSS  
DQ11  
DQ10  
DQ9  
DQ8  
NC  
• High -perform an ce CMOS silicon -gate process  
• All in puts, outputs an d clocks are LVTTL-com patible  
• Exten ded Data-Out (EDO) PAGE MODE access  
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH  
distributed across 64m s  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
• Self refresh for low-power data reten tion  
VSS  
CASL#  
CASH#  
OE#  
NC  
NC  
NC/A12†  
A11  
A10  
A9  
A8  
A7  
OPTIONS  
MARKING  
• Plastic Package  
50-pin TSOP (400 m il)  
TW  
• Tim in g  
50n s access  
60n s access  
-5  
-6  
A6  
VSS  
• Refresh Rates  
4K  
8K  
†A12 for " 8K" version, NC for " 4K" version.  
4
8
4X16E43V  
4 Meg x 16  
4X16E83V  
Configuration  
Refresh  
4 Meg x 16  
8K  
• Operatin g Tem perature Ran ge  
Com m ercial (0°C to +70°C)  
Exten ded (-40°C to +85°C)  
4K  
Non e  
IT  
Row Address  
Column Addressing  
4K (A0-A11)  
1K (A0-A9)  
8K (A0-A12)  
512 (A0-A8)  
NOTE: 1. The “#” symbol indicates signal is active LOW.  
4 MEG x 16 EDO DRAM PART NUMBERS  
Part Number Example:  
REFRESH  
MEM4X16E43VTW-5  
PART NUMBER  
ADDRESSING  
PACKAGE  
4X16E43VTW-x  
4X16E83VTW-x  
4
8
400-TSOP  
400-TSOP  
KEY TIMING PARAMETERS  
SPEED  
t RC  
84ns  
104ns  
t RAC  
50ns  
60ns  
t PC  
20ns  
25ns  
t AA  
25ns  
30ns  
t CAC  
13ns  
15ns  
t CAS  
8ns  
x = speed  
-5  
-6  
10ns  
1
4 MEG x 16  
EDO DRAM  
FUNCTIONAL BLOCK DIAGRAM  
4X16E43V (12 row addresses)  
WE#  
CASL#  
CASH#  
CAS#  
16  
16  
DATA-IN BUFFER  
DQ0-  
DQ15  
DATA-OUT  
NO. 2 CLOCK  
BUFFER  
GENERATOR  
OE#  
16  
16  
COLUMN-  
ADDRESS  
BUFFER(10)  
COLUMN  
DECODER  
10  
10  
1,024  
REFRESH  
CONTROLLER  
SENSE AMPLIFIERS  
I/O GATING  
A0-  
1,024 x 16  
A11  
REFRESH  
COUNTER  
12  
4,096 x 1,024 x 16  
MEMORY  
ROW-  
ADDRESS  
4,096 x 16  
12  
4,096  
12  
ARRAY  
BUFFERS (12)  
NO. 1 CLOCK  
GENERATOR  
RAS#  
VDD  
VSS  
FUNCTIONAL BLOCK DIAGRAM  
4X16E83V (13 row addresses)  
WE#  
CASL#  
CASH#  
CAS#  
16  
DATA-IN BUFFER  
DQ0-  
DQ15  
16  
DATA-OUT  
BUFFER  
NO. 2 CLOCK  
GENERATOR  
OE#  
16  
16  
COLUMN-  
ADDRESS  
BUFFER(9)  
COLUMN  
DECODER  
9
9
512  
REFRESH  
CONTROLLER  
SENSE AMPLIFIERS  
I/O GATING  
A0-  
A12  
512 x 16  
REFRESH  
COUNTER  
13  
8192 x 512 x 16  
MEMORY  
ARRAY  
ROW-  
ADDRESS  
8192 x 16  
13  
8192  
13  
BUFFERS (13)  
NO. 1 CLOCK  
GENERATOR  
RAS#  
Vcc  
Vss  
2
4 MEG x 16  
EDO DRAM  
GENERAL DESCRIPTION  
Th e 4 Meg x 16 DRAM is a h igh -speed CMOS,  
dyn am ic ran dom -access m em ory device con tain in g  
67,108,864 bits an d design ed to operate from 3V to  
3.6V. Th e device is fun ction ally organ ized as 4,194,304  
location s con tain in g 16 bits each . Th e 4,194,304  
m em ory location s are arran ged in 4,096 rows by 1,024  
colum n s on th e MEM4X16E43VTW. Durin g READ or  
WRITE cycles, each location is un iquely addressed  
via th e address bits: 12 row-address bits (A0-A11)  
an d 10 colum n -address bits (A0-A9) on th e  
th e last to tran sition back HIGH. Th e CAS# fun ction al-  
ity an d tim in g related to drivin g or latch in g data is such  
th at each CAS# sign al in depen den tly con trols th e asso-  
ciated eigh t DQ pin s.  
Th e row address is latch ed by th e RAS# sign al, th en  
th e colum n address is latch ed by CAS#. Th is device  
provides EDO-PAGE-MODE operation , allowin g for fast  
successive data operation s (READ, WRITE or READ-  
MODIFY-WRITE) with in a given row.  
Th e 4 Meg x 16 DRAM m ust be refresh ed periodi-  
cally in order to retain stored data.  
MEM4X16E43VTW version . In addition , th e byte an d  
word accesses are supported via th e two CAS# pin s  
(CASL# an d CASH#).  
DRAM ACCESS  
Each location in th e DRAM is un iquely addressable,  
as m en tion ed in th e Gen eral Description . Use of both  
CAS# sign als results in a word access via th e 16 I/O pin s  
(DQ0-DQ15). Usin g on ly on e of th e two sign als results  
in a BYTE access cycle. CASL# tran sition in g LOW se-  
lects an access cycle for th e lower byte (DQ0-DQ7), an d  
CASH# tran sition in g LOW selects an access cycle for  
Th e CAS# fun ction ality an d tim in g related to ad-  
dress an d con trol fun ction s (e.g., latch in g colum n  
addresses or selectin g CBR REFRESH) is such th at th e  
in tern al CAS# sign al is determ in ed by th e first extern al  
CAS# sign al (CASL# or CASH#) to tran sition LOW an d  
WORD WRITE  
LOWER BYTE WRITE  
RAS#  
CASL#  
CASH#  
WE#  
STORED  
INPUT  
INPUT  
DATA  
STORED STORED  
INPUT  
INPUT  
DATA  
STORED  
DATA  
DATA  
DATA  
DATA  
DATA  
DATA  
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
LOWER BYTE  
(DQ0-DQ7)  
OF WORD  
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE  
(DQ8-DQ15)  
OF WORD  
ADDRESS 0  
X = NOT EFFECTIVE (DON?T CARE)  
ADDRESS 1  
Fig u re 1  
WORD a n d BYTE WRITE Exa m p le  
3
4 MEG x 16  
EDO DRAM  
DRAM ACCESS (co n t in u e d )  
th e upper byte (DQ8-DQ15). Gen eral byte an d word  
access tim in g is sh own in Figures 1 an d 2.  
WRITE on th e oth er byte are n ot allowed durin g th e  
sam e cycle. However, an EARLY WRITE on on e byte an d  
a LATE WRITE on th e oth er byte, after a CAS# prech arge  
h as been satisfied, are perm issible.  
A logic HIGH on WE# dictates read m ode, wh ile a  
logic LOW on WE# dictates write m ode. Durin g a  
WRITE cycle, data-in (D) is latch ed by th e fallin g edge  
of WE or CAS# (CASL# or CASH#), wh ich ever occurs  
last. An EARLY WRITE occurs wh en WE is taken LOW  
prior to eith er CAS# fallin g. A LATE WRITE or READ-  
MODIFY-WRITEoccurs wh en WEfalls after CAS# (CASL#  
or CASH#) is taken LOW. Durin g EARLY WRITE cycles,  
th e data outputs (Q) will rem ain High -Z, regardless of  
th e state of OE#. Durin g LATEWRITEor READ-MODIFY-  
WRITE cycles, OE# m ust be taken HIGH to disable th e  
data outputs prior to applyin g in put data. If a LATE  
WRITE or READ-MODIFY-WRITE is attem pted wh ile  
keepin g OE# LOW, n o write will occur, an d th e data  
outputs will drive read data from th e accessed location .  
Addition ally, both bytes m ust always be of th e sam e  
m ode of operation if both bytes are active. A CAS#  
prech arge m ust be satisfied prior to ch an gin g m odes of  
operation between th e upper an d lower bytes. For  
exam ple, an EARLY WRITE on on e byte an d a LATE  
EDO PAGE MODE  
DRAM READ cycles h ave tradition ally turn ed th e  
output buffers off (High -Z) with th e risin g edge of  
CAS#. If CAS# wen t HIGH an d OE# was LOW (active),  
th e output buffers would be disabled. Th e 64Mb EDO  
DRAM offers an accelerated page m ode cycle by elim i-  
n atin g output disable from CAS# HIGH. Th is option is  
called EDO, an d it allows CAS# prech arge tim e (tCP) to  
occur with out th e output data goin g in valid (see READ  
an d EDO-PAGE-MODE READ waveform s).  
EDO operates like an y DRAM READ or FAST-PAGE-  
MODE READ, except data is h eld valid after CAS# goes  
HIGH, as lon g as RAS# an d OE# are h eld LOW an d WE#  
is h eld HIGH. OE# can be brough t LOW or HIGH wh ile  
CAS# an d RAS# are LOW, an d th e DQs will tran sition  
between valid data an d High -Z. Usin g OE#, th ere are  
WORD READ  
LOWER BYTE READ  
RAS#  
CASL#  
CASH#  
WE#  
STORED  
OUTPUT  
OUTPUT  
STORED STORED  
OUTPUT  
OUTPUT  
STORED  
DATA  
DATA  
DATA  
DATA  
DATA  
DATA  
DATA  
DATA  
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
LOWER BYTE  
(DQ0-DQ7)  
OF WORD  
0
1
0
1
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
1
0
1
0
0
0
0
UPPER BYTE  
(DQ8-DQ15)  
OF WORD  
ADDRESS 0  
ADDRESS 1  
Z = High-Z  
Fig u re 2  
WORD a n d BYTE READ Exa m p le  
4
4 MEG x 16  
EDO DRAM  
V
V
IH  
IL  
RAS#  
CAS#  
V
V
IH  
IL  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN (A)  
COLUMN (B)  
COLUMN (C)  
COLUMN (D)  
V
V
IOH  
IOL  
DQ  
OPEN  
VALID DATA (A)  
VALID DATA (A)  
VALID DATA (C)  
VALID DATA (D)  
VALID DATA (B)  
t
t
OD  
t
OD  
OD  
t
OES  
t
OEHC  
V
V
IH  
IL  
OE#  
t
OE  
t
OEP  
The DQs go back to  
Low-Z if OES is met.  
The DQs remain High-Z  
until the next CAS# cycle  
if OEHC is met.  
The DQs remain High-Z  
until the next CAS# cycle  
if OEP is met.  
t
t
t
Fig u re 3  
OE# Co n t ro l o f DQs  
V
IH  
RAS#  
CAS#  
V
IL  
V
V
IH  
IL  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN (A)  
COLUMN (B)  
COLUMN (C)  
COLUMN (D)  
V
V
IOH  
IOL  
DQ  
OPEN  
VALID DATA (A)  
VALID DATA (B)  
INPUT DATA (C)  
t
t
WHZ  
WHZ  
t
V
IH  
WE#  
OE#  
WPZ  
V
IL  
V
V
IH  
IL  
t
The DQs go to High-Z if WE# falls and, if WPZ is met,  
will remain High-Z until CAS# goes LOW with  
WE# HIGH (i.e., until a READ cycle is initiated).  
WE# may be used to disable the DQs to prepare  
for input data in an EARLY WRITE cycle. The DQs  
will remain High-Z until CAS# goes LOW with  
WE# HIGH (i.e., until a READ cycle is initiated).  
DON?T CARE  
UNDEFINED  
Fig u re 4  
WE# Co n t ro l o f DQs  
5
4 MEG x 16  
EDO DRAM  
EDO PAGE MODE (co n t in u e d )  
two m eth ods to disable th e outputs an d keep th em  
disabled durin g th e CAS# HIGH tim e. Th e first m eth od  
is to h ave OE# HIGH wh en CAS# tran sition s HIGH an d  
keep OE# HIGH for tOEHC th ereafter. Th is will disable  
th e DQs, an d th ey will rem ain disabled (regardless of  
th e state of OE# after th at poin t) un til CAS# falls again .  
Th e secon d m eth od is to h ave OE# LOW wh en CAS#  
tran sition s HIGH an d th en brin g OE# HIGH for a  
rows for 8 or 4,096 rows for 8). Th e recom m en ded  
procedure is to execute 4,096 CBR REFRESH cycles,  
eith er un iform ly spaced or grouped in bursts, every  
64m s. Th e MEM4X16E43VTW refresh es on e row for every  
CBR cycle. For eith er device, executin g 4,096 CBR  
cycles will refresh th e en tire device. Th e CBR REFRESH  
will in voke th e in tern al refresh coun ter for autom atic  
RAS# addressin g. Altern atively, RAS#-ONLY REFRESH  
capability is in h eren tly provided. However, with th is  
m eth od, on ly on e row is refresh ed on each cycle. JEDEC  
stron gly recom m en ds th e use of CBR REFRESH for th is  
device.  
t
m in im um of OEP an ytim e durin g th e CAS# HIGH  
period. Th is will disable th e DQs, an d th ey will rem ain  
disabled (regardless of th e state of OE# after th at poin t)  
un til CAS# falls again (see Figure 3). Durin g oth er  
t
cycles, th e outputs are disabled at OFF tim e after RAS#  
t
an d CAS# are HIGH or at WHZ after WE# tran sition s  
Th e self refresh m ode is also available.  
LOW. Th e tOFF tim e is referen ced from th e risin g edge  
of RAS# or CAS#, wh ich ever occurs last. WE# can also  
perform th e fun ction of disablin g th e output drivers  
un der certain con dition s, as sh own in Figure 4.  
EDO-PAGE-MODE operation s are always in itiated  
with a row address strobed in by th e RAS# sign al,  
followed by a colum n address strobed in by CAS#, just  
like for sin gle location accesses. However, subsequen t  
colum n location s with in th e row m ay th en be accessed  
at th e page m ode cycle tim e. Th is is accom plish ed by  
cyclin g CAS# wh ile h oldin g RAS# LOW an d en terin g  
n ew colum n addresses with each CAS# cycle. Return in g  
RAS# H IG H t erm in at es t h e EDO -PAG E-M O DE  
operation .  
Th e self refresh feature is in itiated by  
perform in g a CBR Refresh cycle an d h oldin g RAS# low  
for th e specified tRASS. Th e self refresh m ode allows  
th e user th e ch oice of a fully static, low-power data  
reten tion m ode or a dyn am ic refresh m ode at th e exten ded  
refresh period of 128m s, or 31.25µs per cycle, wh en  
usin g a distributed CBR refresh . Th is refresh rate can be  
applied durin g n orm al operation , as well as durin g a  
stan dby or battery backup m ode.  
Th e self refresh m ode is term in ated by drivin g RAS#  
HIGH for a m in im um tim e of t RPS. Th is delay allows for  
th e com pletion of an y in tern al refresh cycles th at m ay  
be in process at th e tim e of th e RAS# LOW-to-HIGH  
tran sition . If th e DRAM con troller uses a distributed  
CBR refresh sequen ce, a burst refresh is n ot required  
upon exitin g self refresh , h owever, if th e con troller is  
usin g RAS# on ly or burst CBR refresh th en a burst  
refresh usin g t RC (MIN) is required.  
DRAM REFRESH  
Th e supply voltage m ust be m ain tain ed at th e speci-  
fied levels, an d th e refresh requirem en ts m ust be m et in  
order to retain stored data in th e DRAM. Th e refresh  
requirem en ts are m et by refresh in g all rows in th e  
4 Meg x 16 DRAM array at least on ce every 64m s (8,192  
6
4 MEG x 16  
EDO DRAM  
*Stresses greater th an th ose listed un der “Absolute  
Maxim um Ratin gs” m ay cause perm an en t dam age to  
th e device. Th is is a stress ratin g on ly, an d fun ction al  
operation of th e device at th ese or an y oth er con dition s  
above th ose in dicated in th e operation al section s of  
th is specification is n ot im plied. Exposure to absolute  
m axim um ratin g con dition s for exten ded periods m ay  
affect reliability.  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on VCC Relative to VSS ................ -1V to +4.6V  
Voltage on NC, In puts or I/O Pin s  
Relative to VSS ....................................... -1V to +4.6V  
Operatin g Tem perature, TA (am bien t)  
Com m ercial ......................................... 0°C to +70°C  
Exten ded (IT) ................................. -40°C to +85°C**  
Storage Tem perature (plastic) ............ -55°C to +150°C  
Power Dissipation ................................................... 1W  
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS  
(Note: 1) (VCC = +3.3V ±0.3V)  
PARAMETER/CONDITION  
SYMBOL MIN  
MAX UNITS NOTES  
SUPPLY VOLTAGE  
VCC  
VIH  
VIL  
II  
3
3.6  
VCC + 0.3  
0.8  
V
INPUT HIGH VOLTAGE:  
Valid Logic 1; All inputs, I/Os and any NC  
2
V
35  
35  
36  
INPUT LOW VOLTAGE:  
Valid Logic 0; All inputs, I/Os and any NC  
-0.3  
-2  
V
INPUT LEAKAGE CURRENT:  
Any input at VIN (0V VIN VCC + 0.3V);  
<
_
<
_
2
µA  
All other pins not under test = 0V  
OUTPUT HIGH VOLTAGE:  
IOUT = -2mA  
VOH  
VOL  
IOZ  
2.4  
–
–
0.4  
5
V
V
OUTPUT LOW VOLTAGE:  
IOUT = 2mA  
OUTPUT LEAKAGE CURRENT:  
_
_
<
<
Any output at VOUT (0V VOUT VCC + 0.3V);  
DQ is disabled and in High-Z state  
-5  
µA  
7
4 MEG x 16  
EDO DRAM  
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS  
(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)  
MAX  
8K  
PARAMETER/CONDITION  
SYMBOL SPEED  
4K  
UNITS NOTES  
STANDBY CURRENT: TTL  
(RAS# = CAS# = VIH)  
ICC1  
ALL  
1
1
mA  
STANDBY CURRENT: CMOS  
(RAS# = CAS# ³ VCC - 0.2V; DQs may be left open;  
Other inputs: VIN ³ VCC - 0.2V or VIN £ 0.2V)  
ICC2  
ALL  
500  
500  
µA  
OPERATING CURRENT: Random READ/WRITE  
Average power supply current  
ICC3  
-5  
-6  
150  
165  
115  
130  
mA  
mA  
mA  
mA  
µA  
26  
26  
22  
t
(RAS#, CAS#, address cycling: tRC = RC [MIN])  
OPERATING CURRENT: EDO PAGE MODE  
Average power supply current  
ICC4  
ICC5  
ICC6  
CC7  
-5  
-6  
120  
125  
120  
125  
t
(RAS# = VIL, CAS#, address cycling: tPC = PC [MIN])  
REFRESH CURRENT: RAS#-ONLY  
Average power supply current  
-5  
-6  
150  
165  
115  
130  
t
(RAS# cycling, CAS# = VIH: tRC = RC [MIN])  
REFRESH CURRENT: CBR  
-5  
-6  
150  
165  
150  
165  
4, 7,  
23  
Average power supply current  
t
(RAS#, CAS#, address cycling: tRC = RC [MIN])  
REFRESH CURRENT: Extended  
ALL  
400  
400  
4, 7,  
Average power supply current: CAS# = 0.2V or CBR cycling;  
23, 37  
t
RAS# = RAS (MIN); WE# = VCC - 0.2V; A0-A10, OE# and  
t
DIN = VCC - 0.2V or 0.2V (DIN may be left open); RC = 125µs  
REFRESH CURRENT: Self  
CC8  
ALL  
350  
350  
µA  
4, 7,  
37  
Average power supply current: CBR with RAS# ³ tRASS (MIN)  
and CAS# held LOW; WE# = VCC - 0.2V; A0-A10, OE# and  
DIN = VCC - 0.2V or 0.2V (DIN may be left open)  
8
4 MEG x 16  
EDO DRAM  
CAPACITANCE  
(Note: 2)  
PARAMETER  
SYMBOL MAX  
UNITS  
pF  
Input Capacitance: Address pins  
Input Capacitance: RAS#, CAS#, WE#, OE#  
Input/Output Capacitance: DQ  
CI1  
CI2  
CIO  
5
7
7
pF  
pF  
AC ELECTRICAL CHARACTERISTICS  
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)  
AC CHARACTERISTICS  
-5  
-6  
PARAMETER  
SYMBOL  
tAA  
tACH  
tAR  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
NOTES  
Access time from column address  
Column-address setup to CAS# precharge  
Column-address hold time (referenced to RAS#)  
Column-address setup time  
Row-address setup time  
25  
30  
12  
38  
0
15  
45  
0
tASC  
tASR  
tAWD  
tCAC  
tCAH  
tCAS  
tCHD  
tCHR  
tCLCH  
tCLZ  
28  
28  
0
0
Column address to WE# delay time  
Access time from CAS#  
42  
49  
18  
13  
15  
29  
Column-address hold time  
CAS# pulse width  
8
8
10  
10  
15  
10  
5
28  
10,000  
10,000  
30, 32  
CAS# LOW to “Don?t Care” during Self Refresh  
CAS# hold time (CBR Refresh)  
Last CAS# going LOW to first CAS# to return HIGH  
CAS# to output in Low-Z  
15  
8
4, 31  
31  
5
0
0
29  
Data output hold after CAS# LOW  
CAS# precharge time  
tCOH  
tCP  
3
3
8
10  
13, 33  
29  
Access time from CAS# precharge  
CAS# to RAS# precharge time  
CAS# hold time  
tCPA  
tCRP  
tCSH  
tCSR  
tCWD  
tCWL  
tDH  
tDS  
tOD  
tOE  
tOEH  
28  
35  
5
38  
5
5
45  
5
31  
31  
CAS# setup time (CBR Refresh)  
CAS# to WE# delay time  
4, 28  
18, 28  
31  
28  
8
35  
10  
10  
0
WRITE command to CAS# lead time  
Data-in hold time  
8
19, 29  
19, 29  
24, 25  
20  
Data-in setup time  
0
Output disable  
0
12  
12  
0
15  
15  
Output enable time  
OE# hold time from WE# during  
READ-MODIFY-WRITE cycle  
8
10  
25  
OE# HIGH hold time from CAS# HIGH  
OE# HIGH pulse width  
tOEHC  
tOEP  
tOES  
tOFF  
5
5
4
0
0
10  
5
ns  
ns  
ns  
ns  
ns  
OE# LOW to CAS# HIGH setup time  
Output buffer turn-off delay  
5
12  
0
15  
17, 24, 29  
OE# setup prior to RAS# during HIDDEN REFRESH cycle  
tORD  
0
9
4 MEG x 16  
EDO DRAM  
AC ELECTRICAL CHARACTERISTICS  
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)  
AC CHARACTERISTICS  
-5  
-6  
PARAMETER  
SYMBOL  
tPC  
MIN  
20  
MAX  
MIN  
25  
MAX  
UNITS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
ns  
ms  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
NOTES  
34  
EDO-PAGE-MODE READ or WRITE cycle time  
EDO-PAGE-MODE READ-WRITE cycle time  
Access time from RAS#  
tPRWC  
tRAC  
tRAD  
tRAH  
tRAS  
tRASP  
tRASS  
tRC  
tRCD  
tRCH  
tRCS  
tREF  
tREF  
47  
56  
34  
50  
60  
RAS# to column-address delay time  
Row address hold time  
9
7
12  
10  
60  
60  
100  
104  
14  
0
15  
RAS# pulse width  
50  
50  
100  
84  
11  
0
10,000  
10,000  
RAS# pulse width (EDO PAGE MODE)  
RAS# pulse width during Self Refresh  
Random READ or WRITE cycle time  
RAS# to CAS# delay time  
125,000  
125,000  
14, 28  
16, 30  
28  
READ command hold time (referenced to CAS#)  
READ command setup time  
Refresh period  
0
0
64  
64  
22, 23  
23  
Refresh period (Self Refresh)  
RAS# precharge time  
128  
128  
tRP  
tRPC  
tRPS  
30  
5
40  
5
RAS# to CAS# precharge time  
RAS# precharge time exiting Self Refresh  
READ command hold time (referenced to RAS#)  
RAS# hold time  
90  
0
105  
0
tRRH  
tRSH  
tRWC  
tRWD  
tRWL  
tT  
tWCH  
tWCR  
tWCS  
tWHZ  
tWP  
16  
35  
13  
116  
67  
13  
2
15  
140  
79  
15  
2
READ-WRITE cycle time  
RAS# to WE# delay time  
18  
WRITE command to RAS# lead time  
Transition time (rise or fall)  
WRITE command hold time  
50  
12  
50  
15  
8
10  
45  
0
35  
WRITE command hold time (referenced to RAS#)  
WE# command setup time  
38  
0
18, 28  
WE# to outputs in High-Z  
WRITE command pulse width  
WE# pulse widths to disable outputs  
WE# hold time (CBR Refresh)  
WE# setup time (CBR Refresh)  
5
10  
8
5
tWPZ  
tWRH  
tWRP  
10  
10  
10  
8
10  
4 MEG x 16  
EDO DRAM  
EDO DRAM  
NOTES  
t
t
1. All voltages referen ced to VSS.  
16. Eith er RCH or RRH m ust be satisfied for a READ  
cycle.  
2. Th is param eter is sam pled. VCC = +3.3V; f = 1  
MHz; TA = 25°C.  
t
17. OFF (MAX) defin es th e tim e at wh ich th e output  
3. ICC is depen den t on output loadin g an d cycle  
rates. Specified values are obtain ed with m in i-  
m um cycle tim e an d th e outputs open .  
4. En ables on -ch ip refresh an d address coun ters.  
5. Th e m in im um specification s are used on ly to  
in dicate cycle tim e at wh ich proper operation  
over th e full tem perature ran ge is en sured.  
6. An in itial pause of 100µs is required after power-  
up, followed by eigh t RAS# refresh cycles (RAS#-  
ONLY or CBR with WE# HIGH), before proper  
device operation is en sured. Th e eigh t RAS# cycle  
ach ieves th e open circuit con dition an d is n ot  
referen ced to VOH or VOL.  
18. WCS, tRWD, tAWD, an d CWD are n ot restrictive  
operatin g param eters. tWCS applies to EARLY  
WRITE cycles. If tWCS > tWCS (MIN), th e cycle is  
an EARLY WRITE cycle an d th e data output will  
rem ain an open circuit th rough out th e en tire  
t
t
t
cycle. tRWD, tAWD, an d CWD defin e READ-  
MODIFY-WRITE cycles. Meetin g th ese lim its  
allows for readin g an d disablin g output data an d  
th en applyin g in put data. OE# h eld HIGH an d  
WE# taken LOW after CAS# goes LOW results in a  
LATE WRITE (OE#-con trolled) cycle. tWCS, tRWD,  
t
wake-ups sh ould be repeated an y tim e th e REF  
refresh requirem en t is exceeded.  
t
t
7. AC ch aracteristics assum e T = 2.5n s.  
tCWD, an d AWD are n ot applicable in a LATE  
8. VIH (MIN) an d VIL (MAX) are referen ce levels for  
m easurin g tim in g of in put sign als. Tran sition  
tim es are m easured between VIH an d VIL (or  
between VIL an d VIH).  
9. In addition to m eetin g th e tran sition rate  
specification , all in put sign als m ust tran sit  
between VIH an d VIL (or between VIL an d VIH) in a  
m on oton ic m an n er.  
WRITE cycle.  
19. Th ese param eters are referen ced to CAS# leadin g  
edge in EARLY WRITE cycles an d WE# leadin g  
edge in LATE WRITE or READ-MODIFY-WRITE  
cycles.  
20. If OE# is tied perm an en tly LOW, LATE WRITE, or  
READ-MODIFY-WRITE operation s are n ot  
possible.  
10. If CAS# an d RAS# = VIH, data output is High -Z.  
11. If CAS# = VIL, data output m ay con tain data from  
th e last valid READ cycle.  
21. A HIDDEN REFRESH m ay also be perform ed after  
a WRITE cycle. In th is case, WE# is LOW an d  
OE# is HIGH.  
12. Measured with a load equivalen t to two TTL  
gates an d 100pF; an d VOL = 0.8V an d VOH = 2V.  
13. If CAS# is LOW at th e fallin g edge of RAS#,  
output data will be m ain tain ed from th e previous  
cycle. To in itiate a n ew cycle an d clear th e data-  
22. RAS#-ONLY REFRESH requires th at all 8,192 rows  
of th e ARC8V4M16E or all 4,096 rows of th e  
4X16E43V be refresh ed at least on ce every  
64m s.  
23. CBR REFRESH for eith er device requires th at at  
least 4,096 cycles be com pleted every 64m s.  
t
out buffer, CAS# m ust be pulsed HIGH for CP.  
t
t
14. Th e RCD (MAX) lim it is n o lon ger specified.  
24. Th e DQs go High -Z durin g READ cycles on ce OD  
tRCD (MAX) was specified as a referen ce poin t  
or OFF occur. If CAS# stays LOW wh ile OE# is  
t
t
t
on ly. If RCD was greater th an th e specified RCD  
(MAX) lim it, th en access tim e was con trolled  
brough t HIGH, th e DQs will go High -Z. If OE# is  
brough t back LOW (CAS# still LOW), th e DQs  
will provide th e previously read data.  
exclusively by CAC (tRAC [MIN] n o lon ger  
applied). With or with out th e RCD lim it, AA  
an d CAC m ust always be m et.  
t
t
t
25. LATE WRITE an d READ-MODIFY-WRITE cycles  
t
t
t
m ust h ave both OD an d OEH m et (OE# HIGH  
durin g WRITE cycle) in order to en sure th at th e  
output buffers will be open durin g th e WRITE  
cycle. If OE# is taken back LOW wh ile CAS#  
rem ain s LOW, th e DQs will rem ain open .  
t
15. Th e RAD (MAX) lim it is n o lon ger specified.  
tRAD (MAX) was specified as a referen ce poin t  
t
t
on ly. If RAD was greater th an th e specified RAD  
(MAX) lim it, th en access tim e was con trolled  
exclusively by AA (tRAC an d CAC n o lon ger  
26. Colum n address ch an ged on ce each cycle.  
27. Th e first CASx# edge to tran sition LOW.  
t
t
t
applied). With or with out th e RAD (MAX) lim it,  
tAA, RAC, an d CAC m ust always be m et.  
t
t
11  
4 MEG x 16  
EDO DRAM  
NOTES (co n t in u e d )  
28. Output param eter (DQx) is referen ced to  
correspon din g CAS# in put; DQ0-DQ7 by CASL#  
an d DQ8-DQ15 by CASH#.  
35. VIH oversh oot: VIH (MAX) = VCC + 2V for a pulse  
width £ 3n s, an d th e pulse width can n ot be  
greater th an on e th ird of th e cycle rate. VIL  
un dersh oot: VIL (MIN) = -2V for a pulse width £  
3n s, an d th e pulse width can n ot be greater th an  
on e th ird of th e cycle rate.  
36. NC pin s are assum ed to be left floatin g an d are  
n ot tested for leakage.  
37. Self refresh an d exten ded refresh for eith er device  
requires th at at least 4,096 cycles be com pleted  
every 128m s.  
29. Each CASx# m ust m eet m in im um pulse width .  
30. Th e last CASx# edge to tran sition HIGH.  
31. Last fallin g CASx# edge to first risin g CASx#  
edge.  
32. Last risin g CASx# edge to first fallin g CASx#  
edge.  
33. Last risin g CASx# edge to n ext cycle?s last risin g  
CASx# edge.  
34. Last CASx# to go LOW.  
12  
4 MEG x 16  
EDO DRAM  
READ CYCLE  
t
RC  
t
t
RP  
RAS  
V
V
IH  
IL  
RAS#  
CAS#  
t
CSH  
t
t
RRH  
RSH  
t
t
t
RCD  
CAS  
CRP  
V
V
IH  
IL  
t
AR  
t
t
RAD  
RAH  
t
t
t
ASR  
ASC  
CAH  
t
ACH  
V
V
IH  
IL  
ROW  
ROW  
COLUMN  
ADDR  
WE#  
t
t
RCH  
RCS  
V
V
IH  
IL  
t
t
t
t
AA  
RAC  
CAC  
CLZ  
NOTE 1  
t
OFF  
V
V
OH  
OL  
DQ  
OPEN  
OPEN  
VALID DATA  
t
t
OD  
OE  
V
V
IH  
IL  
OE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
tACH  
tAR  
tASC  
tASR  
tCAC  
tCAH  
tCAS  
tCLCH  
tCLZ  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tOE  
MIN  
MAX  
MIN  
MAX  
15  
UNITS  
ns  
25  
30  
12  
12  
50  
12  
38  
0
15  
45  
0
ns  
tOFF  
tRAC  
tRAD  
tRAH  
tRAS  
tRC  
tRCD  
tRCH  
tRCS  
tRP  
0
0
15  
ns  
ns  
60  
ns  
ns  
9
7
12  
10  
60  
104  
14  
0
ns  
0
0
ns  
ns  
13  
15  
ns  
50  
84  
11  
0
10,000  
10,000  
ns  
8
8
10  
10  
5
ns  
ns  
10,000  
10,000  
ns  
ns  
5
ns  
ns  
0
0
ns  
0
0
ns  
tCRP  
tCSH  
tOD  
5
5
ns  
30  
0
40  
0
ns  
38  
0
45  
0
ns  
tRRH  
tRSH  
ns  
12  
15  
ns  
13  
15  
ns  
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.  
13  
4 MEG x 16  
EDO DRAM  
EDO DRAM  
EARLY WRITE CYCLE  
t
RC  
t
t
RP  
RAS  
V
V
IH  
IL  
RAS#  
CAS#  
t
CSH  
t
RSH  
t
t
t
CRP  
RCD  
CAS  
V
V
IH  
IL  
t
AR  
t
t
RAD  
RAH  
t
t
ASC  
t
ASR  
CAH  
t
ACH  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN  
ROW  
t
CWL  
t
t
t
t
RWL  
WCR  
WCH  
WP  
t
WCS  
WE#  
V
V
IH  
IL  
t
t
DS  
DH  
V
V
IOH  
IOL  
DQ  
VALID DATA  
V
V
IH  
IL  
OE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tACH  
tAR  
tASC  
tASR  
tCAH  
tCAS  
tCLCH  
tCRP  
MIN  
12  
38  
0
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tRAD  
tRAH  
tRAS  
tRC  
tRCD  
tRP  
MIN  
9
MAX  
MIN  
12  
10  
60  
104  
14  
40  
15  
15  
10  
45  
0
MAX  
UNITS  
ns  
15  
45  
0
ns  
7
ns  
ns  
50  
84  
11  
30  
13  
13  
8
10,000  
10,000  
ns  
0
0
ns  
ns  
8
10  
10  
5
ns  
ns  
8
10,000  
10,000  
ns  
ns  
5
ns  
tRSH  
ns  
5
5
ns  
tRWL  
tWCH  
tWCR  
tWCS  
tWP  
ns  
tCSH  
tCWL  
tDH  
38  
8
45  
10  
10  
0
ns  
ns  
ns  
38  
0
ns  
8
ns  
ns  
tDS  
0
ns  
5
5
ns  
14  
4 MEG x 16  
EDO DRAM  
READ-WRITE CYCLE  
(LATE WRITE and READ-MODIFY-WRITE cycles)  
t
RWC  
t
t
RAS  
RP  
V
V
IH  
IL  
RAS#  
CAS#  
t
CSH  
t
RSH  
t
t
t
t
CAS  
CRP  
ASR  
RCD  
V
V
IH  
IL  
t
AR  
t
RAD  
t
t
t
CAH  
t
ASC  
RCS  
RAH  
t
ACH  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN  
ROW  
t
t
t
t
RWD  
CWL  
RWL  
WP  
t
CWD  
t
AWD  
V
V
IH  
IL  
WE#  
t
AA  
t
RAC  
t
CAC  
t
t
DS  
DH  
t
CLZ  
V
V
IOH  
IOL  
VALID D  
VALID D  
DQ  
OPEN  
OPEN  
OUT  
IN  
t
t
t
OE  
OD  
OEH  
V
V
IH  
IL  
OE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
tACH  
tAR  
tASC  
tASR  
tAWD  
tCAC  
tCAH  
tCAS  
tCLCH  
tCLZ  
tCRP  
tCSH  
tCWD  
tCWL  
tDH  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tDS  
tOD  
tOE  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
25  
30  
0
0
0
0
12  
38  
0
15  
45  
0
ns  
12  
12  
15  
15  
ns  
ns  
ns  
ns  
tOEH  
tRAC  
tRAD  
tRAH  
tRAS  
tRCD  
tRCS  
tRP  
tRSH  
tRWC  
tRWD  
tRWL  
tWP  
8
10  
ns  
0
0
ns  
50  
60  
ns  
42  
49  
ns  
9
7
12  
10  
60  
14  
0
ns  
13  
15  
ns  
ns  
8
8
10  
10  
5
ns  
50  
11  
0
10,000  
10,000  
ns  
10,000  
10,000  
ns  
ns  
5
ns  
ns  
0
0
ns  
30  
13  
116  
67  
13  
5
40  
15  
140  
79  
15  
5
ns  
5
5
ns  
ns  
38  
28  
8
45  
35  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
8
ns  
ns  
15  
4 MEG x 16  
EDO DRAM  
EDO-PAGE-MODE READ CYCLE  
t
t
RASP  
RP  
V
V
IH  
IL  
RAS#  
CAS#  
t
t
t
RSH  
CSH  
PC  
t
t
t
t
t
t
t
t
CRP  
RCD  
CAS  
CP  
CAS  
CP  
CAS  
CP  
V
V
IH  
IL  
t
AR  
t
t
t
t
t
ACH  
ACH  
RAD  
RAH  
ACH  
t
t
t
t
t
t
t
CAH  
ASR  
ASC  
CAH  
ASC  
CAH  
ASC  
V
V
IH  
IL  
ADDR  
WE#  
ROW  
COLUMN  
COLUMN  
COLUMN  
ROW  
t
RCS  
t
RCH  
V
V
IH  
IL  
t
t
t
t
RRH  
AA  
t
t
t
t
AA  
AA  
CPA  
CAC  
t
RAC  
CPA  
CAC  
t
t
CAC  
CLZ  
t
OEHC  
t
OFF  
t
COH  
t
CLZ  
V
V
OH  
OL  
VALID  
DATA  
VALID  
DATA  
VALID  
OPEN  
DQ  
OPEN  
DATA  
t
t
t
OE  
OE  
t
OD  
OD  
t
OES  
t
V
V
OES  
IH  
IL  
OE#  
t
OEP  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tOE  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
25  
30  
12  
15  
tACH  
tAR  
12  
38  
0
15  
45  
0
ns  
tOEHC  
tOEP  
tOES  
tOFF  
tPC  
tRAC  
tRAD  
tRAH  
tRASP  
tRCD  
tRCH  
tRCS  
5
5
10  
5
ns  
ns  
ns  
tASC  
tASR  
tCAC  
tCAH  
tCAS  
tCLCH  
tCLZ  
tCOH  
tCP  
tCPA  
tCRP  
tCSH  
tOD  
ns  
4
5
ns  
0
0
ns  
0
12  
50  
0
15  
60  
ns  
13  
15  
ns  
20  
25  
ns  
8
8
5
0
3
8
10  
10  
5
ns  
ns  
10,000  
10,000  
ns  
9
7
12  
10  
60  
14  
0
ns  
ns  
ns  
0
ns  
50  
11  
0
125,000  
125,000  
ns  
3
ns  
ns  
10  
ns  
ns  
28  
12  
35  
15  
ns  
0
0
ns  
5
38  
0
5
45  
0
ns  
tRP  
tRRH  
tRSH  
30  
0
40  
0
ns  
ns  
ns  
ns  
13  
15  
ns  
16  
4 MEG x 16  
EDO DRAM  
EDO-PAGE-MODE EARLY WRITE CYCLE  
t
t
RP  
RASP  
V
V
IH  
IL  
RAS#  
CAS#  
t
t
t
t
CSH  
PC  
RSH  
CAS  
t
t
t
t
t
t
t
CRP  
RCD  
CAS  
CP  
CAS  
CP  
CP  
V
V
IH  
IL  
t
AR  
t
t
t
t
t
t
RAD  
ACH  
ACH  
CAH  
ACH  
CAH  
t
t
t
t
t
t
ASC  
ASR  
RAH  
ASC  
CAH  
ASC  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN  
COLUMN  
COLUMN  
ROW  
t
t
t
t
t
t
t
CWL  
CWL  
WCH  
WP  
CWL  
WCH  
WP  
t
t
t
t
t
WCS  
WCS  
WCH  
WP  
WCS  
V
V
IH  
IL  
WE#  
DQ  
t
t
WCR  
DH  
RWL  
t
t
t
t
t
t
DS  
DS  
DH  
DS  
DH  
V
IOH  
IOL  
VALID DATA  
VALID DATA  
VALID DATA  
V
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tACH  
tAR  
tASC  
tASR  
tCAH  
tCAS  
tCLCH  
tCP  
tCRP  
tCSH  
tCWL  
tDH  
MIN  
12  
38  
0
MAX  
MIN  
15  
45  
0
MAX  
UNITS  
ns  
SYMBOL  
tPC  
MIN  
20  
9
MAX  
MIN  
25  
12  
10  
60  
14  
40  
15  
15  
10  
45  
0
MAX  
UNITS  
ns  
ns  
tRAD  
tRAH  
tRASP  
tRCD  
tRP  
ns  
ns  
7
ns  
0
0
ns  
50  
11  
30  
13  
13  
8
125,000  
125,000  
ns  
8
10  
10  
5
ns  
ns  
8
10,000  
10,000  
ns  
ns  
5
ns  
tRSH  
ns  
8
10  
5
ns  
tRWL  
tWCH  
tWCR  
tWCS  
tWP  
ns  
5
ns  
ns  
38  
8
45  
10  
10  
0
ns  
38  
0
ns  
ns  
ns  
8
ns  
5
5
ns  
tDS  
0
ns  
17  
4 MEG x 16  
EDO DRAM  
EDO-PAGE-MODE READ-WRITE CYCLE  
(LATE WRITE and READ-MODIFY-WRITE cycles)  
t
t
RASP  
RP  
V
V
IH  
IL  
RAS#  
t
t
t
t
RSH  
NOTE 1  
CSH  
PC  
PRWC  
t
t
t
t
t
t
t
t
CAS  
CRP  
RCD  
CP  
CP  
CP  
CAS  
CAS  
CASL#/CASH#  
V
V
IH  
IL  
t
AR  
t
t
RAD  
RAH  
t
t
t
t
t
t
t
CAH  
ASR  
ASC  
CAH  
ASC  
CAH  
ASC  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN  
COLUMN  
COLUMN  
ROW  
t
RWD  
t
RWL  
t
RCS  
t
t
t
CWL  
CWL  
CWL  
t
t
t
WP  
WP  
WP  
t
t
t
t
AWD  
AWD  
AWD  
CWD  
t
t
CWD  
CWD  
WE#  
V
V
IH  
IL  
t
t
t
t
t
AA  
AA  
AA  
t
RAC  
t
t
t
DH  
DH  
DH  
CPA  
CPA  
t
t
t
DS  
DS  
DS  
t
t
t
t
t
t
CAC  
CLZ  
CAC  
CLZ  
CAC  
CLZ  
V
V
IOH  
IOL  
VALID VALID  
VALID VALID  
VALID VALID  
DQ  
OPEN  
OPEN  
D
D
D
D
D
D
IN  
OUT  
IN  
OUT  
IN  
OUT  
t
t
t
OD  
OD  
OD  
t
OEH  
t
t
t
OE  
OE  
OE  
V
V
IH  
IL  
OE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
tAR  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tDS  
tOD  
tOE  
tOEH  
tPC  
tPRWC  
tRAC  
tRAD  
tRAH  
tRASP  
tRCD  
tRCS  
tRP  
tRSH  
tRWD  
tRWL  
tWP  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
25  
30  
0
0
0
0
38  
0
45  
0
ns  
12  
12  
15  
15  
ns  
tASC  
tASR  
tAWD  
tCAC  
tCAH  
tCAS  
tCLCH  
tCLZ  
ns  
ns  
0
0
ns  
8
10  
25  
56  
ns  
42  
49  
ns  
20  
47  
ns  
13  
15  
ns  
ns  
8
8
5
0
8
10  
10  
5
ns  
50  
60  
ns  
10,000  
10,000  
ns  
9
12  
10  
60  
14  
0
ns  
ns  
7
ns  
0
ns  
50  
11  
0
125,000  
125,000  
ns  
tCP  
10  
ns  
ns  
tCPA  
tCRP  
tCSH  
tCWD  
tCWL  
tDH  
28  
35  
ns  
ns  
5
38  
28  
8
5
ns  
30  
13  
67  
13  
5
40  
15  
79  
15  
5
ns  
45  
35  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
8
ns  
ns  
NOTE: 1. tPC is for LATE WRITE cycles only.  
18  
4 MEG x 16  
EDO DRAM  
EDO-PAGE-MODE READ EARLY WRITE CYCLE  
(Pseudo READ-MODIFY-WRITE)  
t
t
RP  
RASP  
V
V
IH  
IL  
RAS#  
CAS#  
t
CSH  
t
t
t
PC  
RSH  
PC  
t
t
t
t
t
t
t
t
CRP  
RCD  
CAS  
CP  
CAS  
CP  
CAS  
CP  
V
V
IH  
IL  
t
t
AR  
t
t
t
RAD  
ACH  
CAH  
t
ASR  
t
t
t
t
t
ASC  
RAH  
ASC  
CAH  
ASC  
CAH  
V
V
IH  
IL  
ADDR  
WE#  
ROW  
COLUMN (A)  
COLUMN (B)  
ROW  
COLUMN (N)  
t
t
RCH  
t
t
t
RCS  
WCS  
WCH  
V
V
IH  
IL  
t
AA  
t
t
AA  
t
CPA  
RAC  
t
t
DH  
t
CAC  
DS  
CAC  
t
t
WHZ  
COH  
V
V
IOH  
IOL  
VALID  
DATA (B)  
DQ  
VALID DATA  
IN  
OPEN  
VALID DATA (A)  
t
OE  
IH  
IL  
OE#  
V
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tOE  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
25  
30  
12  
15  
tACH  
tAR  
12  
38  
0
15  
45  
0
ns  
tPC  
20  
25  
ns  
ns  
tRAC  
tRAD  
tRAH  
tRASP  
tRCD  
tRCH  
tRCS  
tRP  
tRSH  
tWCH  
tWCS  
tWHZ  
50  
60  
ns  
tASC  
tASR  
tCAC  
tCAH  
tCAS  
tCOH  
tCP  
tCPA  
tCRP  
tCSH  
tDH  
ns  
9
7
12  
10  
60  
14  
0
ns  
0
0
ns  
ns  
13  
15  
ns  
50  
11  
0
125,000  
125,000  
ns  
8
8
3
8
10  
10  
3
ns  
ns  
10,000  
10,000  
ns  
ns  
ns  
0
0
ns  
10  
ns  
30  
13  
8
40  
15  
10  
0
ns  
28  
35  
ns  
ns  
5
38  
8
5
45  
10  
0
ns  
ns  
ns  
0
ns  
ns  
12  
15  
ns  
tDS  
0
ns  
19  
4 MEG x 16  
EDO DRAM  
READ CYCLE  
(with WE#-controlled disable)  
V
V
IH  
IL  
RAS#  
t
CSH  
t
t
t
t
CP  
RCD  
CAS  
CRP  
V
V
IH  
IL  
CASL#/CASH#  
t
AR  
t
t
RAD  
RAH  
t
t
t
t
ASC  
ASR  
ASC  
CAH  
V
V
IH  
IL  
ROW  
COLUMN  
COLUMN  
ADDR  
WE#  
t
RCS  
t
t
t
RCH  
WPZ  
RCS  
V
V
IH  
IL  
t
t
t
t
AA  
RAC  
CAC  
CLZ  
t
t
WHZ  
CLZ  
V
V
OH  
OL  
DQ  
OPEN  
OPEN  
VALID DATA  
t
t
OD  
OE  
V
V
IH  
IL  
OE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
tAR  
tASC  
tASR  
tCAC  
tCAH  
tCAS  
tCLZ  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tOD  
tOE  
tRAC  
tRAD  
tRAH  
tRCD  
tRCH  
tRCS  
MIN  
MAX  
12  
MIN  
MAX  
15  
UNITS  
25  
30  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
38  
0
45  
0
ns  
12  
15  
ns  
50  
60  
0
0
ns  
9
7
12  
10  
14  
0
13  
15  
ns  
8
8
10  
10  
0
ns  
11  
0
10,000  
10,000  
ns  
0
ns  
0
0
tCP  
tCRP  
tCSH  
8
10  
5
ns  
tWHZ  
tWPZ  
12  
15  
5
ns  
10  
10  
38  
45  
ns  
20  
4 MEG x 16  
EDO DRAM  
RAS#-ONLY REFRESH CYCLE  
(OE# and WE# = DON?T CARE)  
t
RC  
t
t
RP  
RAS  
V
V
IH  
IL  
RAS#  
t
t
RPC  
CRP  
t
V
V
IH  
IL  
CASL#/CASH#  
t
ASR  
RAH  
V
V
IH  
IL  
ADDR  
Q
ROW  
ROW  
V
OH  
OL  
OPEN  
V
CBR REFRESH CYCLE  
(Addresses and OE# = DON?T CARE)  
t
t
t
t
RAS  
RP  
RAS  
RP  
NOTE 1  
V
V
IH  
IL  
RAS#  
t
RPC  
t
t
t
t
t
t
CHR  
RPC  
CP  
CSR  
CHR  
CSR  
V
V
IH  
IL  
CASL#/CASH#  
DQ  
V
V
OH  
OL  
OPEN  
t
t
t
t
WRH  
WRP  
WRH  
WRP  
V
V
IH  
IL  
WE#  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tASR  
tCHR  
tCP  
tCRP  
tCSR  
MIN  
MAX  
MIN  
0
MAX  
UNITS  
SYMBOL  
tRAS  
tRC  
tRP  
tRPC  
tWRH  
tWRP  
MIN  
50  
84  
30  
5
MAX  
MIN  
60  
MAX  
UNITS  
ns  
0
8
8
5
5
7
ns  
ns  
ns  
ns  
ns  
ns  
10,000  
10,000  
10  
10  
5
104  
40  
ns  
ns  
5
ns  
5
8
10  
ns  
tRAH  
10  
8
10  
ns  
NOTE: 1. End of first CBR REFRESH cycle.  
21  
4 MEG x 16  
EDO DRAM  
1
HIDDEN REFRESH CYCLE  
(WE# = HIGH; OE# = LOW)  
t
RC  
t
t
t
RAS  
RAS  
RP  
V
V
IH  
IL  
RAS#  
t
t
t
t
CRP  
RCD  
RSH  
CHR  
V
V
IH  
IL  
CASL#/CASH#  
t
t
AR  
RAD  
t
t
t
t
CAH  
ASR  
RAH  
ASC  
V
V
IH  
IL  
ADDR  
ROW  
COLUMN  
t
AA  
t
t
t
RAC  
CAC  
CLZ  
t
OFF  
V
IOH  
IOL  
DQx  
OE#  
OPEN  
VALID DATA  
OPEN  
V
t
t
OE  
OD  
V
V
t
IH  
IL  
ORD  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tAA  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
SYMBOL  
tOE  
MIN  
MAX  
12  
MIN  
MAX  
15  
UNITS  
ns  
25  
30  
tAR  
38  
0
45  
0
ns  
tOFF  
tORD  
tRAC  
tRAD  
tRAH  
tRAS  
tRCD  
tRP  
0
0
12  
0
0
15  
ns  
tASC  
tASR  
tCAC  
tCAH  
tCHR  
tCLZ  
ns  
ns  
0
0
ns  
50  
60  
ns  
13  
12  
15  
15  
ns  
9
12  
10  
60  
14  
40  
15  
ns  
8
8
0
5
0
10  
10  
0
ns  
7
ns  
ns  
50  
11  
30  
13  
10,000  
10,000  
ns  
ns  
ns  
tCRP  
tOD  
5
ns  
ns  
0
ns  
tRSH  
ns  
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.  
22  
4 MEG x 16  
EDO DRAM  
SELF REFRESH CYCLE  
(Addresses and OE# = DON?T CARE)  
NOTE 1  
t
t
t
t
RP  
RASS  
RPS  
( (  
) )  
NOTE 2  
V
V
IH  
IL  
RAS#  
t
t
t
( (  
) )  
( (  
) )  
RPC  
CP  
RPC  
t
t
CP  
CSR  
CHD  
( (  
) )  
V
V
IH  
IL  
CASL#/  
CASH#  
( (  
) )  
V
V
( (  
) )  
OH  
OL  
OPEN  
DQ  
t
t
t
t
WRH  
WRP  
WRH  
WRP  
( (  
) )  
V
V
IH  
IL  
WE#  
( (  
) )  
DON?T CARE  
UNDEFINED  
TIMING PARAMETERS  
-5  
-6  
-5  
-6  
SYMBOL  
tCHD  
tCLCH  
tCP  
tCSR  
tRASS  
MIN  
15  
5
MAX  
MIN  
15  
5
MAX  
UNITS  
SYMBOL  
tRP  
tRPC  
tRPS  
tWRH  
tWRP  
MIN  
30  
5
MAX  
MIN  
MAX  
UNITS  
ns  
ns  
ns  
ns  
ns  
40  
5
ns  
ns  
ns  
ns  
ns  
8
10  
5
90  
8
105  
10  
10  
5
100  
100  
8
t
NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.  
t
2. Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.  
23  
4 MEG x 16  
EDO DRAM  
50-PIN PLASTIC TSOP (400 m il)  
21.04  
20.88  
.88  
TYP  
50  
11.86  
11.66  
10.21  
10.11  
SEE DETAIL A  
1
25  
.18  
.13  
.80  
TYP  
.45  
.30  
PIN #1 ID  
.25  
.20  
.25  
GAGE PLANE  
.10  
MAX  
.60  
.40  
DETAIL A  
.80  
TYP  
MAX  
MIN  
NOTE: 1. All dimensions in millimeters  
or typical where noted.  
2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.  
24  
厂商 型号 描述 页数 下载

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