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CYV270M0101EQ_0710

型号：

CYV270M0101EQ_0710

描述：

自适应视频电缆均衡器[ Adaptive Video Cable Equalizer ]

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

245 K

下载PDF手册
CYV270M0101EQ  
Adaptive Video Cable Equalizer  
Features  
Functional Description  
■ Adaptive cable equalization  
The CYV270M0101EQ is an adaptive video cable equalizer  
designed to equalize and restore signals received over 75Ω  
coaxial cable. The equalizer meets SMPTE 259M data rates and  
is optimized for performance at 270 Mbps. The  
CYV270M0101EQ is optimized to equalize up to 350m of  
Canare L-5CFB and Belden 1694A coaxial cable at 270 Mbps.  
The CYV270M0101EQ connects seamlessly to the HOTLink II  
family of transceivers and HOTLink receivers.  
■ SMPTE 259M compliant  
■ Supports DVB-ASI at 270 Mbps  
■ Multi standard operation from 143 Mbps to 360 Mbps  
■ Cable length indicator for SD-SDI data rates  
■ Maximum cable length adjustment for SD-SDI data rates  
■ Carrier detect and mute functionality for SD-SDI data rates  
■ Equalizer bypass mode  
The CYV270M0101EQ has DC restoration for compensation of  
the DC content of the SMPTE pathological patterns. A cable  
length indicator (CLI) provides an indication of the cable length  
equalized at SD-SDI data rates. The maximum cable length  
adjust (MCLADJ) sets the approximate maximum cable length to  
equalize. The CYV270M0101EQ differential serial outputs  
(SDO, SDO) mute when the approximate cable length set by  
MCLADJ is reached. CD/MUTE is a bidirectional pin that  
provides an indication of the signal present at the equalizer  
inputs. It also controls muting the outputs of the equalizer.  
■ Seamless connection with HOTLink II™ family and HOTLink®  
receiver  
■ Equalizes up to 350m of Canare L-5CFB and Belden 1694A  
coaxial cable at 270 Mbps  
■ Low power 160 mW at 3.3V  
■ Single 3.3V supply  
Power consumption is typically 160 mW at 3.3V.  
■ 16-pin SOIC  
■ 0.18 μm CMOS technology  
■ Pb-free and RoHS compliant  
■ Uses Cypress CLEANLink™ technology  
■ Pin compatible to existing equalizer devices  
Equalizer System Connection Diagram  
CYV270M0101EQ  
Adaptive  
Serial Links  
HOTLink II  
Serializer  
Cable  
Driver  
HOTLink II  
Deserializer  
Copper Cable  
Connections  
Cable  
Equalizer  
Cypress Semiconductor Corporation  
Document Number: 001-06830 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 25, 2007  
[+] Feedback  
CYV270M0101EQ  
Equalizer Block Diagram  
CYV270M0101EQ Adaptive Video Cable Equalizer Block Diagram  
CYV270M0101EQ Adaptive Video Cable Equalizer Block Diagram  
Cable Length Analog  
Carrier Detect and  
Adjustor and Mute  
Mute Control Block  
Threshold Block  
MUTE  
CD  
MCLADJ  
DC Restore  
BYPASS  
SDI, SDI  
Equalizer  
Differential Output  
SDO, SDO  
Pinouts  
Figure 1. Pin Diagram - 16 Pin SOIC (Top View)  
16  
15  
CD/MUTE  
VCC  
CLI  
2
VCC  
GND  
3
4
14  
13  
GND  
SDO  
SDI  
SDI  
CYV270M0101EQ  
5
6
12  
11  
SDO  
GND  
GND  
AGC+  
AGC-  
7
8
10  
9
MCLADJ  
BYPASS  
Document Number: 001-06830 Rev. *B  
Page 2 of 10  
[+] Feedback  
CYV270M0101EQ  
Table 1. Pin Descriptions - CYV270M0101EQ Single Channel Cable Equalizer  
Name  
IO Characteristics Signal Description  
Control Signals  
CLI  
Analog Output  
LVTTL IO  
Cable Length Indicator. CLI provides an analog voltage proportional to the equalized  
cable length.  
CD/MUTE  
Carrier Detect/Mute Indicator.  
Output:  
When the incoming data stream is present and the cable length does not exceed that set  
by MCLADJ, the CD/MUTE outputs a voltage less than 0.8V.  
When the incoming data stream is not present or the cable length exceeds that set by  
MCLADJ, the CD/MUTE outputs a voltage greater than 2.8V.  
Input:  
When the CD/MUTE pin is set LOW, the equalizer’s differential serial outputs are not muted.  
When the CD/MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted.  
MCLADJ  
BYPASS  
Analog Input  
LVTTL Input  
Maximum Cable Length Adjust. The maximum equalized cable length is set by the  
voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is  
reached, CD is driven high and the differential output is muted.  
If MCLADJ functionality is not needed, this pin should be left floating or tied to ground to  
allow maximum equalized cable length.  
Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s  
differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs  
(SDO, SDO) without equalizing.  
When BYPASS is set LOW, the incoming video data stream is equalized and presented at  
the equalizer‘s serial differential outputs (SDO, SDO).  
In equalizer bypass mode, CD/MUTE is not functional.  
AGC±  
Analog  
Automatic Gain Control. Place a capacitor of 1 μF between the AGC± pins.  
SDO, SDO  
Differential  
Output  
Differential Serial Outputs. The equalized serial video data stream is presented at the  
SDO/SDO differential serial CML output.  
SDI, SDI  
Differential  
Input  
Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial video  
data stream over 75Ω coaxial cable.  
Power  
VCC  
Power  
Gnd  
+3.3V Power.  
GND  
Connect to Ground.  
Document Number: 001-06830 Rev. *B  
Page 3 of 10  
[+] Feedback  
CYV270M0101EQ  
Equalizer Operation  
MCLADJ  
The CYV270M0101EQ is an adaptive video cable equalizer  
designed to equalize standard definition (SD) serial digital  
interface (SDI) video data streams. The CYV270M0101EQ  
equalizer is optimized to equalize up to 350m of Canare L-5CFB  
and Belden 1694A cable at 270 Mbps. The device contains one  
power supply and typically consumes 160 mW power at 3.3V.  
The adaptive equalizer meets the SMPTE 259M and DVB-ASI  
video standards. It meets all pathological requirements for  
SMPTE 259M as defined by RP178. The CYV270M0101EQ  
Video Cable Equalizer is auto adaptive from 143 Mbps to 360  
Mbps.  
Maximum Cable Length Adjust (MCLADJ) sets the approximate  
maximum amount of cable to be equalized.  
If the MCLADJ voltage is greater than the CLI output voltage, CD  
is driven high and the equalizer serial differential outputs (SDO,  
SDO) are muted. If the MCLADJ voltage is less than CLI voltage,  
then the equalizer’s differential serial outputs (SDO, SDO) are  
not muted and the incoming data stream is equalized. The graph  
in Figure 2 on page 7 illustrates the voltage required at MCLADJ  
input to equalize various Belden 1694A cable lengths for SD data  
rates. If MCLADJ functionality is not required, this pin should be  
left floating or tied to ground to allow maximum equalized cable  
length.  
The CYV270M0101EQ equalizer has variable gain and multiple  
equalization stages that reverse the effects of the cable. This  
equalization is achieved by separate regulation of the lower and  
higher frequency components in the signal to give a clean output  
eye diagram. The CYV270M0101EQ has DC restoration to  
compensate the DC content of the SMPTE pathological patterns.  
CD/MUTE  
Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that  
provides an indication of the signal present at the equalizer’s  
input, or it controls the muting of the equalizer’s output.  
SDI, SDI  
If CD/MUTE is used as an output and the incoming data stream  
is not present or the cable length exceeds that set by MCLADJ,  
the voltage at the CD/MUTE output is greater than 2.8V. If  
CD/MUTE is used as an output, the incoming data stream is  
present and the cable length does not exceed that set by  
MCLADJ, then the voltage at the CD/MUTE output is less than  
0.8V.  
The CYV270M0101EQ accepts single-ended or differential  
serial video data streams over 75Ω coaxial cable. It is recom-  
mended to AC couple the SDI and SDI inputs as they are inter-  
nally biased to 1.2V.  
SDO, SDO  
If CD/MUTE is used as an input, and set LOW, the equalizer  
serial outputs are not muted. If the CD/MUTE is used as an input  
and is set HIGH, then the equalizer serial outputs are muted.  
The CYV270M0101EQ has differential serial output interface  
drivers that use current mode logic [CML] drivers to provide  
source matching for the transmission line. These outputs are  
either AC coupled or DC coupled to the HOTLink II SerDes  
device.  
When an invalid signal or a signal transmitted with a launch  
amplitude of less than 500 mV at SD data rates is received, the  
equalizer’s serial outputs are muted and the MCLADJ setting is  
overwritten.  
CLI  
BYPASS  
Cable Length Indicator (CLI) is an analog output that gives an  
output voltage proportional to the equalized cable length. CLI  
gives an approximation of the length of cable at the differential  
serial inputs (SDI, SDI). CLI works at standard definition (SD)  
data rates. The graph in Figure 3 on page 7 illustrates the CLI  
output voltage at various Belden 1694A cable lengths. With an  
increase in cable length, CLI output voltage decreases.  
The CYV270M0101EQ has a bypass mode that allows the user  
to bypass the equalizer’s equalization and DC restoration  
functions. When the Bypass mode is tied to VCC, the signal  
presented at the equalizer’s differential serial inputs (SDI, SDI)  
is routed to the equalizer’s differential serial outputs (SDO, SDO)  
without performing equalization.  
When BYPASS is tied to GND, the incoming video data stream  
is equalized and presented at the equalizer‘s differential serial  
outputs (SDO, SDO).  
In equalizer bypass mode, CD/MUTE is not functional.  
AGC  
Place a capacitor of 1 μF between the AGC± pins of the  
CYV270M0101EQ equalizer.  
Document Number: 001-06830 Rev. *B  
Page 4 of 10  
[+] Feedback  
CYV270M0101EQ  
Power Up Requirements  
Maximum Ratings  
The CYV270M0101EQ contains one power supply. The voltage  
on any input or IO pin must not exceed the power pin during  
power up.  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature.................................. –65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Ambient  
Range  
Temperature  
VCC  
Supply Voltage to Ground Potential................–0.5V to +3.8V  
Commercial  
0°C to +70°C  
+3.3V ±5%  
DC Voltage Applied to Outputs  
in High Z State....................................... –0.5V to VCC + 0.5V  
DC Input Voltage .....................................–0.5V to VCC+0.5V  
Electro Static Discharge (ESD) HBM.......................> 2000 V  
(JEDEC EIA/JESD-A114A)  
Latch Up Current ....................................................> 200 mA  
DC Electrical Characteristics  
Parameter  
VCC  
Description  
Supply Voltage[1]  
Power Consumption[2]  
Supply Current[1]  
Test Conditions  
Min  
3.135  
125  
38  
Typ  
3.3  
160  
48  
Max  
3.465  
190  
60  
Unit  
V
–
–
–
PD  
mW  
mA  
V
IS  
VCMOUT  
Output Common Mode Voltage[1]  
Load = 50Ω  
–
VCC – ΔVSDO/2  
–
= 2.9  
VCMIN  
Input Common Mode Voltage[1]  
(Bypass = High)  
Input Common Mode Voltage[1]  
(Bypass = Low)  
–
–
1
0
1.4  
2.9  
V
V
–
–
–
–
CLI DC Voltage (0m)[1]  
–
–
–
–
2.2  
1.5  
2.65  
1.9  
1.3  
0.72  
–
2.95  
2.3  
V
V
V
V
V
V
V
CLI DC Voltage (No Signal)[1]  
Floating MCLADJ DC Voltage[1]  
MCLADJ Range[3]  
0.4  
2.8  
–
1.02  
–
VCD/MUTE(OH) CD/MUTE Output Voltage[1]  
Carrier Not Present  
Carrier Present  
VCD/MUTE(OL)  
–
0.8  
–
VCD/MUTE  
VCD/MUTE  
CD/MUTE Input Voltage Required to Min to Mute  
Force Outputs to Mute[1]  
2.5  
–
CD/MUTE Input Voltage Required to Max to Activate  
Force Active[1]  
–
–
1
V
Notes  
1. Production test.  
2. Calculated results from production test.  
3. Not tested. Based on characterization.  
Document Number: 001-06830 Rev. *B  
Page 5 of 10  
[+] Feedback  
CYV270M0101EQ  
AC Electrical Characteristics  
Parameter  
Description  
Serial Input Data Rate[1]  
Input Voltage Swing  
Test Conditions  
Min  
143  
500[5]  
Typ  
Max  
360  
Unit  
Mbps  
mV  
–
–
–
VSDI  
Single-ended, at the transmitter,  
SD data rate  
1200  
ΔVSDO  
Output Voltage Swing[1]  
Differentialp-p, 50Ω load  
450  
–
700  
0.2[1]  
950  
–
mV  
UI  
–
Output Jitter for Various Cable  
Lengths and Data Rates  
270 Mbps  
Belden 1694A: 0-350m  
Canare L-5CFB: 0-350m  
800 mV transmit amplitude  
Equalizer pathological pattern  
–
–
–
–
–
–
–
–
Output Rise/Fall Time[3, 4]  
Mismatch in Rise/Fall Time[3, 4]  
Duty Cycle Distortion[3, 4]  
Overshoot[3, 4]  
Input Return Loss[3, 4]  
Input Resistance[3]  
20% - 80%  
80  
–
120  
–
350  
30  
–
ps  
ps  
UI  
%
–
SD Color Bar Pattern  
–
–
0.03  
–
–
10  
–
–
-15  
–
–
dB  
kΩ  
pF  
Ω
Single-ended  
Single-ended  
Single-ended  
2.5  
1
–
Input Capacitance[3]  
Output Resistance[3]  
–
–
–
50  
–
Notes  
4. Not tested. Guaranteed by design simulations.  
5. Based on characterization across temperature and voltage with 350m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.  
Document Number: 001-06830 Rev. *B  
Page 6 of 10  
[+] Feedback  
CYV270M0101EQ  
Typical Performance Graphs  
(Unless otherwise stated, VCC = 3.3V, TA = 25°C)  
Figure 2. MCLADJ Input Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2
1.9  
1.8  
1.7  
0
50  
100  
150  
200  
250  
300  
350  
CABLE LENG TH (m )  
Figure 3. CLI Output Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate  
2.7  
2.6  
2.5  
2.4  
2.3  
2.2  
2.1  
2
1.9  
1.8  
1.7  
0
50  
100  
150  
200  
250  
300  
350  
C ABLE LENG TH (m )  
Document Number: 001-06830 Rev. *B  
Page 7 of 10  
[+] Feedback  
CYV270M0101EQ  
Typical Application Circuit  
Figure 4. Interfacing CYV270M0101EQ to the HOTLink II SerDes  
C D / M U T E  
C L I  
+3.3V  
+3.3V  
C12  
C10  
0.01 μF  
0. 01 μF  
LFI  
R XLE  
SDASEL  
LPEN  
BNC JACK  
R XD 7  
R XD 6  
R XD 5  
R XD 4  
R XD 3  
R XD 2  
R XD 1  
R XD 0  
R XO P  
R XS T2  
R XS T1  
R XS T0  
R XC LK +  
R16  
1 μF  
1 μF  
C15  
C16  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
C D / M U T E  
V C C  
75Ω  
C L I  
V C C  
V E E  
S D I  
IN SEL  
75 Ω  
L2  
Z0  
Z0  
IN1+  
V E E  
S D O  
2 Z0  
R18  
S D O  
S D I  
6.4 n H  
IN1  
−
V E E  
V E E  
M C L A D J  
B Y P A S S  
A G C +  
FR AMC HAR  
RFEN  
A G C  
−
+
37.4 Ω  
75 Ω  
1 μF  
C11  
R FMOD E  
D EC MOD E  
RXCKSEL  
RXMOD E  
RXRATE  
R15  
R14  
CYV270M0101EQ  
R XC LK  
−
R XC LK C+  
M C L A D J  
CYV15G0101DXB  
Document Number: 001-06830 Rev. *B  
Page 8 of 10  
[+] Feedback  
CYV270M0101EQ  
Ordering Information  
Operating  
Range  
Ordering Code  
Package Name  
Package Type  
CYV270M0101EQ-SXC  
SZ16.15  
Pb-Free 16-Pin 150 Mil SOIC  
0 to 70°C  
Package Dimensions  
Figure 5. 16-Pin (150 Mil) SOIC S16.15  
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Document Number: 001-06830 Rev. *B  
Page 9 of 10  
[+] Feedback  
CYV270M0101EQ  
Document History Page  
Document Title: CYV270M0101EQ Adaptive Video Cable Equalizer  
Document Number: 001-06830  
Issue  
Date  
Orig. Of  
Change  
Rev.  
Ecn No.  
Description Of Change  
New preliminary datasheet  
**  
427547  
663916  
SEE ECN  
SEE ECN  
BCD  
FRE  
*A  
Updated AC and DC parameters. Changed datasheet status from  
preliminary to final  
*B  
1396423  
SEE ECN  
UKK/AESA  
Updated AC and DC electrical characteristics and pin description of  
CD/MUTE and MCLADJ  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-06830 Rev. *B  
Revised October 25, 2007  
Page 10 of 10  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. HOTLink is a registered trademark and  
HOTLink II is a trademark of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and company names  
mentioned in this document may be the trademarks of their respective holders.  
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厂商 型号 描述 页数 下载

CYPRESS

 		CYV15G0100EQ 准专业型视频电缆均衡器[ Prosumer Video Cable Equalizer ] 10 页

CYPRESS

 		CYV15G0100EQ-SXC 准专业型视频电缆均衡器[ Prosumer Video Cable Equalizer ] 10 页

CYPRESS

 		CYV15G0101DXB 单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ] 39 页

CYPRESS

 		CYV15G0101DXB-BBC 单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ] 39 页

CYPRESS

 		CYV15G0101DXB-BBI 单通道的HOTLink收发器[ Single-channel HOTLink Transceiver ] 39 页

CYPRESS

 		CYV15G0101DXB-BBXC 单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ] 39 页

CYPRESS

 		CYV15G0101DXB-BBXI 单通道的HOTLink II ™收发器[ Single-channel HOTLink II⑩ Transceiver ] 39 页

CYPRESS

 		CYV15G0101EQ 多码率视频电缆均衡器（ SOIC ）[ Multi-Rate Video Cable Equalizer (SOIC) ] 10 页

CYPRESS

 		CYV15G0101EQ-SXC 多码率视频电缆均衡器（ SOIC ）[ Multi-Rate Video Cable Equalizer (SOIC) ] 10 页

CYPRESS

 		CYV15G0101EQ_07 多速率视频电缆均衡器[ Multi Rate Video Cable Equalizer ] 10 页

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