XTR300AIRGWTG4,PDF,XTR300AIRGWTG4 PDF资料,Datasheet,下载XTR300AIRGWTG4技术资料

XTR300

SBOS336B − JUNE 2005 − REVISED MARCH 2006

Industrial Analog Current/Voltage

OUTPUT DRIVER

F_DEATURES

A_DPPLICATIONS

USER-SELECTABLE: Voltage or Current

Output

PLC OUTPUT PROGRAMMABLE DRIVER

D

INDUSTRIAL CROSS-CONNECTORS

INDUSTRIAL HIGH-VOLTAGE I/O

D

+40V SUPPLY VOLTAGE

V

I

: 10V (up to 17.5V at 20V supply)

OUT

3-WIRE-SENSOR CURRENT OR VOLTAGE

OUTPUT

: 20mA (linear up to 24mA)

OUT

SHORT- OR OPEN-CIRCUIT FAULT

INDICATOR PIN

D

10V 2- AND 4-WIRE VOLTAGE OUTPUT

Patents Pending

D

NO CURRENT SHUNT REQUIRED

OUTPUT DISABLE FOR SINGLE INPUT MODE

THERMAL PROTECTION

DESCRIPTION

The XTR300 is a complete output driver for industrial and

process control applications. The output can be configured

as current or voltage by the digital I/V select pin. No

external shunt resistor is required. Only external

gain-setting resistors and a loop compensation capacitor

are required.

OVER-CURRENT PROTECTION

SEPARATE DRIVER AND RECEIVER

CHANNELS

D

DESIGNED FOR TESTABILITY

The separate driver and receiver channels provide

flexibility. The Instrumentation Amplifier (IA) can be used

for remote voltage sense or as a high-voltage, high-

impedance measurement channel. In voltage output

mode, a copy of the output current is provided, allowing

calculation of load resistance.

C

−

V

XTR300 V+

Current Copy

I

MON

R

1k

I

IMON

Ω

COPY

The digital output selection capability, together with the

error flags and monitor pins, make remote configuration

and troubleshooting possible. Fault conditions on the

output and on the IA input as well as over-temperature

conditions are indicated by the error flags. The monitoring

pins provide continuous feedback about load power or

impedance. For additional protection, the maximum output

current is limited and thermal protection is provided.

I

DRV

Input Signal

(Optional)

V

IN

DRV

OPA

SET

IA

IN+

R

SET

OS

I

IA

RG

1

R

Load

IA

GAIN

RG

2

GND1

V

REF

IA

IN

−

IA

OUT

GND2

EF

R

IA

OD

M1

M2

CM

Digital communication like HART can be modulated onto

the input signal. The receive signal applied to the output

can be detected at the monitor pins in both current and

voltage output modes. In addition to HART

communication, the device offers system or sensor

configuration through the signal connector.

Ω

1k

EF

Digital

Error

Flags

LD

OT

Control

EF

GND3

DGND

The XTR300 is specified over the −40°C to +85°C

industrial temperature range and for supply voltage up to

40V.

Figure 1. XTR300 Basic Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

HART is a registered trademark of the HART Communication Foundation.

All other trademarks are the property of their respective owners.

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Copyright  2005−2006, Texas Instruments Incorporated

www.ti.com

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

(1)

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V

handledwith appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

Signal Input Terminals

(2)

Voltage . . . . . . . . . . . . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

(2)

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

(3)

Output Short Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

ESD Rating

ORDERING INFORMATION⁽¹⁾

PACKAGE

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V

DESIGNATOR MARKING

PRODUCT PACKAGE-LEAD

QFN-20

XTR300

(1)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

RGW

XTR300

(5mm x 5mm)

(1)

For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see

the TI web site at www.ti.com.

(2)

(3)

Input terminals are diode-clamped to the power-supply rails.

Input signals that can swing more than 0.5V beyond the supply

rails should be current limited.

PIN ASSIGNMENTS

See the Driver Output Disable section in Application Information

section for thermal protection.

1

NAME

M2

FUNCTION

Mode Input

2

M1

Mode Input

3

V

Noninverting Signal Input

Input for Gain Setting; Inverting Input

Current Monitor Output

IN

PIN CONFIGURATION

4

SET

5

I

MON

Top View

QFN

6

IA

Instrumentation Amplifier Signal Output

Instrumentation Amplifier Inverting Input

Instrumentation Amplifier Noninverting Input

Instrumentation Amplifier Gain Resistor

Negative Power Supply

OUT

7

IA

−

IN

IN+

8

20 19 18 17 16

9

RG1

RG2

V−

10

11

12

13

14

15

16

17

1

2

3

4

5

15

14

13

V+

M2

M1

Exposed

Thermal

Die Pad

on

Underside.

(Must be

connected

NC

No Internal Connection

NC

DRV

NC

Operational Amplifier Output

No Internal Connection

DRV

V_IN

12 NC

11

SET

I_MON

V+

Positive Power Supply

DGND

Ground for Digital I/O

−

to V )

−

V

EF

Error Flag for Common-Mode Over-Range,

Active Low

CM

6

7

8

9

10

18

EF

Error Flag for Load Error, Active Low

Error Flag for Over Temperature, Active Low

Output Disable, Disabled Low

LD

Pad

19

EF

OT

20

OD

Pad

Exposed thermal pad must be connected to V−

2

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: VOLTAGE OUTPUT MODE

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

=

20V, R

= 800Ω, R

= 2kΩ, R = 2kΩ, V

= 4V, R

= 10kΩ, Input Signal Span 0V to 4V, and C = 100pF, unless

A

S

LOAD

SET

OS

REF

GAIN

C

otherwise noted.

XTR300

PARAMETER

MIN

TYP

MAX

CONDITION

UNITS

OFFSET VOLTAGE

Offset Voltage, RTI

vs Temperature

vs Power Supply

V

0.4

1.6

0.2

1.9

6

mV

OS

dV /dT

OS

PSRR

µV/°C

µV/V

V

S

=

5V to 22V

10

INPUT VOLTAGE RANGE

Nominal Setup for 10V Output

See Figure 2

Input Voltage For Linear Operation

(V−) + 3V

(V+) − 3V

V

NOISE

Voltage Noise, f = 0.1Hz to 10Hz, RTI

Voltage Noise Density, f = 1kHz, RTI

3

µV

nV/√Hz

PP

e

n

40

OUTPUT

Voltage Output Swing from Rail

Gain Nonlinearity

vs Temperature

Gain Error

I

≤ 15mA

(V−) +3V

(V+) − 3

V

%FS

ppm/°C

%FS

ppm/°C

mΩ

DRV

0.01

0.1

0.04

0.2

7

0.1

1

I

0.1

1

B

vs Temperature

Output Impedance, dV

/dI

DRV DRV

(1)

Output Leakage Current While Output Disabled

Short-Circuit Current

Pin OD = L

30

nA

I

15

20

24

mA

SC

(2)

Capacitive Load Drive

C

LOAD

C = 10nF, R = 15

C C

1

µF

Rejection of Voltage Difference between GND1 and GND2, RTO

130

dB

FREQUENCY RESPONSE

Bandwidth

−3dB

SR

G = 5

300

1

kHz

V/µs

µs

(2)

Slew Rate

SR

C

= 10nF, C = 1µF, R = 15Ω

0.015

8

L

C

(2)(3)

Settling Time

, 0.1%, Small Signal

V

= 1V

DRV

Overload Recovery Time

50% Overdrive

12

µs

(1)

(2)

(3)

Output leakage includes input bias current of INA.

Refer to Driving Capacitive Loads section in Application Information.

8µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

C

−

V

XTR300 V+

Current Copy

I

MON

R

I

IMON

Ω

COPY

1k

I

DRV

Input Signal

= 0V to 4.0V

V

GND3

IN

V

IN

DRV

OPA

Transfer Function:

SET

IA

−

V_INV_REF

IN+

R_G

2

V_IN

V_OUT

=

+

R

(

)

I

OS

SET

IA

RG

1

R_SET

R_OS

R

Load

IA

GAIN

RG

2

V

= 4.0V

REF

IA

IN−

IA

OUT

EF

CM

OD

M1

M2

H

L

EF

LD

Digital

Error

Flags

Control

EF

OT

DGND

∆

V

GND

GND2

GND1

Figure 2. Standard Circuit for Voltage Output Mode

3

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: CURRENT OUTPUT MODE

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

=

20V, R

= 800Ω, R

= 2kΩ, R

= 2kΩ, V = 4V, Input Signal Span 0 to 4V, and C = 100pF, unless otherwise

A

S

LOAD

SET

OS

REF C

noted.

XTR300

PARAMETER

MIN

TYP

MAX

CONDITION

UNITS

OFFSET VOLTAGE

Input Offset Voltage

vs Temperature

vs Power Supply

V

Output Current < 1µA

0.4

1.5

0.2

1.8

6

mV

OS

dV /dT

OS

PSRR

µV/°C

µV/V

V

S

=

5V to 22V

10

INPUT VOLTAGE RANGE

Nominal Setup for 20V Output

Maximum Input Voltage For Linear Operation

See Figure 3

(V−) + 3

(V+) − 3

V

NOISE

Voltage Noise, f = 0.1Hz to 10Hz, RTI

Voltage Noise Density, f = 1kHz, RTI

3

µV

nV/√Hz

PP

i

33

n

OUTPUT

Compliance Voltage Swing from Rail

I

=

24mA

(V−) +3

(V+) − 3

V

DRV

Output Conductance, (dI

Transconductance

Gain Error

/dV

)

dV

DRV

=

15V, dI

=

24mA

0.7

µA/V

DRV

See Transfer Function

I

=

24mA

0.04

3.6

0.01

1.5

0.6

32

0.12

10

%FS

ppm/°C

%FS

ppm/°C

nA

DRV

vs Temperature

Linearity Error

I

DRV

I

0.1

6

B

DRV

vs Temperature

I

DRV

Output Leakage Current While Output Disabled

Short-Circuit Current

Pin OD = L

I

24.5

38.5

mA

SC

(1)(2)

Capacitive Load Drive

C

LOAD

1

µF

FREQUENCY RESPONSE

Bandwidth

−3dB

SR

160

1.3

8

kHz

mA/µs

µs

(2)

Slew Rate

(2)(3)

Settling Time

, 0.1%, Small Signal

I

=

2mA

DRV

Overload Recovery Time

C

LOAD

= 0, 50% Overdrive

1

µs

(1)

(2)

(3)

Refer to Driving Capacitive Loads section in Application Information.

With capacitive load, the slew rate can be limited by the short circuit current and the load error flag can trigger during slewing.

8µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

C_C

V−

XTR300 V+

Current Copy

I_MON

I_COPY

I_DRV

Input Signal

V_IN= 0V to 4.0V

V_IN

DRV

IA_IN+

OPA

SET

Transfer Function:

V_IN

−

V_INV_REF

R_OS

R_SET

I_IA

I_OUT= 10

+

RG₁

RG₂

(

)

R_SET

R_OS

IA

V_REF= 4.0V

IA_IN

−

IA_OUT

I_OUT

EF_CM

EF_LD

EF_OT

OD

M1

M2

H

Digital

Control

Error

Flags

L

H

DGND

GND1

GND2

Figure 3. Standard Circuit for Current Output Mode

4

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

=

20V, R

= 800Ω, unless otherwise noted.

A

S

LOAD

XTR300

TYP

PARAMETER

MIN

MAX

CONDITION

UNITS

OFFSET VOLTAGE

Offset Voltage, RTI

Drift

V

I

= 0A

0.4

1.5

0.2

1.8

5

mV

OS

DRV

dV /dT

OS

PSRR

µV/°C

µV/V

vs Power Supply

V

S

=

5V to 22V

INPUT VOLTAGE RANGE

Common-Mode Voltage Range

Common-Mode Rejection Ratio

V

(V−) + 3

100

(V+) − 3

V

CM

CMRR

(V−) + 3V < V

< (V+) − 3V

126

dB

CM

INPUT BIAS CURRENT

Input Bias Current

I

20

35

10

nA

B

Input Offset Current

I

0.3

OS

INPUT IMPEDANCE

Differential

8

10 || 5

Ω || pF

8

Common-Mode

10 || 5

OPEN-LOOP GAIN

Open-Loop Voltage Gain

A

OL

(V−) + 3V < V

< (V+) − 3V , I =

DRV

24mA

100

126

dB

DRV

OUTPUT

Voltage Output Swing from Rail

Short-Circuit Current

I

=

24mA

(V−) + 3

25.5

(V+) − 3

38.5

V

DRV

I

M2 = High

M2 = Low

Pin OD = L

32

20

mA

pA

LIMIT

16

24

LIMIT

Output Leakage Current While Output Disabled

I

10

LEAK_DRV

FREQUENCY RESPONSE

Gain-Bandwidth Product

Slew Rate

GBW

SR

G = 1

2

1

MHz

V/µs

5

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: INSTRUMENTATION AMPLIFIER (IA)

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

=

20V, R = 2kΩ, and R

= 2kΩ, unless otherwise noted. See Figure 4.

A

S

IA

GAIN

XTR300

TYP

PARAMETER

CONDITION

MIN

MAX

UNITS

OFFSET VOLTAGE

Offset Voltage, RTI

vs Temperature

vs Power Supply

V

I

= 0A

DRV

0.7

2.4

0.8

2.7

10

mV

OS

dV /dT

OS

µV/°C

µV/V

V

=

5V to 22V

PSRR

S

INPUT VOLTAGE RANGE

V

Common-Mode Voltage Range

Common-Mode Rejection Ratio

(V−) + 3

100

(V+) − 3

V

CM

CMRR

RTI

130

dB

INPUT BIAS CURRENT

Input Bias Current

I

20

1

35

10

nA

B

I

Input Offset Current

OS

INPUT IMPEDANCE

Differential

8

10 || 5

Ω || pF

8

10 || 5

Common-Mode

TRANSCONDUCTANCE (Gain)

Transconductance Error

vs Temperature

IA

= 2 (IA

− IA )/R

OUT

IN+ IN− GAIN

IA

OUT

=

2.4mA, (V−) + 3V < V

< (V+) − 3V

0.04

0.2

0.01

20

0.1

%FS

ppm/°C

%FS

nA

IAOUT

(V−) + 3V < V

< (V+) − 3V

Linearity Error

IAOUT

Input Bias Current to G1, G2

(1)

Input Offset Current to G1, G2

1

nA

OUTPUT

Output Swing to the Rail

Output Impedance

Short-Circuit Current

(V−) + 3

(V+) − 3

V

IA

=

2.4mA

OUT

600

7.2

4.5

MΩ

mA

OUT

I

M2 = High

M2 = Low

LIMIT

FREQUENCY RESPONSE

Gain-Bandwidth Product

Slew Rate

GBW

SR

MHz

G = 1, R

= 10kΩ, R = 5kΩ

1

GAIN

IA

G = 1, R

= 10kΩ, R = 5kΩ

V/µs

GAIN

IA

=

40µA, R

= 10kΩ, R = 5kΩ,

= 100pF

OUT

GAIN IA

(2)

Settling Time , 0.1%

6

µs

C

L

Overload Recovery Time, 50%

R

= 10kΩ, R = 15kΩ, C = 100pF

10

GAIN

IA

L

(1)

(2)

See Typical Characteristics curve.

6µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

ELECTRICAL CHARACTERISTICS: CURRENT MONITOR

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

= 20V, unless otherwise noted. See Figure 4.

A

S

XTR300

TYP

PARAMETER

MIN

MAX

UNITS

CONDITION

OUTPUT

Offset Current

vs Temperature

vs Power Supply

I

= 0A

30

0.06

0.1

100

nA

nA/°C

nA/V

V

OS

DRV

dI /dT

OS

PSRR

V

=

5V to 22V

10

S

Monitor Output Swing to the Rail

Monitor Output Impedance

I

=

2.4mA

(V−) + 3

(V+) − 3

MON

200

MΩ

MON

MONITOR CURRENT GAIN

Current Gain Error

vs Temperature

I

= I

/10

DRV

MON

I

=

24mA

0.04

3.6

0.12

0.1

%FS

ppm/°C

%FS

DRV

I

=

DRV

Linearity Error

I

=

0.01

1.5

DRV

vs Temperature

I

=

ppm/°C

DRV

6

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the temperature range, T_A= −40°C to +85°C.

All specifications at T = +25°C, V

=

20V, unless otherwise noted. See Figure 4.

A

S

XTR300

PARAMETER

MIN

TYP

MAX

UNITS

CONDITION

POWER SUPPLY

Specified Voltage Range

Operating Voltage Range

Quiescent Current

V

S

5

20

22

V

mA

I

Q

I

= IA = 0A

OUT

1.8

2.3

2.8

DRV

Over Temperature

TEMPERATURE RANGE

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Resistance

−40

−55

+85

°C

(1)

+125

Junction-to-Case

q

6

°C/W

JC

Junction-to-Ambient

q

38

JA

THERMAL FLAG (EF ) Output

OT

Alarm (EF pin LOW)

OT

140

125

°C

Return to Normal Operation (EF pin HIGH)

OT

DIGITAL INPUTS (M1, M2, OD)

V

Low-Level Input Voltage

High-Level Input Voltage

≤0.8

≥1.4

1

V

IL

IH

Input Current

DIGITAL OUTPUTS (EF , EF , EF )

OT

µA

LD

CM

I

High-Level Leakage Current (Open-Drain)

Low-Level Output Voltage

−1.2

0.8

µA

V

OH

V

I

= 5mA

OL

Low-Level Output Voltage

I

= 2.8mA

0.4

V

OL

DIGITAL GROUND PIN

(V−) ≤ DGND ≤ (V+) − 7V

Current Input

M1 = M2 = L, OD = H, All Digital Outputs H

−25

µA

(1)

EF not connected with OD.

OT

Feedback

Network

V

−

XTR300 V+

Current Copy

I_MON

I_COPY

I_DRV

GND3

Input Signal

V_IN

DRV

IA_IN+

OPA

SET

R_SET

I_IA

RG₁

RG₂

R_GAIN

IA

GND1

IA_IN

−

IA_OUT

EF_CM

EF_LD

EF_OT

OD

M1

M2

R

IA

Digital

Control

Error

Flags

H

DGND

GND3

Figure 4. Standard Circuit for Current Output Mode

7

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TYPICAL CHARACTERISTICS

At T = +25°C and V+ = 20V, unless otherwise noted.

A

QUIESCENT CURRENT vs TEMPERATURE

3.0

QUIESCENT CURRENT vs SUPPLY VOLTAGE

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

2.5

2.0

1.5

1.0

0.5

0

−

25

50

0

25

50

75

100

125

10

15

20

25

30

35

40

45

_

Temperature ( C)

Total Supply Voltage (V)

INPUT BIAS CURRENT vs TEMPERATURE

(V_IN, SET, IA_IN+, IA_IN−, RG1, RG2)

OPA OUTPUT SWING TO RAIL vs TEMPERATURE

I_DRV= +24mA

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0

−

= 24mA

I_DRV

−

5

10

15

20

25

30

I_DRV= +20mA

−

I_DRV= +10mA

−

= 10mA

I_DRV

−

= 20mA

I_DRV

−

25

50

25

0

25

50

75

100

125

50

0

25

50

75

100

125

_

Temperature ( C)

IA GAIN AND PHASE

vs FREQUENCY

OPA GAIN AND PHASE vs FREQUENCY

80

60

40

20

0

180

160

140

120

100

80

0

−

Ω

R_GAIN= 10k

20

−

45

40

Ω

R_IA= 500k

60

90

Phase

80

Ω

R_IA= 50k

135

180

225

270

100

120

140

160

180

200

Ω

R_IA= 10k

60

40

Ω

R_IA= 5k

Gain

20

−

20

40

Ω

R_IA= 1k

100k

Gain

0

Phase

−

20

0.001 0.01 0.1

1

10

100

1k

10k

1M

10M

1

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

8

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C and V+ = 20V, unless otherwise noted.

A

OPA CMRR AND PSRR vs FREQUENCY

160

IA CMRR AND PSRR vs FREQUENCY

140

120

100

80

140

120

100

PSRR+

−

PSRR

80

60

40

20

0

−

PSRR

60

CMRR

PSRR+

40

CMRR

20

0

1

10

100

1k

10k

100k

1

10

100

1k

10k

100k

Frequency (Hz)

SMALL−SIGNAL STEP RESPONSE

CURRENT MODE

LARGE−SIGNAL STEP RESPONSE

CURRENT MODE

µ

= 200 A

G = 8

C_L= 100nF || R_L= 800

C_C= 4.7nF

I_OUT

G = 8

C_L= 100nF || R_L= 800

= 20mA

Ω

C_C= 4.7nF

Ω

R_SET= 1k

R_G= 10k

Ω

R_SET= 1k

R_G= 10k

See Figure 3

µ

200 s/div

µ

200 s/div

LARGE−SIGNAL STEP RESPONSE

VOLTAGE MODE

SMALL−SIGNAL STEP RESPONSE

VOLTAGE MODE

G = 5

Ω

C_L= 100nF || R_L= 800

C_C= 4.7nF

C_L= 100nF || R_L= 800

C_C= 4.7nF

Ω

R_SET= 1k

Ω

R_SET= 1k

Ω

R_G= 10k

See Figure 2

µ

200 s/div

µ

200 s/div

9

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS (continued)

At T = +25°C and V+ = 20V, unless otherwise noted.

A

INPUT−REFERRED NOISE SPECTRUM

VOLTAGE OUTPUT MODE

INPUT−REFERRED 0.1Hz to 10Hz NOISE

VOLTAGE OUTPUT MODE

1M

G = 5

100k

10k

1k

100

10

1

10

100

1k

10k

100k

1s/div

Frequency (Hz)

INPUT−REFERRED NOISE SPECTRUM

CURRENT OUTPUT MODE

INPUT−REFERRED 0.1Hz to 10Hz NOISE

CURRENT OUTPUT MODE

1M

100k

10k

1k

G = 10

100

10

1

10

100

1k

10k

1s/div

Frequency (Hz)

IA INPUT−REFERRED NOISE SPECTRUM

G = 20

IA INPUT−REFERRED 0.1Hz to 10Hz NOISE

1M

100k

10k

1k

100

10

1

10

100

1k

10k

1s/div

Frequency (Hz)

10

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C and V+ = 20V, unless otherwise noted.

A

OPA OFFSET VOLTAGE DISTRIBUTION

18

IA OFFSET VOLTAGE DISTRIBUTION

30

25

20

15

10

5

16

14

12

10

8

6

4

2

0

Offset Voltage (mV)

OPA OFFSET VOLTAGE DRIFT DISTRIBUTION

60

IA OFFSET VOLTAGE DRIFT DISTRIBUTION

40

35

30

25

20

15

10

5

50

40

30

20

10

0

µ

_

µ

_

Offset Voltage Drift ( V/ C)

VOLTAGE MODE GAIN ERROR DISTRIBUTION

CURRENT MODE GAIN ERROR DISTRIBUTION

40

35

30

25

20

15

10

5

30

25

20

15

10

5

0

Gain Error (ppm)

11

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C and V+ = 20V, unless otherwise noted.

A

VOLTAGE MODE NONLINEARITY DISTRIBUTION

60

CURRENT MODE NONLINEARITY DISTRIBUTION

60

50

40

30

20

10

0

50

40

30

20

10

0

Nonlinearity (ppm)

VOLTAGE MODE GAIN

CURRENT MODE GAIN

ERROR DRIFT DISTRIBUTION

70

ERROR DRIFT DISTRIBUTION

60

50

40

30

20

10

0

50

40

30

20

10

0

_

Gain Error Drift (ppm/ C)

CURRENT MODE

VOLTAGE MODE

NONLINEARITY DRIFT DISTRIBUTION

80

NONLINEARITY DRIFT DISTRIBUTION

100

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

_

Nonlinearity Drift (ppm/ C)

12

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C and V+ = 20V, unless otherwise noted.

A

POSITIVE CURRENT LIMIT vs TEMPERATURE

36

NEGATIVE CURRENT LIMIT vs TEMPERATURE

Voltage Mode

−

16

18

20

22

24

26

28

30

32

34

36

34

32

30

28

26

24

22

20

18

16

Current Mode

Voltage Mode

Current Mode

−

25

50

25

0

25

50

75

100

125

50

0

25

50

75

100

125

_

Temperature ( C)

NONLINEARITY vs OUTPUT CURRENT

( 24mA End Point Calibration)

NONLINEARITY vs OUTPUT CURRENT

( 20mA End Point Calibration)

0.025

0

0.025

0

−

_

55 C

_

+25 C

_

−

_

+25 C

55 C

−

0.025

0.050

0.075

0.025

0.050

0.075

_

+85 C

+125 C

_

+85 C

_

+125 C

−

0.10

−

8

−

4

24 20 16 12

8

4

0

4

8

12 16 20 24

24 20 16 12

0

4

8

12 16 20 24

Output Current (mA)

13

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APPLICATION INFORMATION

−

V

GND

V+

C₂

100nF

C₃

100nF

C_C

47nF

GND1

(2)

Thermal

Pad

−

V

XTR300 V+

Current Copy

I_COPY

I_MON

I−MON

R₃

I_DRV

Ω

1k

V_IN

R_C

External Load

S−IN

OS

Ω

15

DRV

R_OS

OPA

Ω

2k

C₄

SET

100nF R₆

Ω

2.2k

IA_IN+

RG₁

RG₂

IA_IN−

GND1

R_IMON

R_SET

C_LOAD

R_LOAD

Ω

1k

I_IA

R_GAIN

C₅

SG

IA

R₇

Ω

10k

10nF

2.2k

GND1

IA−O

IA_OUT

GND2

EF_CM

EF_LD

EF_OT

OD

M1

M2

R_IA

Logic Supply

(+2.7V to +5V)

Digital

Control

Error

Flags

Ω

1k

DGND

GND3

(1)

Pull−up Resistors

Ω

(10k )

GND4

NOTE: (1) See the Electrical Characteristics and Digital Input and Output section for operating limits of DGND.

−

(2) Connect thermal pad to V .

The following information should be considered during XTR300 circuit configuration:

D

Recommended bypassing: 100nF or more for

supply bypassing at each supply.

D

R , R , and C protect the IA.

6

7

5

D

R

and C

represent the load resistance and

LOAD

R

can be in the kΩ-range or short-circuited if not

load capacitance.

IMON

used. Do not leave this current output

D

R

SET

defines the transfer gain. It can be split to allow

unconnected—it would saturate the internal current

a signal offset and, therefore, allow a 5V single-

supply digital-to-analog converter (DAC) to control a

10V or 20mA output signal.

source. The current at this I

output is I

(I /10).

IMON DRV

/10.

MON

DRV

Therefore, V

= R

IMON

D

R is not required but can match R

to compensate for the bias current.

(or R

||R

)

3

SET

SET OS

The XTR300 can be used with asymmetric supply voltages;

however, the minimum negative supply voltage should be

equal to or more negative than −3V (typically −5V). This sup-

ply value ensures proper control of 0V and 0mA with wire re-

sistance, ground offsets, and noise added to the output. For

positive output signals, the current requirement from this

negative voltage source is less than 5mA.

R

can be short-circuited if not used. Do not leave

IA

this current output unconnected. R

10kΩ to match the output of 10V with 20mA for the

equal input signal.

is selected to

GAIN

D

R ensures stability for unknown load conditions

C

GND1 through GND4 must be selected to fulfill speci−

fied operating ranges. DGND must be in the range of

(V−) ≤ DGND ≤ (V+) −7V.

and limits the current into the internal protection

diodes. C helps protect the device. Over-voltage

4

clamp diodes (standard 1N4002) might be

necessary to protect the output.

Figure 5. Standard Circuit Configuration

14

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Built on a robust high-voltage BI-CMOS process, the

XTR300 is designed to interface the 5V or 3V supply do-

main used for processors, signal converters, and amplifi-

ers to the high-voltage and high-current industrial signal

environment. It is specified for up to 20V supply, but can

also be powered asymmetrically (for example, +24V and

−5V). It is designed to allow insertion of external circuit

protection elements and drive large capacitive loads.

C

−

V

XTR300 V+

Current Copy

I

MON

I

COPY

R

IMON

I

DRV

GND3

Input Signal

V

FUNCTIONAL FEATURES

IN

DRV

OPA

The XTR300 provides two basic functional blocks: an in-

strumentation amplifier (IA) and a driver that is a unique

operational amplifier (OPA) for current or voltage output.

This combination represents an analog output stage which

can be digitally configured to provide either current or volt-

age output to the same terminal pin. Alternatively, it can be

configured for independent measurment channels.

SET

IA

IN+

R

SET

I

IA

RG

1

R

Load

IA

GAIN

RG

2

GND1

IA

IN

−

IA

OUT

EF

OD

M1

M2

CM

GND2

EF

Digital

Error

LD

OT

L

Three open collector error signals are provided to indicate

output related errors such as over-current or open-load

Control

Flags

EF

L

DGND

(EF ) or exceeding the common-mode input range at the

LD

IA inputs (EF ). An over-temperature flag (EF ) can be

CM

OT

used to control output disable to protect the circuit. The

monitor outputs (I and IA ) and the error flags offer

optimal testability during operation and configuration. The

MON

OUT

Figure 6. Simplified Voltage Output Mode

Configuration

I

output represents the current flowing into the load in

MON

voltage output mode, while the IA

represents the volt-

OUT

Applications not requiring the remote sense feature can

use the OPA in stand-alone operation (M1 = high). In this

case, the IA is available as a separate input channel.

age across the connectors in current output mode. Both

monitor outputs can be connected together when used in

current or voltage output mode because the monitor sig-

nals are multiplexed accordingly.

The IA gain can be set by two resistors, R

and R

:

GAIN

SET

R_GAIN

2R_SET

VOLTAGE OUTPUT MODE

V_OUT

+

V_IN

(1)

In voltage output mode (M1 and M2 are connected low or

left unconnected), the feedback loop through the IA pro-

vides high impedance remote sensing of the voltage at the

destination, compensating the resistance of a protection

circuit, switches, wiring, and connector resistance. The

output of the IA is a current that is proportional to the input

voltage. This current is internally routed to the OPA sum-

ming junction through a multiplexer, as shown in Figure 6.

or when adding an offset, V

with a single-ended input:

, to get bidirectional output

REF

R_GAIN

2

V_IN

R_SET

V_IN* V_REF

ǒ

Ǔ

V_OUT

+

)

R_OS

(2)

The R

resistor is also used in current output mode.

A 1:10 copy of the output current of the OPA can be moni-

SET

Therefore, it is useful to define R

then set the ratio between current and voltage span with

for the current mode,

tored at the I

pin. This output current and the known

SET

MON

output voltage can be used to calculate the load resistance

or load power.

R

.

GAIN

During an output short-circuit or an over-current condition

the XTR300 output current is limited and EF (load error,

LD

active low) flag is activated.

15

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CURRENT OUTPUT MODE

INPUT SIGNAL CONNECTION

The XTR300 does not require a shunt resistor for current

control because it uses a precise current mirror arrange-

ment.

It is possible to drive the XTR300 with a unidirectional input

signal and still get a bidirectional output by adding an addi-

tional resistor, R , and an offset voltage signal, V

. It

REF

OS

can be a mid-point voltage or a signal to shift the output

voltage to a desired value.

In current output mode (M1 connected low, or left uncon-

nected and M2 connected high) a precise copy of 1/10th

of the output is internally routed back to the summing junc-

tion of the OPA through a multiplexer, closing the control

loop for the output current.

This design is illustrated in Figure 8a, Figure 8b, and

Figure 8c. As with a normal operational amplifier, there are

several options for offset-shift circuits. The input can be

connected for inverting or noninverting gain. Unlike many

op amp input circuits, however, this configuration uses cur-

rent feedback, which removes the voltage relationship be-

tween the noninverting input and output potential because

there is no feedback resistor.

The OPA driver can deliver more than 24mA within a wide

output voltage range. An open-output condition or high-im-

pedance load that prevents the flow of the required current

activates the EF flag.

LD

While in current output mode, a current (I ) that is propor-

IA

tional to the voltage at the IA input is routed to IA

and

OUT

a) Noninverting Input

can be used to monitor the load voltage. A resistor con-

verts this current into voltage. This arrangement makes

level shifting easy.

XTR300

V_IN

(0 to V_OFFSET

)

Alternatively, the IA can be used as an independent moni-

toring channel. If this output is not used, connect it to GND

to maintain proper function of the monitor stage, as shown

in Figure 7.

OPA

V_REF

R_OS

R_SET

Ω

2k

Ω

2k

I−Feedback

−

V

XTR300 V+

Current Copy

I

MON

b) Noninverting Input

I

COPY

I

DRV

XTR300

Input Signal

V

IN

V_IN

V_MIDSCALE)

DRV

OPA

(

SET

IA

IN+

OPA

R

SET

I

IA

RG

1

V_MIDSCALE

R

IA

Load

GAIN

RG

2

R_SET

GND1

Ω

1k

IA

IN−

IA

OUT

I−Feedback

GND2

EF

CM

OD

M1

M2

R

IA

EF

LD

Digital

Control

Error

Flags

L

EF

OT

H

DGND

GND3

c) Inverting Input (V

= V

)

REF

OFFSET

XTR300

Figure 7. Simplified Current Output Mode

Configuration

V_REF

The transconductance (gain) can be set by the resistor,

OPA

V_IN

V_OFFSET

R

, according to the equation:

SET

(

)

R_SET

10

R_SET

Ω

1k

I_OUT

+

V_IN

(3)

to get bidirectional output

I−Feedback

or when adding an offset V

with a single-ended input:

REF

V_IN

R_SET

V_IN* V_REF

_{+ 10}ǒ

Ǔ

I_OUT

)

Figure 8. Circuit Options for Op Amp Output

Level-Shifting

R_OS

(4)

16

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The input bias current effect on the offset voltage can be

reduced by connecting a resistor in series with the positive

input that matches the approximate resistance at the neg-

ative input. This resistor placed close to the input pin acts

as a damping element and makes the design less sensitive

ting. When M1 is high, the internal feedback connections

are opened; IA

and I

are both connected to the out-

OUT

MON

put pins; and M2 only determines the current limit (I ) set-

SC

ting.

to RF noise. See R in Figure 5.

3

SUMMARY OF CONFIGURATION MODES⁽¹⁾

M1

M2

MODE

DESCRIPTION

EXTERNALLY-CONFIGURED MODE:

OPA AND IA

L

V

Voltage Output Mode, I = 20mA

OUT

SC

L

H

L

I

Current Output Mode, I = 32mA

SC

OUT

It is possible to use the precision of the operational amplifi-

er (OPA) and instrumentation amplifier (IA) independently

from each other by configuring the digital control pins (M1

H

Ext

IA and I

on ext. pins, I = 20mA

SC

MON

H

Ext

IA and I

on ext. pins, I = 32mA

SC

high). In this mode, the IA output current is routed to IA

(1)

OUT

OD is a control pin independent of M1 or M2. See the Driver

Output Disable section.

and the copy of the OPA output current is routed to I

as shown in Figure 4.

,

MON

Table 1. Mode Configuration

This mode allows external configuration of the analog sig-

nal routing and feedback loop.

The current output IA has high input impedance, low offset

voltage and drift, and very high common-mode rejection

M1 and M2 are pulled low internally with 1µA. Terminate

these two pins to avoid noise coupling.

ratio. An external resistor (R ) can be used to convert the

IA

Output disable (OD) is internally pulled high with approxi-

mately 1µA.

output current of the IA (I ) to an output voltage. The gain

IA

is given by:

2R_IA

R_GAIN

2

R_GAIN

DRIVING CAPACITIVE LOADS AND LOOP

COMPENSATION

I_IA

+

V_INor V_IA

+

V_IN

(5)

For normal operation, the driver OPA and the IA are con-

nected in a closed loop for voltage output. In current output

mode, the current copy closes the loop directly.

The OPA provides low drift and high voltage output swing

that can be used like a common operational amplifier by

connecting a feedback network around it. In this mode, the

In current output mode, loop compensation is not critical,

even for large capacitive loads. However, in voltage output

mode, the capacitive load, together with the source imped-

ance and the impedance of the protection circuit, gener-

ates additional phase lag. The IA input might also be pro-

tected by a low-pass filter that influences phase in the

closed loop.

copy of the output current is available at the I

pin (it in-

MON

cludes the current into the feedback network). It provides

an output current limit for protection, which can be set be-

tween two ranges by M2. The error flag indicates an over-

current condition, as well as indicating driving the output

into the supply rails.

Alternatively, the feedback can be closed through the I

pin to create a precise voltage-to-current converter.

MON

The loop compensation low-pass filter consists of C and

C

the parallel resistance of R and R

. For loop stability

SET

OS

with large capacitive load, the external phase shift has to

be added to the OPA phase. With C , the voltage gain of

the OPA has to approach zero at the frequency where the

C

DRIVER OUTPUT DISABLE

The OPA output (DRV) can be switched to a high-imped-

ance mode by driving the OD control pin low. This input can

total phase approaches 180° + 135°.

The best stability for large capacitive loads is provided by

be connected to the over-temperature flag, EF , and a

OT

adding a small resistor, R (15Ω). See the Output Protec-

C

pull-up resistor to protect the IC from over-temperature by

disconnecting the load.

tion section.

An empirical method of evaluation is using a square wave

input signal and observing the settling after transients. Use

small signal amplitudes only—steep signal edges cause

excessive current to flow into the capacitive load and may

activate the current limit, which hides or prevents oscilla-

tion. A small-signal oscillation can be hidden from large ca-

The output disable mode can be used to sense and mea-

sure the voltage at the IA input pins without loading from

the DRV output. This mode allows testing of any voltage

present at the I/O connector. However, consider the bias

current of the IA input pins.

pacitive loads, but observing the I

propriate resistor (use a similar value like R

indicate stability issues. Note that noise pulses at I

output on an ap-

The digital control inputs, M1 and M2, set the four opera-

tion modes of the XTR300 as shown in Table 1. When M1

is asserted low, M2 determines voltage or current mode

MON

||R ) would

SET OS

dur-

MON

and the corresponding appropriate current limit (I ) set-

SC

17

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ing overload (EF active) are normal and are caused by

LD

cycling of the current mirror.

Current Mirror

I_R

The voltage output mode includes the IA in the loop. An

additional low-pass filter in the input reverses the phase

and therefore increases the signal bandwidth of the loop,

but also increases the delay. Again, loop stability has to be

observed. Overloading the IA disconnects the closed loop

and the output voltage rails.

I_R

IA_IN+

A1

Current Mirror

INTERNAL CURRENT SOURCES,

I_R

SWITCHING NOISE, AND SETTLING TIME

R_GAIN

The accuracy of the current output mode and the DC per-

formance of the IA rely on dynamically-matched current

mirrors.

I_R

2I_R

Identical current sources are rotated to average out mis-

match errors. It can take several clock cycles of the internal

100kHz ocsillator (or a submultiple of that frequency) to

reach full accuracy. This may dominate the settling time to

the 0.1% accuracy level and can be as much as 100µs in

current output mode or 40µs in voltage output mode.

2I_R

I_IA

A2

IA_IN

−

2I_R

Current Mirror

A small portion of the switching glitches appear at the DRV

output, and also at the I

and IA

outputs. The stan-

MON

dard circuit configuration, with R , C , and C , which are

C

4

C

Figure 9. IA Block Diagram

required for loop compensation and output protection, also

helps reduce the noise to negligible levels at the signal out-

put. If necessary, the monitor outputs can be filtered with

a shunt capacitor.

The output current, IA , of the instrumentation amplifier

OUT

is limited to protect the internal circuitry. This current limit

has two settings controlled by the state of M2 (see Electri-

cal Characteristics, Short-Circuit Current specification).

Note that if R

is too small, the current output limitation

IA STRUCTURE, VOLTAGE MONITOR

SET

of the instrumentation amplifier can disrupt the closed loop

of the XTR300 in voltage output mode. With M2 = low, the

The instrumentation amplifier has high-impedance NPN

transistor inputs that do not load the output signal, which

is especially important in current output mode. The output

signal is a controlled current that is multiplexed either to

the SET pin (to close the voltage output loop) or to IA

(for external access).

nominal R

of 10kΩ allows an input voltage of 20V ,

PP

GAIN

which produces an output current of 4mA . When using

lower resistors for R

IA output current limitation must be taken into account.

PP

that can allow higher currents, the

GAIN

OUT

The principal circuit is shown in Figure 9. The two input

buffer amplifiers reproduce the input difference voltage

CURRENT MONITOR

across R

. The resulting current through this resistor is

GAIN

In current output mode (M2 = high), the XTR300 provides

high output impedance. A precision current mirror gener-

ates an exact 1/10th copy of the output current and this cur-

rent is either routed to the summing junction of the OPA to

close the feedback loop (in the current output mode) or to

bidirectionally mirrored to the output. That mirroring results

in the ideal transfer function of:

(

)

I_IA+ IA_OUT+ 2 IA_IN)* IA_IN*ńR_GAIN

(6)

the I

pin for output current monitoring in other operating

The accuracy and drift of R defines the accuracy of the

MON

GAIN

modes.

voltage to current conversion. The high accuracy and sta-

bility of the current mirrors result from a cycling chopper

technique.

18

ꢠ ꢆꢁ ꢡꢢ ꢢ

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

The high accuracy and stability of this current split results

from a cycling chopper technique. This design eliminates

the need for a precise shunt resistor or a precise shunt-

voltage measurement, which would require high common-

mode rejection performance.

therefore removes the source of power. This

connection acts like an automatic shut down, but

requires an external pull-up resistor to safely override

the internal current sources. The IA channel is not

affected, which allows continuous observation of the

voltage at the output.

During a saturation condition of the DRV output (the error

flag is active), the monitor output (I

) shows a current

MON

peak because the loop opens. Glitches from the current

mirror chopper appear during this time in the monitor sig-

nal. This part of the signal cannot be used for measure-

ment.

DIGITAL COMMUNICATION: HART

The bandwidth and drive capability of the XTR300 are

sufficient to transmit communication signals such as

HART. The combination of current monitor and voltage

sense with the IA circuit enables communication signal

transmission from the signal output connector to the

monitor pins in both current or voltage output mode. In

ERROR FLAGS

The XTR300 is designed for testability of its proper func-

tion and allows observation of the conditions at the load

connection without disrupting service.

current output mode, the signal arrives at IA

; in voltage

OUT

output mode the communication signal modulates the

DRV current and arrives at I . Both IA and I can

If the output signal is not in accordance to the transfer func-

tion, an error flag is activated (limited by the dynamic re-

sponse capabilities). These error flags are in addition to

MON

OUT

MON

be connected together because they are internally

multiplexed according to the output mode (while M1 = low).

the monitor outputs, I

and IA , which allow the mo-

OUT

MON

Driving a communication signal through the output

connector back into the system or sensor, regardless of

the output mode, enables easy configuration, calibration,

diagnosis, and universal communication.

mentary output current (in voltage mode) or output voltage

(in current mode) to be read back.

This combination of error flag and monitor signal allows

easy observation of the XTR300 for function and working

condition, providing the basis for not only remote control,

but also for remote diagnosis.

DIGITAL I/O AND GROUND

CONSIDERATIONS

All error flags of the XTR300 have open collector outputs

with a weak pull-up of approximately 1µA to an internal 5V.

External pull-up resistors to the logic voltage are required

when driving 3V or 5V logic.

The XTR300 offers voltage output mode, current output

mode, external configuration, and instrumentation mode

(voltage input). In addition, the internal feedback mode can

be disconnected and external loop connections can be

made. These modes are controlled by M1 and M2 (see the

function table). The OD input pin controls enable or disable

of the output stage (OD is active low).

The output sink current should not exceed 5mA. This is just

enough to directly drive optical-couplers, but a current-lim-

iting resistor is required.

There are three error flags:

D

IA Common-Mode Over-Range (EF )—goes low

as soon as the inputs of the IA reach the limits of the

linear operation for the input voltage.

This flag shows noise from the saturated current

mirrors which can be filtered with a capacitor to GND.

CM

The digital I/O is referenced to DGND and signals on this

pin should remain within 5V of the DGND potential. This

DGND pin carries the output low-current (sink current) of

the logic outputs. DGND can be connected to a potential

within the supply voltage but needs to be 8V below the

positive supply. Proper connection avoids current from the

digital outputs flowing into the analog ground.

D

Load Error (EF )—indicates fault conditions driving

LD

voltage or current into the load. In voltage output mode

it monitors the voltage limits of the output swing and

the current limit condition caused from short or low

load resistance. In current output mode it indicates a

saturation into the supply rails from a high load

resistance or open load.

It is important to note that DGND has normally reverse-

biased diodes connected to the supply. Therefore, high

and destructive currents could flow if DGND is driven

beyond the supply rails by more than a diode forward

voltage. Avoid this condition during power-on and

power-off!

D

Over-Temperature Flag (EF )—is a digital output

OT

that goes low if the chip temperature reaches a

temperature of +140°C and resets as soon as it cools

down to +125°C. It does not automatically shut down

the output; it allows the user system to take action on

the situation. If desired, this output can be connected

to output disable (OD) which disables the output and

19

ꢠ ꢆ ꢁ ꢡꢢ ꢢ

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

R is also part of the recommended loop compensation. C

helps protect the output against RFI and high-voltage

spikes.

OUTPUT PROTECTION

C

4

The XTR300 is intended to operate in a harsh industrial

environment. Therefore, a robust semiconductor process

was chosen for this design. However, some external

protection is still required.

C_C

47nF

V+

The instrumentation amplifier inputs can be protected by

external resistors that limit current into the protection cell

behind the IC-pins, as shown in Figure 10. This cell

conducts to the power-supply connection through a diode

as soon as the input voltage exceeds the supply voltage.

The circuit configuration example shows how to arrange

these two external resistors.

D

XTR300

1N4002

R_C

Ω

15

DRV

I/V OUT

OPA

D

C₄

100nF

1N4002

The bias current is best cancelled if both resistors are

equal. The additional capacitor reduces RF noise in the

input signal to the IA.

−

V

Figure 11. Example for DRV Output Protection

POWER ON/OFF GLITCH

R₆

Ω

2.2k

IA_IN+

When power is turned on or off, most analog amplifiers

generate some glitching of the output because of internal

circuit thresholds and capacitive charges. Characteristics

of the supply voltage, as well as its rise and fall time, also

directly influence output glitches. Load resistance and

capacitive load affect the amplitude as well.

V_SENSE+

RG₁

RG₂

C₅

10nF

IA

R_GAIN

R₇

2.2k

V_SENSE−

IA_IN+

The output disable control (OD) allows good control over

the output during power-on, power-off, and system down

time by providing a high impedance to the output.

Figure 12a, Figure 12b, and Figure 12c show the output

voltage with the output disabled during power on and

off—no glitch can be see on the output signal. Holding OD

low also prevents glitches in current output mode.

Figure 12c indicates no glitches when transitioning from

disable to enable.

Figure 10. Current Limiting Resistors

The load connection to the DRV output must be low

impedance; therefore, external protection diodes may be

necessary to handle excessive currents, as shown in

Figure 11. The internal protection diodes start to conduct

earlier than a normal external PN-type diode because they

are affected by the higher die temperature. Therefore,

either Schottky diodes are required, or an additional

All measurements are made with a load resistance of 1kΩ

and tested in the circuit configuration of Figure 5. OD has

an internal pull-up of approximately 1µA; therefore, a

100kΩ resistor provides safe pull-down during power

on—make sure the logic controlling the OD pin does not

glitch.

resistor (R ) can be placed in series with the input. An

C

example of this protection is shown in Figure 11. Assuming

the standard diodes limit the voltage to 1.4V and the

internal diodes clamp at 0.7V, this resistor can limit the

current into the internal protection diodes to 50mA:

(1.4V * 0.7V)ń15W + 47mA

(7)

20

ꢠ ꢆꢁ ꢡꢢ ꢢ

www.ti.com

SBOS336B − JUNE 2005 − REVISED MARCH 2006

Power−Supply Voltage

5.0V/div

Power−Supply Voltage

5.0V/div

Output

0.5V/div

Output

0.5V/div

Time (10ms/div)

a) Power-on in voltage or current output mode.

CH 1 shows supply voltage; CH 2 output voltage across a 1kΩ load.

b) Power-off in voltage or current output mode.

CH 1 shows supply voltage; CH 2 output voltage across a 1kΩ load.

Output

0.5V/div

OD

2.0V/div

Time (10ms/div)

c) CH 2: Output signal during toggle of OD:

CH 1 voltage or current output mode across a 1kΩ load.

Figure 12. Output Signal with Output Disabled During Power On/Off

LAYOUT CONSIDERATIONS

−

V

V+

Supply bypass capacitors should be close to the package

and connected with low-impedance conductors. Avoid

L₁

10 H

L₂

µ

10 H

µ

noise coupled into R , and observe wiring resistance.

GAIN

For thermal management, see the Heat Sinking section.

C_B1

100nF

Layout for the XTR300 is not critical; however, its internal

current chopping works best with good (low dynamic

impedance) supply decoupling. Therefore, avoid through-

hole contacts in the connection to the bypass capacitors

or use multiple through-hole contacts. Switching noise

from chopper-type power supplies should be filtered

enough to reduce influence on the circuit. Small resistors

(2Ω, for example) or damping inductors in series with the

supply connection (between the DC/DC converter and the

XTR circuit) act as a decoupling filter together with the

bypass capacitor, as shown in Figure 13.

C_B2

100nF

C_B3

µ

1 F

C_B4

µ

1 F

−

V

V+

XTR300

Figure 13. Suggested Supply Decoupling for

Noisy Chopper-Type Supplies

21

ꢠ ꢆ ꢁ ꢡꢢ ꢢ

www.ti.com

SBOS336B − JUNE 2005 − REVISED MARCH 2006

Resistors connected close to the input pins help dampen

environmental noise coupled into conductor traces.

Therefore, place the OPA input- and IA input-related

resistors close to the package. Also, avoid additional wire

The QFN package was specifically designed to provide

excellent power dissipation, but board layout greatly

influences the heat dissipation of the package. Refer to the

QFN Package section for further details.

resistance in series to R , R , and R

(observe the

SET OS

GAIN

The XTR300 has a junction-to-ambient thermal resistance

reliability of the through-hole contacts), because this could

produce gain and offset error as well as drift; 1Ω is already

0.1% of the 1kΩ resistor.

(q ) value of 38°C/W when soldered to a 2-oz copper

JA

plane. This value can be further decreased by the addition

of forced air. See Table 2 for the junction-to-ambient

thermal resistance of the QFN-20 package. Junction

temperature should be kept below +125°C for reliable

operation. The junction temperature can be calculated by:

The exposed lead-frame die pad on the bottom of the

package must be connected to V−, pin 11 (see the QFN

Package section for more details).

T = T + P • q

JA

J

A

D

where q = q + q

JA

JC

CA

QFN PACKAGE

T = Junction Temperature (°C)

J

T = Ambient Temperature (°C)

The XTR300 is available in a QFN package. This leadless,

near chip-scale package maximizes board space and

enhances thermal and electrical characteristics through

an exposed pad.

A

PD = Power Dissipated (W)

q

= Junction-to-Ambient Thermal Resistance

= Junction-to-Case Thermal Resistance

= Case-to-Air Thermal Resistance

JA

JC

CA

QFN packages are physically small, have a smaller

routing area, and improved thermal performance. For

optimal heat performance, the exposed power pad must

be connected to an adequate heat slug with at least six

thermal vias to a copper area. See the example land

pattern RGW (S-PQFP-N20), available for download at

www.ti.com or at the end of this datasheet.

HEATSINKING METHOD

q

JA

The part is soldered to a 2-oz copper pad under the

exposed pad.

38

Soldered to copper pad with forced airflow (150lfm).

Soldered to copper pad with forced airflow (250lfm).

Soldered to copper pad with forced airflow (500lfm).

36

35

34

The QFN package can be easily mounted using standard

printed circuit board (PCB) assembly techniques. See

Application Note, QFN/SON PCB Attachment (SLUA271)

and Application Report, Quad Flatpack No−Lead Logic

Packages (SCBA017), available for download at

www.ti.com, for more information.

Table 2. Junction-to-Ambient Thermal Resistance

with Various Heatsinking Efforts

To appropriately determine the required heatsink area,

required power dissipation should be calculated and the

relationship between power dissipation and thermal

resistance should be considered to minimize overheat

conditions and allow for reliable long-term operation.

The exposed leadframe die pad on the bottom of the

package must be connected to the V− pin, and proper heat

sinking has to be provided.

The efficiency of the heat sinking can be tested using the

HEAT SINKING

EF

output signal. This output goes low at nominally

OT

+140°C junction temperature (assume 6% tolerance).

With full-power dissipation—for example, maximum

current into a 0Ω load—the ambient temperature can be

slowly raised until the OT flag goes low; at this point, the

usable operation condition is determined.

Power dissipation depends on power supply, signal, and

load conditions. It is dominated by the power dissipation of

the output transistors of the OPA. For DC signals, power

dissipation is equal to the product of output current, I

OUT

and the output voltage across the conducting output

transistor (V − V ).

The recommended landing pattern is shown in document

RGW (S-PQFP-N20). The nine (not less than six) through-

hole contacts of the inner heat sink solder pad connect to

a copper plane in any one layer. It must be large enough

to efficiently distribute the heat into the PCB. This pad has

to be electrically connected to the V− pin to provide the

required substrate connection.

S

OUT

It is important to note that the temperature protection will

not shut the part down in over-temperature conditions,

unless the EF pin is connected to the output enable pin

OT

OD; see the section on Driver Output Disable.

The power that can be safely dissipated by the package is

related to the ambient temperature and the heatsink

design.

22

PACKAGE OPTION ADDENDUM

www.ti.com

14-Mar-2006

PACKAGING INFORMATION

Orderable Device

XTR300AIRGWR

XTR300AIRGWRG4

XTR300AIRGWT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGW

20

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RGW

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

XTR300AIRGWTG4

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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