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XTNETE2101PZ

型号：

XTNETE2101PZ

描述：

10BASE -T / 100BASE - TX / 100BASE -FX低功耗物理层接口[ 10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

39 页

PDF大小：

497 K

下载PDF手册
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Integrated, Single-Chip, Ethernet  
Physical-Layer (PHY) Interface for  
Full-Duplex or Half-Duplex Connection to  
10BASE-T, 100BASE-TX, and 100BASE-FX  
Networks  
10BASE-T  
– Fully Compliant With IEEE Std 802.3  
– Smart Squelch for Improved Noise  
Immunity  
– Integrated Transmit Wave Shaping  
– Autopolarity (Reverse-Polarity  
Correction)  
Low-Power 3.3-V CMOS Design With  
Power-Down Capability for CardBus and  
Other Applications Requiring Low Power  
– Transmit Jabber Detection  
100BASE-TX  
Integrated Transmit Filtering and Receive  
Equalization Provide for Minimal External  
Component Count to Reduce System Cost  
– Fully Compliant With ANSI Twisted-Pair  
Physical-Media-Dependent (TP-PMD)  
Standard and IEEE Std 802.3  
– Synthesized Rise-Time Control  
– Integrated Receiver With Adaptive Line  
Equalization (EQ) and Baseline Wander  
(BLW) Correction (DC Restoration)  
10BASE-T/100BASE-TX Connection  
Supported With Magnetics Package and  
RJ-45 Connector  
Electrostatic Discharge (ESD) Human Body  
Model (HBM) Protection 1.5 kV Per JEDEC  
JESD 22-A114-A  
IEEE Std 802.3-Compliant  
Media-Independent Interface (MII) That  
Includes Management Interface  
Digital Signal Processor (DSP)-Based  
Digital Phase-Locked Loop (PLL)  
Technology Allows Data Recovery at  
10 Mbit/s and 100 Mbit/s, Requiring One  
20-MHz Clock Reference Source  
IEEE Std 802.3-Compliant Autonegotiation  
(N-Way) With Next-Page Support  
IEEE Std 1149.1 (JTAG) Test Access Port  
(TAP)  
Packaged in 100-Terminal Plastic Quad  
Flatpack  
100BASE-TX  
Physical Coding Sublayer  
(PCS) and  
Physical Medium Attachment  
(PMA)  
MII Data  
and  
Control  
Interface  
10/100 PMD  
– BLW Correct  
– Adaptive EQ  
– MLT-3  
Magnetics  
RJ-45  
10BASE-T  
10/100 MAC  
MII  
PCS and PMA  
MII  
PLL Clock  
Generation  
and Recovery  
Autonegotiation  
With Next-Page  
Support  
Management  
Registers  
JTAG  
Figure 1. 10BASE-T/100BASE-TX PHY  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI is a trademark of Texas Instruments Incorporated.  
Ethernet is a registered trademark of Xerox Corporation.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
description  
The TNETE2101 physical-layer (PHY) device from Texas Instruments (TI ) is a single-chip, high-performance  
solution for a range of 10BASE-T, 100BASE-TX, and 100BASE-FX networking systems (see Figure 1). The  
highly integrated TNETE2101 includes an on-board media-independent interface (MII) for simple connection  
to IEEE Std 802.3-compliant media-access controls (MACs). The device integrates all filtering and rise-time  
control functions for a cost-effective and space-saving PHY solution. Built-in autonegotiation allows automatic  
selection of half-/full-duplex 10BASE-T or 100BASE-TX, with an autopolarity-correction feature for immunity  
to receive-pair reversal.  
PZ PACKAGE  
(TOP VIEW)  
ACPLL  
ACBLW  
ACAGC  
V
SS  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
JTDI  
V
2
3
V
4
DDA  
DD5  
V
DDA  
JTDO  
5
AIREF  
V
SS  
6
V
JTCLK  
7
SSA  
ATXREF  
JTMS  
JTRST  
MTCLK  
8
V
9
SSA  
V
SSA  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
XTAL1  
V
NC  
DD  
XTAL2  
V
MTXD0  
MTXD1  
MTXD2  
MTXD3  
DDA  
V
DDA  
NC  
V
SSA  
NC  
CDEVSEL0  
CDEVSEL1  
CDEVSEL2  
CREPEATER  
CFIBER  
V
SS  
MTXEN  
MTXER  
MCOL (CDEVSEL4)  
MCRS  
MRCLK  
V
DD  
V
DD  
LACTIVITY  
MRXD0  
LDUPCOL  
V
DD5  
NC – No connection (no external connection allowed)  
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Terminal Functions  
analog function  
TERMINAL  
†
DESCRIPTION  
TYPE  
I/O  
NAME  
ACAGC  
ACBLW  
ACPLL  
NO.  
3
A
A
A
I
I
I
Automatic gain control (AGC) capacitor for the AGC loop  
Baseline wander (BLW) capacitor for the BLW correction loop  
PLL capacitor required for an internal PLL  
2
1
Analog current reference. An external resistor between AIREF and analog ground sets the bias  
current for internal analog circuits.  
AIREF  
6
8
A
A
I
I
100BASE-TX transmit reference. An external resistor between ATXREF and analog ground sets the  
100BASE-TX transmit amplitude.  
ATXREF  
†
A = analog  
configuration  
TERMINAL  
NAME  
DESCRIPTION  
TYPE  
I/O  
NO.  
Autonegotiationenable. CAUTONEG enables (active high) or disables autonegotiation within the  
PHY. When CAUTONEG is low, the current values of CSPEED and CDUPLEX determine the  
speed and duplex of the PHY. On the rising edge of CAUTONEG, the values of CSPEED and  
CDUPLEXsettheadvertisedcapabilitiesofthePHYforautonegotiate. Thisalsooccursonpower  
up or on the rising edge of MRST if CAUTONEG is high. When CAUTONEG is high, the  
autonegotiation process also can be controlled with the PHY register bit AUTOENB (register 0,  
bit 12). See 10BASE-T/100BASE-TX PHY operation for details.  
CAUTONEG  
33  
TTL  
I
CDEVSEL2  
CDEVSEL1  
CDEVSEL0  
20  
19  
18  
MII device-select address. The values of CDEVSEL2–CDEVSEL0, SLINK (CDEVSEL3), and  
MCOL (CDEVSEL4) are latched into the MII on the rising edge of MRST. This allows a unique  
address to be assigned to the PHY in applications in which multiple PHYs are in use.  
TTL  
TTL  
I
Duplex configuration. When CAUTONEG is low, CDUPLEX sets the PHY duplex to either  
half-duplex(low)orfull-duplex(high).WhenCAUTONEGishighandautonegotiationiscomplete,  
CDUPLEX is driven low if half-duplex mode was selected, or set to the high-impedance state if  
full-duplex mode was selected. The PHY duplex also can be controlled and read at PHY register  
0, bit 8, DUPLEX.  
CDUPLEX  
CFIBER  
36  
22  
I/O  
100BASE-FX fiber-mode enable. In 100BASE-FX fiber mode, the fiber interface is enabled, and  
unshielded twisted pair (UTP) interface and autonegotiation are disabled. Selecting 10BASE-T  
mode with this mode enabled causes the PHY to power down. This function can be controlled by  
PHY register 0x11 bit 10, FIBER, if CFIBER is high.  
TTL  
TTL  
I
I
MII-isolate enable. CISOLATE causes the PHY to raise all its MII outputs to a high-impedance  
state and ignore the MII inputs. In normal mode (CREPEATER is high), the PHY raises MTCLK,  
MRCLK, MRXD0–MRXD3, MRXDV, MRXER, MCRS, and MCOL to a high-impedance state and  
does not respond to MTXEN. In repeater mode, only MRCLK, MRXD0–MRXD3, MRXDV, and  
MRXER are raised to high impedance and, consequently, CISOLATE performs an active-high  
receive-enable function. This function can be controlled by PHY register 0, bit 10, ISOLATE, if  
CISOLATE is low.  
38  
CISOLATE  
Loopback enable. When CLOOPBK is low, transmit is looped back to receive. This function can  
be controlled by PHY register 0, bit 14, LOOPBK, if CLOOPBK is high.  
30  
37  
TTL  
TTL  
CLOOPBK  
CPASS5B  
I
I
Pass-through mode enable. CPASS5B when set low, configures the PHY to bypass the internal  
5B4B encoder and decoder. The 5B-encoded data is transmitted on MTXD0–MTXD3 and  
MTXER with the most significant data bit on MTXER. The 5B-encoded data is received on  
MRXD0–MRXD3 and MRXER, with the most significant bit on MRXER. This function can be  
controlled by PHY register 0x11, bit 8, NOENDEC, if CPASS5B is high.  
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Terminal Functions (Continued)  
configuration (continued)  
TERMINAL  
TYPE  
DESCRIPTION  
I/O  
NAME  
NO.  
Power-down enable. When CPWRDOWN is low, the PHY is placed in a low power-consumption  
state. This function can be controlled by PHY register 0, bit 11, PDOWN, if CPWRDOWN is high.  
32  
TTL  
TTL  
CPWRDOWN  
I
Repeater-mode enable. When CREPEATER is low, the repeater mode is enabled and the PHY  
does not assert MCRS in response to transmit activity. This function can be controlled by PHY  
register 0x11, bit 5, REPEATER, if CREPEATER is high.  
21  
34  
CREPEATER  
CSPEED  
I
Speed configuration. When CAUTONEG is low, CSPEED sets the PHY speed to either  
10BASE-T (low) or 100BASE-TX (high). When CAUTONEG is high and autonegotiation is  
complete,CSPEEDisdrivenlowif10BASE-Tmodewasselected, orsetathigh-impedancestate  
if 100BASE-TX mode was selected. The PHY speed also can be controlled and read at PHY  
register 0, bit 13, SPEED.  
TTL  
I/O  
fiber interface  
TERMINAL  
†
DESCRIPTION  
TYPE  
I/O  
NAME  
NO.  
FRCVN  
FRCVP  
79  
80  
100BASE-FXserial data input pair. Differential3.3-Vpseudo-emitter-coupledlogic(PECL)125-Mbit/s  
receive-data input for fiber mode.  
PECL  
PECL  
PECL  
I
I
FSDN  
FSDP  
82  
83  
100BASE-FX serial data detect pair. Differential 3.3-V PECL 125-Mbit/s signal-detect input.  
FXMTN  
FXMTP  
76  
77  
100BASE-FX serial data output pair. Differential 3.3-V PECL 125-Mbit/s serialized transmit-data  
output for fiber mode.  
O
†
PECL = pseudo-emitter-coupled-logic  
IEEE Std 1149.1 JTAG interface  
TERMINAL  
‡
DESCRIPTION  
TYPE  
I/O  
NAME  
NO.  
Test clock. JTCLK is used to clock state information and test data into and out of the device during  
operation of the test port.  
JTCLK  
69  
5-V TTL  
5-V TTL  
5-V TTL  
I
I
Test data input. JTDI is used to serially shift test data and test instructions into the device during  
operation of the test port.  
JTDI  
73  
71  
Test data output. JTDO is used to serially shift test data and test instructions out of the device during  
operation of the test port.  
JTDO  
O
JTMS  
68  
67  
5-V TTL  
5-V TTL  
I
I
Test-mode select. JTMS is used to control the state of the test-port controller within the PHY.  
TAP reset. JTRST is used to reset the TAP controller (optional).  
JTRST  
‡
5-V TTL terminals are 5-V tolerant if V  
DD5  
is connected to 5 V.  
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Terminal Functions (Continued)  
LED status  
TERMINAL  
DESCRIPTION  
TYPE  
I/O  
NAME  
NO.  
Activity indicator. LACTIVITY lights an attached LED in response to receive and transmit activity  
within the PHY.  
24  
LED  
LACTIVITY  
O
Duplex/collisionindicator. LDUPCOL lights an attached LED in response to a network collision when  
the PHY is in half-duplex mode of operation. The LED is illuminated continuously when the PHY is  
in full-duplex mode.  
25  
LED  
LDUPCOL  
LLINK  
O
Link status indicator. LLINK lights an attached LED when the PHY has established a valid link with  
its partner. If autonegotiation is enabled, the driver flashes the LED during negotiation to indicate that  
it is attempting to establish a link. This is useful because a negotiation takes a minimum of 3 seconds  
(considerablylongerifnext-pageinformationalsoisbeingexchanged), andtheusermaybetempted  
to remove the cable if the link light does not illuminate immediately. The user also is alerted to a  
network misconfiguration (where no common ability exists between the two link partners) by a  
continuously flashing LED.  
27  
28  
LED  
LED  
O
O
Link speed indicator. LSPEED lights an attached LED when the PHY has established a valid  
100BASE-TX link with its partner.  
LSPEED  
MII interface  
TERMINAL  
NAME  
†
DESCRIPTION  
TYPE  
I/O  
NO.  
Collision detect. MCOL indicates that the PHY is receiving data while simultaneously  
transmitting. MCOL does not assert in full-duplex mode. The value of MCOL is latched on the  
rising edge of MRST for use as CDEVSEL4, bit 4, of the MII device-select address.  
MCOL  
(CDEVSEL4)  
56  
5-V TTL  
I/O  
Management data clock. MDCLK clocks serial management interface to the  
physical-media-dependent (PMD) chip.  
MDCLK  
43  
42  
54  
5-V TTL  
5-V TTL  
5-V TTL  
I
Management data I/O. MDIO is serial management interface to the PMD chip. MDIO is  
synchronous to MDCLK.  
MDIO  
I/O  
O
Receive clock. Receive clock source from the PHY. MRCLK is 2.5 MHz in 10BASE-T mode and  
25 MHz in 100BASE-TX mode.  
MRCLK  
MCRS  
MRST  
55  
41  
5-V TTL  
5-V TTL  
O
I
Carrier sense. MCRS asserts when the PHY initiates a frame reception.  
MII reset. MRST is the reset signal to the PMD front end (active low).  
MRXD3  
MRXD2  
MRXD1  
MRXD0  
47  
48  
50  
52  
Receive data. MRXD3–MRXD0 are nibble receive data bits 3–0 from the PHY. Data is  
synchronous to MRCLK.  
5-V TTL  
O
Receive data valid. MRXDV indicates that data on MRXD0–MRXD3 is valid. MRXDV is  
synchronous to MRCLK.  
MRXDV  
MRXER  
MTCLK  
46  
45  
66  
5-V TTL  
5-V TTL  
5-V TTL  
O
O
O
Receive error. MRXER indicates reception of a coding error on received data. MRXER is  
synchronous to MRCLK.  
Transmit clock. MTCLK is the transmit clock source from the PHY. This clock is 2.5 MHz in  
10BASE-T mode and 25 MHz in 100BASE-TX mode.  
MTXD3  
MTXD2  
MTXD1  
MTXD0  
60  
61  
62  
63  
Transmit data. MTXD3–MTXD0 are nibble transmit data bits 3–0 from the MAC. Data is  
synchronous to MTCLK.  
5-V TTL  
I
†
5-V TTL terminals are 5-V tolerant if V  
is connected to 5 V.  
DD5  
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Terminal Functions (Continued)  
MII interface (continued)  
TERMINAL  
†
TYPE  
I/O  
DESCRIPTION  
NAME  
MTXEN  
MTXER  
NO.  
Transmit enable. MTXEN indicates valid transmit data on MTXD0–MTXD3. MTXEN is  
58  
5-V TTL  
5-V TTL  
I
synchronous to MTCLK.  
Transmit error. MTXER allows coding errors to be propagated across the MII. MTXER is  
synchronous to MTCLK.  
57  
I
†
5-V TTL terminals are 5-V tolerant if V  
is connected to 5 V.  
DD5  
miscellaneous  
TERMINAL  
‡
DESCRIPTION  
TYPE  
I/O  
NAME  
NO.  
Link status. When asserted high, SLINK indicates that a good link has been established with  
the link partner. When autonegotiation is enabled, SLINK also indicates that the CSPEED and  
CDUPLEX terminals are being driven with the negotiated speed and duplex configuration. The  
value of SLINK is latched on the rising edge of MRST for use as CDEVSEL3, bit 3, of the MII  
device-select address.  
SLINK  
39  
TTL  
I/O  
(CDEVSEL3)  
XTAL1  
Clock input. XTAL1 is the main 20-MHz reference clock input for the TNETE2101. A 20-MHz  
clock oscillator can be connected to XTAL1, or a crystal with a capacitor network can be  
connected across XTAL1 and XTAL2.  
11  
12  
A
A
I
XTAL2  
O
Output for external crystal circuit. See XTAL1.  
‡
A = analog  
network interface  
TERMINAL  
‡
DESCRIPTION  
TYPE  
I/O  
O
I
NAME  
ACT  
NO.  
85  
A
A
Center tap. ACT is the connection to the primary center tap of the transmit transformer.  
ARCVP  
ARCVN  
91  
92  
Receive pair. ARCVP and ARCVN are the differential line inputs to the device from the transformer  
and termination components.  
AXMTP  
AXMTN  
87  
88  
Transmit pair. AXMTN and AXMTP are the differential line outputs from the device to the transformer  
and termination components.  
A
O
‡
A = analog  
no connection  
TERMINAL  
NO.  
15, 17, 64, 74, 94, 95, 97, 98  
DESCRIPTION  
NAME  
NC  
No connection (no external connection allowed).  
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Terminal Functions (Continued)  
power  
TERMINAL  
NAME  
POWER  
DOMAIN  
DESCRIPTION  
Power. Analog 3.3-V supply connection.  
†
NO.  
V
5, 13, 14, 96  
84  
V
DDA  
XMT_V  
DDA  
XMT_AV  
Power. Analog 3.3-V supply connection for transmit.  
Power. Analog 3.3-V supply connection for receive.  
DDA  
DD  
DDA  
or  
V
4, 93  
V
DDA  
DD5  
V
DD  
Power. Power for digital I/O that connects to 3.3 V for 3.3-V I/O operations and to 5 V for 5-V  
I/O operations. Used for I/O on MII and JTAG interface.  
V
31, 51, 72  
V
DD5  
23, 35, 44, 53,  
65, 78  
V
V
V
V
Power. Digital 3.3-V supply connection for core logic and I/O.  
Ground. Analog ground connection.  
DD  
DDD  
7, 9, 10, 16,  
86, 89, 90, 99,  
100  
GND  
GND  
SSA  
26, 29, 40, 49,  
59, 70, 75, 81  
Ground. Digital ground connection.  
SS  
†
Denotes suggested power-plane connection for layout  
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
functional block diagram for UTP interface  
BLW  
Correction  
100BASE-TX  
Digital  
Clock  
Recovery  
MRXD0  
MRXD1  
MRXD2  
MRXD3  
MCRS  
MRXDV  
MRXER  
MRCLK  
Adaptive  
Equalization  
5B4B  
Decode  
Descrambler  
Align  
Align  
Digital  
Clock  
Recovery  
RCVP  
RCVN  
Smart  
Squelch  
Manchester  
Decode  
10BASE-T  
Collision  
Detect  
MCOL  
100BASE-TX  
MTXD0  
MTXD1  
MTXD2  
MTXD3  
MTXEN  
MTXER  
MTCLK  
Rise-Time  
Control  
5B4B  
Encode  
Serialize  
Serialize  
Scramble  
Line  
Driver  
XMTP  
XMTN  
Manchester  
Encode  
Wave Shape  
10BASE-T  
Autonegotiation and  
Link Status Monitor  
LED  
Controller  
JTAG  
LED Terminals  
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
functional description  
10BASE-T/100BASE-TX differential line transmitter function  
The TNETE2101 differential line drivers are designed to drive at least 100 m of CAT5 cable in 100BASE-TX  
mode and in excess of 100 m of CAT3 (or CAT5) cable in 10BASE-T mode. Three transmitter-output terminals  
(including a center-tap connection) interface to a single transformer for both operating modes. This simplifies  
the external connection to a single RJ-45 socket connected directly to the transformer secondary winding (see  
Figure 2).  
The TNETE2101 incorporates on-chip wave shaping for 10BASE-T transmission and rise-time control for  
100BASE-TX transmission, which enables the device to interface directly to the magnetics without using  
external components, other than two termination resistors. The functional block diagram illustrates the  
TNETE2101 transmitter function for a single 10BASE-T/100BASE-TX PHY channel.  
10BASE-T/100BASE-TX differential line receiver function  
The two receiver-input terminals of the TNETE2101 must be connected to the physical-media interface (PMI)  
through an external isolation transformer. The receiver circuitry establishes its own common-mode input bias  
voltage, therefore, no external resistor divider-biasing network is required. A simple termination network  
consisting of two resistors and one capacitor is recommended (see Figure 2). Data received from the network  
is output on the MRXD data nibble of the MII and synchronized to the rising edge of the corresponding MRCLK  
signal. The MRCLK frequency automatically adjusts to 2.5 MHz in 10BASE-T mode or 25 MHz in 100BASE-TX  
mode.  
A single receiver-input pair supports both speed modes, with all multiplexing functions performed internally to  
the device.  
The 10BASE-T receiver smart-squelch function allows incoming data to pass only if the input amplitude is  
greater than a minimum signal threshold and a specific pulse sequence is received. This prevents input data  
being affected by impulse line noise that is mistaken for signal or link activity. The squelch circuits quickly  
deactivate if received pulses exceed the specifications; therefore, long pulses are not mistaken as link pulses.  
The 100BASE-TX receiver decodes the MLT-3 waveform and provides a data nibble on MRXD0–MRXD3. After  
MLT-3 signal is received, the signal is immediately amplified and equalized. This allows reception over a  
minimum of 100 m of CAT5 cable. The low-frequency component of the MLT-3 signal, often referred to as BLW,  
is removed. BLW can be a consequence of long periods without data transitions in transformer-coupled circuits.  
The ideal MLT-3 then is internally converted to non-return-to-zero information (NRZI), then resynchronized to  
its own recovered clock using a digital phase-locked-loop (PLL) technique. The reclocked data then is  
deserialized into 5-bit code groups, descrambled, and 5B4B decoded. When a start-of-stream delimiter is  
detected in the 5B data stream, the next frame is output on the MII. The functional block diagram illustrates the  
TNETE2101 receiver function for a single 10BASE-T/100BASE-TX PHY channel.  
9
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
XMT_V  
DDA  
50 Ω  
50 Ω  
Valor ST6118  
or Equivalent  
MTCLK  
MTXD0–MTXD3  
MTXEN  
AXMTP  
ACT  
AXMTN  
+1  
+2  
+3  
+4  
+5  
+6  
+7  
+8  
MTXER  
MRCLK  
MRXD0–MRXD3  
MRXDV  
Ethernet  
Controller  
ARCVP  
MRXER  
50 Ω  
MCOL  
MCRS  
MDIO  
MDCLK  
MRST  
SLINK  
0.1 µF  
1:1  
Transformer  
RJ-45C  
50 Ω  
ARCVN  
AIREF  
7.5 K Ω  
2.5 K Ω  
TNETE2101  
ATXREF  
V
DD  
LACTIVITY  
LDUPCOL  
LSPEED  
LLINK  
20-MHz  
3.3-V  
XTAL1  
Oscillator  
ACAGC ACPLL  
ACBLW  
0.001 µF  
270 pF  
6.8 K Ω  
470 pF  
4700 pF  
Figure 2. External Components for the TNETE2101  
10  
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link-integrity test and reverse-polarity and correction  
When autonegotiation is disabled and the TNETE2101 is configured for 10BASE-T only, the transmitter sends  
a normal link pulse through the data-out (DO) circuit every 16 ms.  
The receiver looks for valid link pulses on the input pair. If a link pulse is not received within a given time interval,  
the device enters a link-fail state. In this state, link pulses continue to be generated, and the receiver  
continuously looks for the link pulse pattern. The device remains in this state until a valid receive packet or  
multiple legal-link test pulses are received.  
Link pulses of the opposite polarity (received and qualified in the same manner as normal link pulses) are an  
indication that the receive-pair connections are reversed and that an automatic internal reconfiguration has  
occurred to correct this problem. Reverse-polarity correction is not required in 100BASE-TX mode, where the  
data is MLT-3-encoded.  
autonegotiation  
The TNETE2101 fully supports IEEE Std 802.3 autonegotiation, including next-page transfer. When enabled,  
this feature allows the TNETE2101 to negotiate with any other autonegotiation-capable PHYs on its link  
segment to establish their highest common protocol. Until a PHY has completed its negotiation, it cannot assert  
LINK.  
More information on the link partner abilities can be obtained by reading the TNETE2101 registers.  
loopback test mode  
By asserting the CLOOPBK terminal on the device or by setting the LOOPBK bit in the GEN_ctl register, the  
transmit circuit of the PHY is looped back to the corresponding receive circuit located closest to the twisted-pair  
I/O terminals.  
In 10BASE-T mode and loopback mode, all receive activities (other than link test pulses) are ignored. However,  
squelch information is still processed, allowing the link status to be maintained under momentary loopback  
self-test.  
LED status indication  
The TNETE2101 has four terminals that drive LEDs, indicating activity, duplex/collision, link, and speed. The  
circuitry contains an open-drain N-channel MOS (NMOS) device for the LED driver, and the LEDs should be  
connected to digital 3.3 V through a current-limiting resistor. The value of the resistor depends on the LED type.  
In 10BASE-T mode, the link LED illuminates when the PHY has established a valid link. In 100BASE-TX mode,  
the link LED indicates that the descrambler has locked onto the data and the TNETE2101 is in a state to transmit  
and receive data. The link LED flashes during the autonegotiation process to indicate link activity to the user,  
since autonegotiation can take several seconds. During loopback test, the LED is not illuminated.  
The activity LED illuminates when the PHY is transmitting or receiving data; it remains illuminated for a minimum  
of 20 ms for each activity. Its operation is the same in both speed modes. The activity LED illuminates on any  
attempt to transmit data, including those made in loopback mode and in link-fail state.  
The duplex/collision LED illuminates continuously when the PHY is in full-duplex mode and for a minimum of  
20 ms when collisions occur in half-duplex mode. If continuous or frequent collisions occur, it flashes at 10 Hz.  
test access port (TAP)  
To be compliant with IEEE Std 1149.1 and for boundary-scan testing, the TAP includes five terminals that are  
used to interface serially with the device and the board on which it is installed.  
11  
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100BASE-FX differential PECL interface  
The PHY provides three pairs of differential PECL terminals for connection to external fiber-optic transceivers.  
The data streams are 125-Mbit/s NRZI encoded, with the receive data stream routed to the digital PLL for data  
recovery. To maintain a reliable lock on the digital PLL, the receive data stream must be jitter free.  
The FSDP/FSDN serial data-detect pair must be differentially positive to enable data recovery. While this pair  
is differentially negative, MRCLK is inactive, and no attempt is made to process any receive data appearing on  
FRCVP/FRCVN.  
Differential PECL signals should be terminated with a standard emitter-coupled logic (ECL) load of 50 Ω to a  
voltage source of V  
– 2 V (that is, 1.3 V) or to an equivalent circuit.  
DD  
reset and power up timing  
Atinitialpowerup, thePHYperformsaninternalreset. Noexternalresetcircuitryisrequired;however, operation  
of the TNETE2101 is not specified for 50 ms after power up (V  
stable).  
DD  
During operation, a full reset of the device can be performed by taking MRST low for not less than 50 s. Correct  
operation of the device is not certain until 50 ms after MRST is deasserted high.  
10BASE-T/100BASE-TX PHY operation  
PHY link establishment  
The PHY implements the full autonegotiation standard, including next-page capability. CAUTONEG, CSPEED,  
and CDUPLEX are used to directly configure the link speed or to set and report autonegotiated speeds.  
When CAUTONEG is deasserted low, CSPEED and CDUPLEX determine the link configuration. CSPEED and  
CDUPLEX have weak pullups, giving a default configuration of full-duplex 100BASE-TX when not connected.  
The rising edge of CAUTONEG latches the values of CSPEED and CDUPLEX into the autonegotiation  
advertisement (AN_adv) register as shown in Table 1. This advertises to the link partner during negotiation of  
the capabilities of PHY and the highest common link is determined. CSPEED and CDUPLEX then are driven  
with the negotiated speed and duplex.  
Table 1. External-Link Configuration Speeds  
CSPEED CDUPLEX AN_adv  
ADVERTISED TECHNOLOGIES  
0
0
0
1
0x0021 Half-duplex 10BASE-T  
0x0061 Half-/full-duplex 10BASE-T  
Half-duplex 10BASE-T  
0x00A1  
1
1
0
1
Half-duplex 100BASE-TX  
Half-/full-duplex 10BASE-T  
0x00E1  
Half-/full-duplex 100BASE-TX  
For external controlling and reading of CAUTONEG, CSPEED, and CDUPLEX, timing to be considered is  
shown in Figure 3. CSPEED and CDUPLEX must not be driven externally for 1200 ms (maximum) after  
CAUTONEG is asserted high. The PHY begins negotiation when CAUTONEG is asserted. In the final 750 ms  
(minimum) of autonegotiation, the PHY drives CSPEED and CDUPLEX to indicate the link configuration. The  
values of these two terminals can be latched on the rising edge of SLINK.  
12  
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PHY link establishment (continued)  
CAUTONEG  
CSPEED  
CDUPLEX  
SLINK  
1200 ms MAX  
750 ms MIN  
Figure 3. External Autonegotiation Configuration and Status  
Autonegotiation, duplex, and speed also can be controlled through the PHY register 0, GEN_ctl. These bits,  
AUTOENB (bit 12), SPEED (bit 13), and DUPLEX (bit 8), are similar to and work with CAUTONEG, CSPEED,  
and CDUPLEX, respectively. These bits can be written and read.  
When CAUTONEG is low, the AUTOENB bit remains set to a 0 and cannot be set to a 1; therefore,  
autonegotiation cannot be enabled. In this case, the values read from SPEED and DUPLEX reflect the values  
driven on the terminals CSPEED and CDUPLEX, respectively.  
When CAUTONEG is high, AUTOENB can be set to a 1 (enabled) or a 0 (disabled). When AUTOENB is  
enabled, autonegotiation is started and the SPEED and DUPLEX bits are updated to reflect the negotiated  
values. When AUTOENB is disabled, autonegotiation is disabled and speed and duplex are forced to the values  
written in the SPEED and DUPLEX bits.  
PHY configuration  
The TNETE2101 can be configured externally through the terminals or internally through the PHY registers  
much like the autonegotiation terminals and register bits. Each external terminal has an equivalent PHY register  
bit. Table 2 correlates the terminal with the register bit.  
Table 2. External Configuration Terminal/Register Bit Correlation  
TERMINAL  
CISOLATE  
CPWRDOWN  
CLOOPBK  
CREPEATER  
CPASS5B  
PIN NO.  
38  
BIT  
REGISTER  
0x0  
BIT NO.  
FUNCTION  
Sets MII interface to high-impedance state  
Places PHY in power-down state  
Enables loopback  
ISOLATE  
PDOWN  
LOOPBK  
REPEATER  
NOENDEC  
FIBER  
10  
11  
14  
5
32  
0x0  
30  
0x0  
21  
0x11  
Enables repeater mode  
37  
0x11  
8
Disables 5B4B encoder/decoder  
Enables fiber interface  
CFIBER  
22  
0x11  
10  
Alloftheterminalsareactivelowandtheregisterbitsareactivewhensettoa1. Alltheregisterbitscanbewritten  
and read. The value read from the register bit reflects the internal configuration setting of the PHY and is derived  
from the external terminal setting and the internal register bit value.  
13  
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PHY configuration (continued)  
Table 3 shows the external configuration terminal, register value, and the result, except for the isolate function.  
Table 3. Terminal and Register Values  
TERMINAL  
VALUE  
REGISTER  
VALUE  
REGISTER  
VALUE  
RESULT  
(LOW = ACTIVE)  
WRITTEN  
READ  
Low  
High  
High  
X
0
1
1
0
1
Enabled  
Disabled  
Enabled  
Table 4 shows the operation for the isolate function and the resulting control of the isolate function.  
Table 4. Isolate-Function Operation  
TERMINAL  
VALUE  
REGISTER  
VALUE  
REGISTER  
VALUE  
RESULT  
(LOW = ACTIVE)  
WRITTEN  
READ  
Low  
Low  
High  
0
1
0
1
0
Disabled  
Enabled  
Disabled  
X
The terminal can be set to a value that disables control of the function through the internal PHY registers.  
14  
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10BASE-T/100BASE-TX/100BASE-FX  
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10BASE-T/100BASE-TX PHY registers  
The IEEE Std 802.3 MII serial protocol allows for up to 32 different PMD devices, with up to 32 (16-bit-wide)  
internal registers in each device. The 10BASE-T/100BASE-TX PHY implements 11 internal registers, three of  
which are hardwired. Figure 4 shows the device register map. Most of the registers are the generic registers  
mandated by the MII specification. The three registers (TXPHY_X) in Figure 4 are TI-specific registers. All other  
registers are read as 0s.  
REGISTER  
GEN_ctl  
ADDRESS  
0x00h  
0x01h  
0x02h  
0x03h  
0x04h  
0x05h  
0x06h  
0x07h  
DESCRIPTION  
Generic control (see Figure 7 and Table 6)  
GEN_sts  
GEN_id_hi  
GEN_id_lo  
AN_adv  
Generic status (see Figure 8 and Table 7)  
Generic identifier (high) hardwired (see Figure 9)  
Generic identifier (low) hardwired (see Figure 10)  
Autonegotiation advertisement (see Figure 11 and Table 8)  
Autonegotiation link partner ability (see Figure 12 and Table 9)  
Autonegotiation expansion (see Figure 15 and Table 13)  
Autonegotiation next-page transmit (see Figure 16 and Table 14)  
AN_lpa  
AN_exp  
AN_np  
Reserved  
Reserved  
Reserved  
TXPHY_id  
TXPHY_ctl  
TXPHY_sts  
0x08h  
•
•
•
Reserved by IEEE Std 802.3  
0x0Fh  
†
0x10h  
0x11h  
0x12h  
PHY identifier  
PHY control (see Figure 17 and Table 15)  
PHY status (see Figure 18 and Table 16)  
†
TI-specific register  
Figure 4. Register Map  
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MII frame format  
The default or IDLE state of the MII is a logic 1. All 3-state drivers are disabled and the PHY pullup resistor pulls  
the management data input/output (MDIO) line to a logic 1. Before initiating any other transaction, the station  
management entity sends a preamble sequence of contiguous logic-1 bits on MDIO with 32 corresponding  
cycles on MDCLK. This sequence provides the PHY a pattern to use to establish synchronization. A PHY  
observes the sequence of 32 contiguous 1 bits on MDIO with 32 corresponding cycles on MDCLK before  
responding to any other transactions. See Figures 5 and 6 for MII frame formats.  
Start Delimiter  
Operation Code  
PHY Address  
Register Address  
Turnaround  
Data  
01  
10  
AAAAA  
RRRRR  
10  
DDDD.DDDD.DDDD.DDDD  
Figure 5. MII Read Frame Format  
Start Delimiter  
Operation Code  
PHY Address  
Register Address  
Turnaround  
Data  
01  
01  
AAAAA  
RRRRR  
10  
DDDD.DDDD.DDDD.DDDD  
Figure 6. MII Write Frame Format  
start delimiter  
The start of a frame is indicated by a 01 pattern. This pattern specifies transitions from the default logic-1 line  
state to 0 and then back to 1.  
operation code  
The operation code for a read is 10, and the code for a write is 01.  
PHY address  
The PHY address is five bits, providing 32 unique PHY addresses. The first PHY address bit transmitted and  
received is the most significant bit of the address. The TNETE2101 address is set using  
CDEVSEL0–CDEVSEL2, CDEVSEL 3 (SLINK), and CDEVSEL4 (MCOL).  
register address  
The register address is 5 bits, providing 32 individual registers to be addressed within each PHY. See Figure 4  
for the addresses of individual registers.  
turnaround  
An idle-bit time, during which no device actively drives the MDIO signal, is inserted between the register address  
field and the data field of a read frame to avoid contention. During a read frame, the PHY drives a 0 bit onto MDIO  
for the bit time that follows the idle bit and precedes the data field. During a write frame, this field consists of  
a 1 bit followed by a 0 bit.  
data  
The data field is 16 bits. The first data bit transmitted and received is the most significant bit of the data payload.  
16  
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MII interrupt operation  
TheTNETE2101canprovideaninterruptbasedoncertainPHYeventsthroughtheMIIMDIOsignal. Thisallows  
software to receive an interrupt on events, such as a change in link, without periodically polling the device.  
Interrupt is indicated by driving the MDIO terminal low after the quiescent cycle and while MDCLK is high. The  
quiescent cycle is the cycle following the data transfer, during which neither the MACs nor the PHYs drive  
the MDIO.  
The interrupt feature is controlled by register bits, MINT, INTEN, and TINT. MINT is the MII-interrupt bit  
(register 0x12, bit 15) and is set to a 1 when one or more interrupt events have occurred. INTEN is the  
interrupt-enable bit (register 0x11, bit 1) which allows MINT to generate an interrupt on the MDIO terminal.  
Additionally, to test interrupt operation (TINT), test interrupt (register 0x11, bit 0) can be set to a 1 which  
generates an interrupt, regardless of the value of MINT and INTEN.  
Once an interrupt has occurred, MINT can be set to a 0 again by reading the register that contains the event  
status. Table 5 shows all the events that can cause MINT to be set and the register location.  
Table 5. Interrupt Causes and Register Location  
EVENT  
JABBER  
LINK  
CAUSE  
REGISTER  
0x01  
BIT  
1
When set to a 1  
Change in state or is different from either the last read value of current state of LINK  
When set to a 1  
0x01  
2
RFAULT  
0x01  
4
AUTOCMPLT When set to a 1  
0x01  
5
PAGERX  
FEFI  
When set to a 1  
0x06  
1
When set to a 1  
0x12  
10  
11  
12  
13  
14  
SYNCLOSS  
TPENERGY  
PLOK  
When set to a 1  
0x12  
When set to a 1 and MANCONF is enabled  
Change in state and MANCONF is enabled  
When set to a 1  
0x12  
0x12  
PHOK  
0x12  
details of an interrupt on MDIO  
The first MII frame exchanged after power up on MDCLK/MDIO synchronizes the internal MII-state  
machine. (After the first MII frame, the TNETE2101 does not require the 32 contiguous 1s before the start  
of frame for synchronization.)  
A complete clock cycle (high and low) must occur after the last data bit. This clock cycle, or quiescent cycle,  
allows the device driving MDIO to set its output to a high-impedance state. After reaching the  
high-impedance state, MDIO goes high due to the required external pullup on the MDIO signal.  
Clock brought high again enables the interrupt to be driven on the MDIO line (MDIO = low). For as long as  
the clock is held high, if an interrupt occurs, MDIO is driven low. The interrupt occurring is not contingent  
on seeing another rising edge on the MDCLK, instead, it is clocked through, based on the internal PHY  
clock.  
On every rising edge thereafter, PHY samples the MDIO line to see if the management entity is outputing  
a low, signifying the start of frame. If the MDIO line is high, there is no start of frame and the PHY again drives  
the MDIO line low, if there is an interrupt. If start of frame is recognized, the PHY inhibits driving the interrupt  
onto the MDIO line until after the MII frame has completed.  
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PHY generic control register – GEN_ctl at 0x00  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
R
E
S
E
T
L
O
O
P
B
K
S
P
E
E
D
A
U
T
O
E
N
B
P
D
O
W
N
I
A
U
T
O
R
S
R
T
D
U
P
L
E
X
C
O
L
T
E
S
T
S
O
L
A
T
E
Reserved  
Figure 7. PHY Generic Control Register  
18  
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Table 6. PHY Generic Control Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
PHY reset. Writing a 1 to RESET causes the PHY to be reset and all registers (except GEN_ctl) to be reset to their  
default values. RESET is self-clearing–it returns a value of 1 when read, until the internal reset is complete (which  
takes no longer than 500 ms). Writing a 0 to RESET (default) has no effect. This operation can interrupt data  
communications.  
RESET  
15  
Loopback. LOOPBK enables or disables internal loopback within the PHY device. When LOOPBK is set to 1, data  
is wrapped internally within the PHY and does not appear on the network. When LOOPBK is cleared to 0 (default),  
data is transmitted to and received from the network. While the PHY is in loopback, all network lines are placed in  
a noncontentious state. If CLOOPBK is asserted low, loopback is enabled and this bit cannot be set to 0 but is read  
as 1.  
LOOPBK  
SPEED  
14  
13  
Speed select. Link speed is determined by way of either autonegotiation or manual setting. There are three methods  
by which the PHY speed can be determined:  
– Autonegotiation enabled. Speed determined by negotiation.  
– Autonegotiation disabled by CAUTONEG being low . Speed determined by CSPEED setting.  
– Autonegotiation disabled by register bit AUTOENB set to a 0. Speed determined by register bit SPEED setting.  
When SPEED is set to a 1 (default) the PHY speed is 100 Mbit/s and when set to a 0 the PHY speed is 10 Mbit/s.  
The value read from the SPEED bit always reflects the current PHY speed, regardless of which method is used to  
select the speed (as described previously).  
Autonegotiate enable. AUTOENB enables or disables the autonegotiation process if CAUTONEG is high. When  
AUTOENB is 0, the link is configured by way of the DUPLEX and SPEED bits, and the PHY implements the  
appropriate link-integrity test.  
AUTOENB  
12  
When AUTOENB is set to 1 (default), autonegotiation is enabled and the PHY engages in the autonegotiation  
process when a LINK FAIL condition is detected or the AUTORSRT bit is set. The link must not be treated as valid  
until the AUTOCMPLT bit and LINK bit are set to 1. If CAUTONEG terminal is low, autonegotiation is disabled, and  
AUTOENB cannot be set to 1 but is read as 0.  
Power down. When PDOWN is set to 1, the PHY is placed in a low power-consumption state. The time required for  
the PHY to power up after PDOWN is cleared can vary considerably. It is good practice to set RESET after this time  
to make certain that the PHY is in a valid state. If CPWRDOWN is asserted low, the PHY is powered down, and this  
bit cannot be set to 0 but is read as 1.  
PDOWN  
11  
10  
9
Isolate. The function of ISOLATE depends on whether the PHY is in repeater mode or node mode (determined by  
the REPEATER bit in TXPHY_ctl). In node mode, when ISOLATE is set to 1 (default), the PHY electrically isolates  
its data paths from the MII. In this state, it does not respond to MTXD0–MTXD3, MTXEN, and MTXER inputs, but  
presents a high impedance on its MTCLK, MRCLK, MRXDV, MRXER, MRXD0–MRXD3, and MCOL outputs. It still  
responds to management frames on MDIO and MDCLK. In repeater mode, when ISOLATE is set to 1, the PHY  
presents a high impedance on its MRCLK, MRXDV, MRXER, and MRXD0–MRXD3 outputs only. If CISOLATE is  
deasserted high, the ISOLATE function is disabled, and this bit cannot be set to 1 but is read as 0.  
ISOLATE  
AUTORSRT  
Restartautonegotiation. If autonegotiation has been enabled by setting AUTOENB to 1, the autonegotiation process  
can be restarted by setting AUTORSRT to 1. AUTORSRT is self clearing, and the PHY returns a value of 1 in this  
bit until autonegotiation fast-link pulse (FLP) data-burst transmission has been initiated. When AUTOENB is cleared  
to 0, AUTORSRT is read as 0. The default value of AUTORSRT is 0.  
Duplex mode. Duplex mode is determined by way of either autonegotiation or normal setting. There are three ways  
the PHY speed can be determined:  
– Autonegotiation enabled. Duplex determined by negotiation.  
– Autonegotiation disabled by CAUTONEG being low. Duplex determined by CDUPLEX setting.  
– Autonegotiation disabled by register bit AUTOENB set to a 0. Duplex determined by register bit DUPLEX setting.  
DUPLEX  
8
When DUPLEX is set to 1 (default), the PHY is in full duplex. When DUPLEX is set to 0, the PHY is in half duplex.  
The value read from the DUPLEX bit always reflects the current PHY duplex, regardless of which is used to select  
the duplex, (as described previously).  
Collision test mode. When COLTEST is set to 1 and LOOPBK is set to 1, the PHY asserts the collision-detect signal  
MCOL when transmit enable MTXEN is asserted. The default value of COLTEST is 0.  
COLTEST  
Reserved  
7
6–0  
Reserved. Read and write as 0.  
19  
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PHY generic status register – GEN_sts at 0x01  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
1
1
1
1
Reserved  
1
AUTOCMPLT RFAULT  
1
LINK  
JABBER  
1
Figure 8. PHY Generic Status Register  
Table 7. PHY Generic Status Register Bit Functions  
BIT  
FUNCTION  
NO.  
NAME  
0
15  
14  
100BASE-T4 ability. Not supported.  
1
1
1
1
100BASE-TX full-duplex ability. Supported by this PHY.  
100BASE-TX half-duplex ability. Supported by this PHY.  
10BASE-T full-duplex ability. Supported by this PHY.  
10BASE-T half-duplex ability. Supported by this PHY.  
Reserved. Read and write as 0.  
13  
12  
11  
Reserved  
10–7  
Management frame preamble suppression. This PHY accepts management frames with the preamble suppressed.  
Management frames sent over MDIO do not need to be preceded by the preamble pattern of 32 1s.  
1
6
5
Autoconfiguration complete. When AUTOCMPLT is read as 1, it indicates that the autonegotiation process has  
completed and the values of registers AN_adv, AN_lpa, AN_exp, and AN_np are valid. If autonegotiation is in  
progress, or has been restarted and AUTORSRT is still set to 1, or has been disabled by clearing AUTOENB to 0,  
the AUTOCMPLT bit reads as 0.  
AUTOCMPLT  
Remote fault. The RFAULT bit is set to 1 during autonegotiation if an error in the protocol is detected and negotiation  
is restarted. If the negotiation involved the exchange of multiple next pages, this bit indicates that the first of those  
pages needs to be reloaded into AN_np due to the restart. RFAULT is latched as 1 until the register is read. The  
default value of RFAULT is 0.  
RFAULT  
1
4
3
Autonegotiation ability. Supported by this PHY.  
Link status. In general, when LINK is set to 1, the PHY is reporting that a good link is available to the link partner for  
exchange of data. The value of LINK is latched until the register is read. The default value of LINK is 1.  
In 10BASE-T mode, LINK is set to 1 when the PHY has determined that a valid 10BASE-T link is established. LINK  
read as a 0 indicates that the link is not valid. The PHY implements the standard 10BASE-T link integrity test state  
machine. To maintain a good link, link pulses are expected every 8–24 ms. If no link pulses are seen for over 100 ms,  
the link invalid state is entered, and this bit is cleared. If AUTOENB is not set, then the bit is set again after seven  
consecutive, correctly timed link pulses are received.  
LINK  
2
In 100BASE-TX mode, the LINK bit is set when the descrambler has locked onto the incoming data stream and has  
remained locked for a minimum of 330 s.  
If AUTONEG is set, then the link is becoming invalid, which causes the autonegotiation process to restart.  
Jabber detect. The jabber function is not specified for 100BASE-TX PHYs, so JABBER always reads as 0 (default)  
when the PHY is operating in the 100-Mbit/s mode.  
When JABBER is read as 1, it indicates that a 10BASE-T jabber condition has been detected. JABBER is latched  
as 1 until the register is read or PHY is reset.  
JABBER  
1
0
The jabber condition occurs when a single packet transmission exceeds 20 ms. In the jabber condition, all transmit  
requests are ignored, MCOL is asserted high, and collision detection is disabled, as is the internal loopback of  
transmitdata (when in half-duplex mode). The jabber condition persists for 576–628 ms after deassertion of MTXEN  
before packet transmission can restart.  
1
Extended capability. This PHY implements an extended register set.  
20  
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PHY generic identifier – GEN_id_hi/GEN_id_lo at 0x02/03  
These two hardwired 16-bit registers contain an identifier code for the 10BASE-T/100BASE-TX PHY.  
GEN_id_hi contains 0x4000, and GEN_id_lo contains 0x503X.  
The PHY ID is composed of bits 3–24 of the 25-bit organizationally unique identifier (OUI) assigned to TI by  
IEEE. Bit 3 of the OUI maps to bit 15 of GEN_id_hi, bit 4 of the OUI to bit 14 of the GEN_id_hi, and so on.  
Figures 9 and 10 show the bit layout of GEN_id_hi and GEN_id_lo.  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
OUI  
Bits 3–18  
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9. PHY Generic Identifier – GEN_id_hi at 0x02  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
OUI  
Bits 19–24  
Manufacturer Model Number  
Manufacturer Revision Number  
0
1
0
1
0
0
0
0
0
0
1
1
X
X
X
X
Figure 10. PHY Generic Identifier – GEN_id_lo at 0x03  
21  
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autonegotiation advertisement register – an_adv at 0x04  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
NP  
ACK  
RF  
Technology Ability Field  
Selector Field  
Figure 11. Autonegotiation Advertisement Register  
Table 8. Autonegotiation Advertisement Register Bit Functions  
BIT  
FUNCTION  
NO.  
NAME  
Autonegotiation next page. When NP is set to 1, the autonegotiation process indicates to the link partner that the  
PHY wishes to exchange next pages. The capability of the link partner to exchange next pages can be determined  
by the value of the LPNPABLE bit in the AN_exp register. When the link partner is capable of next-page exchange,  
it requests an exchange by setting the LPNP bit to 1 in the AN_lpa register. Then, the autonegotiation process waits  
untilthenextpageiswrittentotheAN_npregister,andthelinkpartnerhashaditsnextpageloaded.Thelinkpartner’s  
next page then is received into the AN_lpa register.  
NP  
15  
A consequence of this process is that the PHY fails to complete autonegotiation if the PHY and its link partner agree  
to exchange next pages, but the link partner never sends its next page. A software timeout, which forces  
renegotiation with NP cleared to 0, should be implemented to avoid this situation.  
The default value of NP is 0.  
ACK  
RF  
14  
13  
Acknowledge. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.  
Remote fault. When RF is set to 1, the PHY indicates a remote fault condition to its link partner. The type of fault,  
as well as the criteria and method of fault detection, is PHY specific. The default value of RF is 0.  
Autonegotiation advertised technology ability. Bits 12–5 represent an 8-bit value sent to the link partner to indicate  
the abilities of the PHY. Once negotiated, the values of the bits are reflected in bits 12–5 in register 0×05 of the link  
partner.  
12,11  
Bits 11 and 12 are set to 0 by default. These bits are reserved for future use according to IEEE 802.3u. These bits  
can be changed and are sent to the link partner during autonegotiation.  
Pause operation of full duplex links. Defined for use at the MAC level and when set to a 1 signifies that the MAC is  
capable of performing the pause function. The pause capability is exchanged between the PHYs during the  
autonegotiationbut does not change the PHY’s mode of operation. The pause function is valid only during full-duplex  
operation regardless of the medium. The default value of this bit is 0.  
Technology  
Ability  
Field  
10  
9
8
7
6
5
100BASE-T4. Default value is a 0 and should not be set to a 1 since the TNETE2101 does not support this medium.  
100BASE-TX full duplex. Set to 1 to advertise availability to the link partner.  
100BASE-TX half duplex. Set to 1 to advertise availability to the link partner.  
10BASE-T full duplex. Set to 1 to advertise availability to the link partner.  
10BASE-T half duplex. Set to 1 to advertise availability to the link partner.  
Autonegotiationselector field code. This field has a default value of 0001, meaning that the PHY supports only IEEE  
Std 802.3 format link code words.  
Selector Field  
4–0  
22  
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autonegotiation link partner ability register – an_lpa at 0x05  
The link partner ability register, AN_lpa, has three different formats, depending on when the page is received.  
The first page received from the link partner always is in the base-page encoding and is used by the PHY for  
autoconfiguration. If the link partner supports next-page exchange, subsequently received pages can be in  
either message-page or unformatted-page encoding, as determined by the value of the LPNP bit (in AN_lpa).  
The use of next pages is summarized as:  
Both the PHY and the link partner must indicate next-page ability before either can commence exchange  
of next pages.  
If both devices are next-page able, then both devices must send at least one next page.  
Next-page exchange continues until neither device on a link has more pages to transmit [as indicated by  
the LPNP bit (in AN_lpa) and the NP bit (in AN_adv)]. A message page with a null-message code field value  
is sent if the device has no other information to transmit.  
A message code can carry a specific message or information that defines how subsequent unformatted  
page(s) should be interpreted.  
If a message code references unformatted pages, the unformatted pages immediately follow the  
referencing message code in the order specified by the message code.  
Unformatted page users are responsible for controlling the format and sequencing of their unformatted  
pages.  
base-page encoding  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
LPNP  
ACK  
LPRF  
Link Partner Technology Ability Field  
Link Partner Selector Field  
Figure 12. Autonegotiation Link Partner Ability Register  
Table 9. Autonegotiation Link Partner Ability Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
Link partner next page. When LPNP is set to 1, the link partner is indicating that it wishes to exchange a next  
page. See the description of NP in register AN_adv for more information on next-page exchange.  
LPNP  
15  
ACK  
14  
13  
Acknowledge. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.  
Link partner remote fault. When LPRF is set to 1, the link partner is reporting a remote fault condition.  
LPRF  
Link partner technology ability field. Bits 12–5 are updated during autonegotiate with the 8-bit values received  
from the link partner’s PHY advertisement register. Bits 9–5 are examined to determine the highest  
common-link capability between the two PHYs.  
12, 11  
10  
Bit values for 12–11 are updated but to do so affects the PHY’s mode of operation.  
Pause operation for full duplex links. Defined for use at the MAC level and when set to a 1 after autonegotiation,  
signifies that the link partner’s MAC is capable of performing the pause function. The pause capability is  
exchanged between the PHYs during the autonegotiation but does not change the PHY’s mode of operation.  
The pause function is only valid during full-duplex operation, regardless of the medium.  
Link Partner  
Technology  
Ability  
Field  
9
8
7
6
5
100BASE-T4. Set to a 1 if link partner supports 100BASE-T4. The TNETE2101 does not support this capability.  
100BASE-TX full duplex. Set to 1 if supported by the link partner.  
100BASE-TX half duplex. Set to 1 if supported by the link partner.  
10BASE-T full duplex. Set to 1 if supported by the link partner.  
10BASE-T half duplex. Set to 1 if supported by the link partner.  
Link partner selector field. This 5-bit value encodes the format of this register. The PHY supports only IEEE  
Std 802.3 format fields (see description of bits 12–5), code 00001. (The only other currently specified IEEE  
value is 00010 for IEEE Std 802.9a multimedia frames).  
Link Partner  
Selector Field  
4–0  
23  
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message-page encoding (LPMP = 1)  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
LPNP  
ACK  
LPMP ACK2  
T
Message Code Field  
Figure 13. Message-Page-Encoding Register  
Table 10. Message-Page-Encoding Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
Link partner next page. When LPNP is set to 1, the link partner is ready to exchange an extra next page.  
See the description of NP in register AN_adv for more information on next-page exchange.  
LPNP  
15  
ACK  
LPMP  
ACK2  
T
14  
13  
12  
11  
Acknowledge. Reserved for internal use of the autonegotiation process. Ignore during read.  
Link partner message page. When LPMP is set to 1, register AN_lpa contains a message page.  
Acknowledge 2. Reserved for internal use of the autonegotiation process. Ignore during read.  
Toggle. Reserved for internal use of the autonegotiation process. Ignore during read.  
Message code. An 11-bit message code. See Table 11 for descriptions of the currently defined IEEE  
message codes.  
Message Code Field  
10–0  
message-code field values  
Table 11 summarizes the message-code field values specified in IEEE Std 802.3. All message codes not  
specified are reserved for future IEEE use or allocation.  
Table 11. Message-Code Field Values  
MESSAGE  
CODE  
BIT 10–0  
MESSAGE-CODE DESCRIPTION  
Reserved for future autonegotiation use  
0
1
00000000000  
00000000001  
Null message. The null-message code is transmitted during next-page exchange when the local device has  
no further messages to transmit and the link partner is still transmitting valid next pages.  
Technology ability extension code 1 [one unformatted page (UP) with technology ability field to follow]. This  
message code is reserved for future expansion of the technology ability field and indicates that a defined user  
code with a specific technology ability field encoding follows.  
2
3
00000000010  
00000000011  
Technology ability extension code 2 (two UPs with technology ability fields to follow). This message code is  
reserved for future expansion of the technology ability field and indicates that two defined user codes with  
specific technology ability field encoding follow.  
Remote-fault number code (one UP with binary-coded remote fault follows). This message code is followed  
by a single user code whose encoding specifies the type of fault that has occurred. The following user codes  
are defined:  
4
00000000100  
0 – RF test. Used to test remote-fault operation.  
1 – Link loss  
2 – Jabber  
3 – Parallel detection fault. Sent to identify when PDFAULT (in AN_exp) is set.  
24  
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Table 11. Message-Code Field Values (Continued)  
MESSAGE  
CODE  
BIT 10–0  
MESSAGE CODE DESCRIPTION  
OUI-tagged message. The OUI-tagged message consists of a single message code of 0000.0000.0101,  
followed by four user codes defined in the following chart. The numbers indicate where each bit of the 24-bit  
OUI should be stored in the 11-bit user code. Bits 8–0 of the third user code and the fourth (and final) user code  
contain a user-defined user-code value that is specific to the OUI transmitted.  
Bit  
10  
Bit  
0
User-Code Encoding of OUI  
5
00000000101  
1st  
2nd  
3rd  
4th  
23  
12  
1
22  
11  
0
21  
10  
20  
9
19  
8
18  
7
17  
6
16  
5
15  
4
14  
3
13  
2
User-defined user code specific to OUI  
User-defined user code specific to OUI  
PHY identifier tag code. The PHY ID tag code message consists of a single message code of 0000.0000.0110  
followed by four user codes defined in the following chart. The numbers indicate where each bit of the 32-bit  
PHY ID (stored in GEN_id_hi register 0x2:15–0 and GEN_id_lo register 0x3:15–0) should be stored in the  
11-bit user code. Bit 0 of the third user code and the fourth (and final) user code contain a user-defined  
user-code value that is specific to the PHY ID transmitted.  
Bit  
10  
Bit  
0
User-Code Encoding of PHY ID  
6
00000000110  
0x2  
15  
0x2  
14  
0x2  
13  
0x2  
12  
0x2  
11  
0x2  
10  
0x2  
9
0x2  
8
0x2  
7
0x2  
6
0x2  
5
1st  
0x2  
4
0x2  
3
0x2  
2
0x2  
1
0x2  
0
0x3  
15  
0x3  
14  
0x3  
13  
0x3  
12  
0x3  
11  
0x3  
10  
2nd  
0x3  
9
0x3  
8
0x3  
7
0x3  
6
0x3  
5
0x3  
4
0x3  
3
0x3  
2
0x3  
1
0x3  
0
UD  
UC  
3rd  
4th  
User-defined user code specific to PHY ID  
2047  
11111111111  
Reserved for future autonegotiation use  
25  
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unformatted-page encoding (LPMP = 0)  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
LPNP  
ACK  
LPMP ACK2  
T
Unformatted Code Field  
Figure 14. Unformatted-Page Encoding Register  
Table 12. Unformatted-Page Encoding Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
Link partner next page. When LPNP is set to 1, the link partner is indicating that it wishes to exchange  
an extra next page. Refer to the description of NP in register AN_adv for more information on next-page  
exchange.  
LPNP  
15  
ACK  
LPMP  
ACK2  
T
14  
13  
12  
11  
Acknowledge. Reserved for internal use of the autonegotiation process. Ignore during read.  
Link partner message page. When LPMP is cleared to 0, register AN_lpa contains an unformatted page.  
Acknowledge 2. Reserved for internal use of the autonegotiation process. Ignore during read.  
Toggle. Reserved for internal use of the autonegotiation process. Ignore during read.  
Unformatted code. 11-bit user code. The format of this code is determined by the message code (see  
Table 11).  
Unformatted Code Field  
10–0  
autonegotiation expansion register – AN_exp at 0x06  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
Reserved  
PDFAULT  
LPNPABLE  
1
PAGERX LPANABLE  
Figure 15. Autonegotiation Expansion Register  
Table 13. Autonegotiation Expansion-Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
Reserved  
15–5  
Reserved. Read and write as 0.  
Parallel detection fault. The PDFAULT bit is set to 1 during autonegotiation if the PHY detects a valid 10BASE-T or  
100BASE-TXlinkthatfailswithin500–1000msorifboththe10BASE-Tand100BASE-TXlinkmonitorsreportagood  
link. PDFAULT is latched until this register is read, then it is cleared to 0 (default).  
PDFAULT  
4
Link-partner next-page able. When LPNPABLE is set to 1, the link partner is indicating that it is implementing the  
autonegotiation next-page ability. The default value of LPNPABLE is 0.  
LPNPABLE  
1
3
2
1
Next-page able. This PHY supports autonegotiation next-page exchange.  
Page received. The PAGERX bit is set to 1 when a new link code word has been received and stored in the AN_lpa  
register. PAGERX is latched until this register is read, then it is cleared to 0 (default).  
PAGERX  
Link-partner autonegotiation enable. When LPANABLE is set to 1, the PHY has received link code word(s) from the  
link partner during autonegotiation. The value of LPANABLE is retained after autonegotiation completes, and is  
re-evaluated only during a subsequent renegotiation (whether caused by a LINK FAIL condition or a forced restart)  
or PHY reset. The default value of LPANABLE is 0.  
LPANABLE  
0
26  
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autonegotiation next-page transmit register – AN_np at 0x07  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
NP  
ACK  
MP  
ACK2  
T
Message or Unformatted Code Field  
Figure 16. Autonegotiation Next-Page Transmit Register  
Table 14. Autonegotiation Next-Page Transmit-Register Bit Functions  
BIT  
FUNCTION  
NO.  
15  
NAME  
Next page. When a next page with NP set to 1 is transmitted, the link partner is informed that another next page  
is to be transmitted (see Table 11). The default value of NP is 0.  
NP  
ACK  
MP  
14  
Acknowledge. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.  
Messagepage. When MP is set to 1, AN_np contains a message-page code field. When MP is cleared to 0, AN_np  
contains an unformatted-page code field (see Table 11). The default value of MP is 1.  
13  
ACK2  
T
12  
11  
Acknowledge 2. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.  
Toggle. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.  
Message or  
Unformatted  
Code Field  
Message or unformatted code field (see Table 11). The default value of the code field is 000.0000.0001, the null  
message code.  
10–0  
PHY identifier high/low – TXPHY_id at 0x10  
This hardwired 16-bit register contains a TI-assigned identifier code for the PHY PMIs. An additional identifier  
is required to identify non-IEEE Std 802.3 PHY/PMIs, which are not otherwise supported by the IEEE Std 802.3  
MII specification. The identifier code for the internal 10BASE-T/100BASE-TX PHY is 0x0003.  
PHY control register – TXPHY_ctl at 0x11  
BIT  
15  
BIT  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
I
S
W
A
P
O
L
M
A
N
C
O
N
F
S
Q
E
E
N
M
T
E
S
T
F
I
B
E
R
F
E
F
E
N
N
O
E
N
D
E
C
N
O
A
L
I
G
N
D
U
P
O
N
L
R
E
P
E
A
T
R
X
R
E
S
E
T
N
O
L
N
F
E
I
T
I
N
T
G
L
I
N
K
N
T
E
N
I
W
N
K
P
Y
E
R
Figure 17. PHY Control Register  
Table 15. PHY Control-Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
Ignore link. When IGLINK is cleared to 0 (default), the 10BASE-T PHY expects to receive link pulses from the link  
partner (hub, switch, and so on) and clears the LINK bit in the GEN_sts register to 0 if they are not present. When  
IGLINK is set to 1, the internal link-integrity-test state machine is forced to stay in the LINK GOOD state even when  
no link pulses are being received, and it also causes the LINK bit to stay set to 1.  
IGLINK  
15  
14  
Swappolarity. Allows swapping the receive polarity when the MANCONF bit is set to 1. Writing a 1 to SWAPOLcauses  
the PHY to use the reverse of the IEEE Std 802.3 standard polarity for the ARCVP/ARCVN 10BASE-T receiver-input  
pair. This is used to compensate for a cable in which the receive pair has been wired incorrectly.  
SWAPOL  
See the PLOK bit description in register 0×12 for a detailed explanation.  
27  
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10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Table 15. PHY Control Register Bit Functions (Continued)  
BIT  
NAME  
FUNCTION  
NO.  
Manualconfiguration. Writing a 1 to MANCONF enables manual configuration of the PHY polarity using the SWAPOL  
bit. Thedefaultvalueofthisbitis0whichenablesautomaticdetectionofpolaritybymonitoringlinkpulsesforinversion.  
See the PLOK bit description in register 0×12 for a detailed explanation.  
MANCONF  
13  
Signal quality error (SQE) enable. When SQEEN is set to 1, the 10BASE-T PHY (when selected) performs the SQE  
test function at the end-of-packet transmission. The default value of SQEEN is 1.  
SQEEN  
12  
The SQE test provides an internal simulated collision to test collision-detect circuit integrity after a transmission. In  
10BASE-T mode, the SQE test asserts MCOL between 600–1600 ns after the last positive edge of a frame is  
transmitted, with the collision event lasting between 500–1500 ns.  
Manufacturingtest. When MTEST is set to 1, the PHY is placed in manufacturing test mode. Manufacturing test mode  
is reserved for TI manufacturing test only. The default value of MTEST is 0. Operation of the PHY and MII registers  
is undefined when this bit is set.  
MTEST  
FIBER  
11  
10  
100BASE-FX mode. When FIBER is set to 1, PHY disables its cipher-stream scrambler and descrambler. The UTP  
interface terminals are placed in a nonfunctional low-power state and the differential PECL fiber-interface terminals  
are activated. The default value of FIBER is 0. If CFIBER is asserted low, the fiber interface is enabled and this bit  
cannot be set to 0 but is read as 1.  
Far-end fault indication enable. When both FEFEN and FIBER are set to 1, the PHY transmits the far-end fault  
indication (FEFI) symbol stream (consisting of 84 1s and 0) when the 100BASE-FX signal detect is deasserted. Also,  
atthistimetheFEFIbitinTXPHY_stsissetto1.TheFEFIsystemisspecifiedforusein100BASE-FXfiberapplications  
only. The default value of FEFEN is 0.  
FEFEN  
9
8
No encode/decode. When NOENDEC is set to 1, the 100BASE-TX PHY bypasses its 5B4B encoder and decoder.  
Instead, it takes the 5-bit code presented on MTXD0–MTXD3 and MTXER (most significant bit) as transmit data, and  
presents the received 5B code groups on MRXD0–MRXD3 and MRXER (most significant bit). The default value of  
NOENDEC is 0. This mode of operation is provided for applications test purposes.  
NOENDEC  
If CPASS5B terminal is asserted low, the NOENDEC mode is enabled and this bit cannot be set to 0 but is read as 1.  
No symbol alignment. When NOALIGN is set to 1, the 100BASE-TX receive-symbol-alignment block is bypassed and  
the 5-bit descrambled receive symbols are passed directly to the 5B4B decoder.  
NOALIGN  
DUPONLY  
7
6
Duplex LED. When DUPONLY is set to 1, the LDUPCOL LED driver indicates the duplex mode in which the PHY is  
operating and does not indicate network collisions. The default value of DUPONLY is 0.  
Repeater-modeenable. When REPEATER is set to 1, the PHY does not assert MCRS in response to transmit activity  
in100BASE-TXmode. Also, theISOLATE bit in the GEN_ctl register causes only MRCLK, MRXD0–MRXD3, MRXDV,  
and MRXER to resort to a high-impedance state. The default value of REPEATER is 0. If CREPEATER is asserted  
low, the repeater mode is enabled and this bit cannot be set to 0 but is read as 1.  
REPEATER  
RXRESET  
5
4
100BASE-TX receive reset. Writing a 1 to this self-clearing bit allows the 100BASE-TX receive logic (descrambler,  
aligner, and 5B4B decoder) to be reset without affecting other parts of the PHY. The default value of RXRESET is 0.  
Disable link-pulse transmission. When NOLINKP is set to 1 and IGLINK is set to 1, the PHY does not transmit any  
form of link pulses. In 10BASE-T applications, the link partner does not detect a good link and does not transmit any  
data, unless it is not implementing the link-integrity test (for example, a PHY with IGLINK set to 1). Autonegotiation  
shouldbedisabledbyclearingAUTOENBto0whenNOLINKPissetbecausenoautonegotiationFLPsaretransmitted  
to the link partner. NOLINKP has no effect on the PHY if IGLINK is cleared to 0. The default value of NOLINKP is 0.  
This mode of operation is provided for application-test purposes.  
NOLINKP  
NFEW  
3
2
Not far end wrap. NFEW has meaning only when the LOOPBK bit of GEN_ctl is set to 1. Writing a 1 to NFEW causes  
the PHY to wrap the MTXD input data to the MRXD output just after the MII interface. Writing a 0 to NFEW causes  
thePMItowraptheTXdatatotheRXjustbeforethenetworktransceiverinterface(either10BASE-Tor100BASE-TX).  
When NFEW is set to 1, preamble is wrapped without degradation (in normal operation, the PHY may lose some  
preamble bits during initial clock-recovery synchronization). The default value of NFEW is 0.  
Interrupt enable. Writing a 1 to INTEN allows the PHY to generate interrupts on the MII when the MINT bit is set to 1.  
Writing a 0 to INTEN prevents the PHY from generating any MII interrupts. INTEN does not disable test interrupts. The  
default value of INTEN is 0.  
INTEN  
TINT  
1
0
Test interrupt. When TINT is set to 1, the PHY generates interrupts on the MII, regardless of the value of the MINT  
and INTEN bits. TINT is to be used for diagnostic test of the MII-interrupt function. The default value of TINT is 0.  
28  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
PHY status register – TXPHY_sts at 0x12  
BIT  
BIT  
15  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
MINT  
PHOK  
PLOK  
TPENERGY SYNCLOSS  
FEFI  
Reserved  
Figure 18. PHY Status Register  
Table 16. PHY Status-Register Bit Functions  
BIT  
NAME  
FUNCTION  
NO.  
MII Interrupt. MINT indicates an MII-interrupt condition. The MII-interrupt request is activated and latched until this  
register is read. Writing to MINT has no effect. MINT is set to 1 when:  
– JABBER (register 0x0, bit 1) is set to 1.  
– LINK (register 0x0, bit 2) changes state or is different from either the last read value or the current state of the link.  
– RFAULT (register 0x1, bit 4) is set to 1.  
– AUTOCMPLT (register 0x1, bit 5) is set to 1.  
– PAGERX (register 0x6, bit 1) is set to 1.  
– FEFI (register 0x12, bit 10) is set to 1.  
†
MINT  
15  
– SYNCLOSS (register 0x12, bit 11) is set to 1.  
– PHOK (register 0x12, bit 14) is set to 1.  
Additional interrupt sources are active only when the MANCONF bit (register 0x11, bit 13) is set to 1. MINT is set  
to a 1 when:  
– TPENERGY (register 0x12, bit 12) is set to 1.  
– PLOK (register 0x12, bit 13) changes state.  
Power high OK. When PHOK is set to 1, it indicates that the oscillator circuit connected to XTAL1 has begun to  
oscillate (and perform around 75 cycles). PHY-sourced clocks (MRCLK and MTCLK) are not valid until PHOK is  
asserted. The clocks can take up to 50 ms to become stable and the PHY requires the RESET bit to be set to make  
certain it is in a valid state. When PHOK is 0, the PHY is not in a fully operational state.  
PHOK  
PLOK  
14  
13  
Polarity OK. PLOK set to a 1 (default) signifies that the 10BASE-T PHY is receiving valid (noninverted) link pulses.  
PLOK always is set to a 1 when MANCONF is set to a 0, since the PHY automatically corrects polarity. If MANCONF  
is set to a 1 for manual polarity configuration, PLOK is cleared to a 0 if a sequence of seven consecutive inverted  
link pulses is detected. PLOK can be set to a 1 again only if the SWAPOL bit is toggled and then 1 noninverted link  
pulse is received.  
If MANCONF is a 1 and then cleared to a 0 when PLOK is still a 0, PLOK is not set to a 1 until SWAPOL is toggled.  
This reenables the autopolarity detection and PLOK remains a 1.  
10BASE-T polarity is determined strictly from link pulses and not from received data or TP idles.  
Twisted-pair energy detect. When TPENERGY is set to 1, it indicates that the PHY is receiving impulses on  
ARCVP/ARCVN.  
TPENERGY  
SYNCLOSS  
12  
11  
100BASE-TX receive descrambler synchronization loss. The 100BASE-TX descrambler expects to receive at least  
12 consecutive IDLE symbols every 722 µs. If these are not seen, then SYNCLOSS is set to 1, and the descrambler  
attempts to resynchronize itself to the incoming scrambled data stream. The value of SYNCLOSS is latched high  
until this register is read.  
Far-end fault indication. When enabled via the FEFEN bit in TXPHY_ctl, this bit is set to 1 if the FEFI signaling  
sequence is being transmitted by the link partner. The value of FEFI is latched (held) high until this register is read.  
FEFI  
10  
Reserved  
9–0  
Reserved. Read and write as 0.  
†
Useful for switching applications (TI patented)  
29  
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
†
absolute maximum ratings  
Supply voltage range: V  
V
Input voltage range:TTL, V –0.5 V to V  
5-V tolerant TTL, V –0.5 V to V  
PECL, V (<4.6 V max) V  
Output voltage range: TTL, V –0.5 V to V  
5-V tolerant TTL, V –0.5 V to V  
PECL, V (<4.6 V max) V  
Thermal impedance, junction-to-ambient package, Z  
V
, XMT_V  
, (see Notes 1 and 2)–0.5 V to 4.6 V  
DD, DDA  
DDA  
(see Notes 1 and 2)–0.5 V to 5.5 V  
DD5  
+ 0.5 V  
I
DD  
+ 0.5 V  
I
DD5  
–2.02 V to V  
+ 0.5 V  
+ 0.5 V  
I
DD  
DD  
O
DD  
O
+ 0.5 V  
DD5  
–2.02 V to V  
+ 0.5 V  
O
DD  
DD  
: Airflow = 068.40°C/W  
θJA  
Airflow = 150 ft/min57.45°C/W  
Thermal impedance, junction-to-case package, Z  
1.95°C/W  
θJC  
Operating case temperature range, T 0°C to 95°C  
C
Storage temperature range, T –65°C to 150°C  
stg  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values are with respect to GND.  
2. Turning power supplies on and off (cycling sequence) within a mixed 5-V/3.3-V system is an important consideration. The designer  
must observe a few rules to avoid damaging the TNETE2101. Check with the manufacturers of all components used in the 3.3-V  
to 5-V interface to ensure that no unique device characteristics exist that would lead to rules more restrictive than the TNETE2101  
requires.  
•
The optimum solution to power-supply sequencing in a mixed-voltage system is to ramp up the 3.3-V supply first. A power-on  
reset component operating from this supply forces all 5-V-tolerant outputs into the high-impedance state. Then, the 5-V supply  
is ramped up. On power down, the 5-V rail deenergizes first, followed by the 3.3-V rail.  
•
The second-best solution is to ramp both the 3.3-V and the 5-V rails at the same time, making sure that no more than 3.6 V exists  
between these two rails during the ramp up or down. If the 3.3 V is derived from the 5 V, then the 3.3 V rises as the 5 V rises,  
sothe5-Vrailneverexceedsthe3.3-Vrailbymorethan3.6V. Boththeoptimumandsecond-bestalgorithmsforpowerupprevent  
device damage. If it is impractical to implement ramping, follow these rules:  
–
When turning on the power supply, all 3.3-V and 5-V supplies should start ramping from 0 V and reach 95 percent of their  
end-point values within 25 ms. All bus contention between the device and external devices is eliminated by the end of 25 ms.  
When turning off the power supply, 3.3-V and 5-V supplies should start ramping from steady-state values and reach 5 percent  
of their final values within 25 ms. All bus contention between devices and external devices is eliminated by the end of 25 ms.  
There is a 250-s lifetime maximum at greater than 3.6-V difference between the supply rails. Holding the ramp-up/ramp-down  
period to 25 ms per power-on/off cycle should not significantly contribute to mean-time-between-failure (MTBF) shifts during  
product lifetimes.  
–
30  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
recommended operating conditions  
MIN  
3
NOM  
3.3  
5
MAX  
3.6  
UNIT  
V
V
V
, V  
, XMT_V  
Supply voltage  
DD DDA  
DDA  
Reference voltage  
4.5  
0
5.5  
V
DD5  
TTL  
V
DD  
5.5  
V
V
V
Input voltage  
5-V TTL  
PECL  
0
V
V
I
V
V
V
V
– 0.5  
TTP  
0
DD  
TTL, 5-V TTL  
PECL  
V
DD  
– 0.5  
Output voltage  
O
TTP  
0
DD  
LED  
V
V
DD  
TTL  
2
2
DD  
5.5  
High-level input voltage  
Low-level input voltage  
5-V TTL  
PECL  
V
V
IH  
V
– 1.35  
0
V
DD  
– 0.70  
0.8  
DD  
TTL, 5-V TTL  
PECL  
V
V
IL  
V
– 2  
V
DD  
– 1.55  
DD  
Termination voltage  
PECL  
V
– 2  
50  
V
TTP  
DD  
R
Differential-termination resistance  
PECL  
Ω
t
electrical characteristics over recommended operating conditions  
PARAMETERS  
TEST CONDITIONS  
TTL, 5-V TTL  
PECL  
MIN  
2.4  
TYP  
MAX  
UNIT  
I
= –4 mA  
OH  
V
OH  
High-level output voltage  
V
50 Ω to V –2  
1.50  
2.30  
0.8  
DD  
= min, T = max  
V
LEDs (see Note 3)  
PECL  
DD  
C
V
V
Low-level output voltage  
50 Ω to V –2  
0.20  
1.20  
0.30  
0.4  
V
OL  
DD  
= 4 mA  
I
TTL, 5-VTTL  
PECL  
OL  
Differential input voltage  
2.10  
20  
V
ID  
I
I
I
Low-level input current  
V = V  
TTL, 5-V TTL, PECL  
µA  
µA  
µA  
IL  
I
IL(min)  
High-level input current  
V = V  
TTL, PECL  
–20  
–20  
IH  
I
IH(max)  
High-impedance-state output current  
TTL, LED, PECL  
Full duplex  
OZ  
100BASE-TX,  
Power down  
200  
20  
6
I
Supply current, 3.3 V (see Note 4)  
mA  
DD  
C
C
Capacitive input  
Capacitive output  
pF  
pF  
i
6
o
NOTES: 3. LACTIVITY, LDUPCOL, LLINK, LSPEED  
4. Typical values measured at 25°C without LEDs connected  
oscillator requirements  
PARAMETERS  
MIN  
TYP  
MAX  
UNIT  
MHz  
ppm  
%
Clock frequency  
20  
Clock frequency error  
Clock duty cycle  
–50  
40  
50  
60  
V
V
2.85  
V
V
OH  
DD  
–0.50  
0.80  
5
V
OL  
t , t (see Note 5)  
r f  
ns  
NOTE 5: Measured at 20%–80% transition low-to-high or high-to-low points  
31  
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
MDIO timing requirements (see Figure 19)  
NO.  
1
PARAMETERS  
MIN  
10  
MAX  
UNIT  
ns  
t
t
Setup time, MDIO valid to MDCLK high (see Note 6)  
Hold time, MDCLK high to MDIO changing (see Note 6)  
su(MDIO)  
2
10  
ns  
h(MDIO)  
NOTE 6: MDIO is a bidirectional signal that can be sourced by the TNETE2101 or the PMI/PHY. When the TNET2101 sources the MDIO signal,  
TNETE2101 asserts MDIO synchronous to the rising edge of MDCLK.  
MDCLK  
(input)  
1
2
2 V  
MDIO  
(I/O)  
0.8 V  
Figure 19. MDIO Sourced by External Controller  
MDIO timing requirements (see Figure 20)  
NO.  
MIN  
MAX  
300  
UNIT  
1
2
t
t
Access time, MDIO valid to MDCLK high (see Note 7)  
Cycle time  
0
ns  
a(MDIO)  
400  
c(MDCLK)  
NOTE 7: When the MDIO signal is sourced by the PMI/PHY, it is sampled by the TNETE2101 synchronous to the rising edge of MDCLK.  
MDCLK  
(input)  
2 V  
2
1
2 V  
MDIO  
(I/O)  
0.8 V  
Figure 20. MDIO Sourced by the TNETE2101  
32  
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
MII transmit timing requirements (see Figure 21)  
10BASE-T, 100BASE-TX, 100BASE-FX  
NO.  
1
PARAMETER  
MIN  
10  
10  
10  
0
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
Setup time, MTXD3–MTXD0 valid to MTCLK↑  
Setup time, MTXEN valid to MTCLK↑  
Setup time, MTXER valid to MTCLK↑  
Hold time, MTCLK↑ to MTXD3–MTXD0 invalid  
Hold time, MTCLK↑ to MTXEN↓  
su(MTXD3–MTXD0)  
1
ns  
su(MTXEN)  
1
ns  
su(MTXER)  
2
ns  
h(MTXD3–MTXD0)  
h(MTXEN)  
2
0
ns  
2
Hold time, MTCLK↑ to MTXER↓  
0
ns  
h(MTXER)  
3
Cycle time, 10BASE-T  
400  
40  
ns  
c(MTCLK)  
3
Cycle time, 100BASE-TX, 100BASE-FX  
ns  
c(MTCLK)  
3
2
1
MTCLK  
(output)  
2 V  
MTXD3–MTXD0  
MTXEN  
MTXER  
(inputs)  
2 V  
0.8 V  
Figure 21. MII Transmit  
MII receive timing requirements (see Figure 22)  
10BASE-T, 100BASE-TX, 100BASE-FX  
NO.  
1
PARAMETER  
MIN  
TYP  
MAX  
20  
UNIT  
ns  
t
t
t
t
t
t
Delay time, MRXD3–MRXD0 valid to MRCLK↑  
Delay time, MRXDV valid to MRCLK↑  
Delay time, MRXER valid to MRCLK↑  
Delay time, MCOL valid to MRCLK↑  
Cycle time, 10BASE-T  
10  
10  
10  
10  
d(MRXD3–MRXD0)  
d(MRXDV)  
d(MRXER)  
d(MCOL)  
1
20  
ns  
1
20  
ns  
1
20  
ns  
2
400  
40  
ns  
c(MRCLK)  
2
Cycle time, 100BASE-TX, 100BASE-FX  
ns  
c(MRCLK)  
2
MRCLK  
(output)  
2 V  
1
MRXD3–MRXD0  
MRXDV  
MRXER  
MCOL  
2 V  
0.8 V  
(outputs)  
Figure 22. MII Receive  
33  
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
reset timing requirements (see Figure 23)  
NO.  
1
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
Cycle time, XTAL1  
Pulse duration  
50  
c(XTALI)  
2
50  
10  
5
µs  
w(MRSTL)  
su(MRSTL)  
h(MRSTL)  
d(XTALI)  
3
Setup time, MRST low before XTAL1↑  
Hold time, MRST low after XTAL1↑  
ns  
4
ns  
5
Delay time, XTAL1 invalid to XTAL1 valid (stable)  
25  
ms  
V
DD  
(input)  
XTAL1  
(input)  
5
MRST*  
(input)  
3
4
2
1
Figure 23. Reset  
At initial power up, the TNETE2101 performs an internal reset. No external reset circuit is required, however,  
operation of the TNETE2101 is not specified for 50 ms after power up (V is stable).  
DD  
During operation, a full reset of the device can be performed by taking MRST terminal low for at least 50 µs.  
Correct operation of the devices is not assured for a duration of 50 ms after MRST terminal is deasserted high.  
100BASE-TX parameters  
PARAMETER  
DESCRIPTION  
level on transmit waveform (see Figure 24)  
out+  
MIN  
MAX  
UNIT  
V
V
out+  
V
0.95  
1.05  
V
out–  
V
out–  
level on transmit waveform (see Figure 24)  
–1.05 –0.95  
V
V
V
V
/V  
symmetry (see Figure 24)  
98  
0
102  
5
%
TX(sym)  
TX(os)  
r1(TX)  
r2(TX)  
f1(TX)  
out+ out–  
V
/V  
voltage overshoot (see Figure 24)  
%
out+ out–  
t
t
t
t
Rise time, t (0 –> V  
transition) (see Figure 25)  
transition) (see Figure 25)  
3
5
ns  
ns  
ns  
ns  
1
out+  
Rise time, t (0 –> V  
3
5
4
out–  
Fall time, t (V  
transition –> 0) (see Figure 25)  
transition –> 0) (see Figure 25)  
3
5
2
out+  
Fall time, t (V  
3
5
f2(TX)  
3
out–  
Maximum t  
Maximum t  
– Minimum t  
– Minimum t  
Maximum t  
Maximum t  
– Minimum t  
r2(Tx)  
– Minimum t  
f2(Tx)  
(see Figure 25),  
r1(Tx)  
f1(Tx)  
r1(Tx),  
f1(Tx),  
r2(Tx)  
f2(Tx)  
t
0
0
0.5  
0.5  
ns  
ns  
∆(TX)  
t
Duty-cycle distortion (see Figure 26)  
DCD(TX)  
34  
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TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
≤0.05 V  
out+  
V
out+  
0
≤0.05 V  
out–  
V
out–  
Figure 24. 100BASE-TX Transmit Amplitude  
t
3
t
1
V
out+  
90% V  
out+  
10% V  
10% V  
out+  
0
out–  
t
2
t
4
90% V  
out–  
V
out–  
NOTES: A.  
t
occurs at 10% of V  
.
.
.
.
1
2
3
4
out+  
out+  
B.  
C.  
D.  
t
t
t
occurs at 90% of V  
occurs at 10% of V  
occurs at 90% of V  
out–  
out–  
Figure 25. 100BASE-TX Transmit Rise/Fall  
V
out+  
0.5 ns  
50% V  
out+  
0.5 ns  
0
0.5 ns  
50% V  
V
out–  
0.5 ns  
out–  
Figure 26. 100BASE-TX Transmit Duty-Cycle Distortion  
35  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
receiver squelch parameters  
10BASE-T  
PARAMETER  
DESCRIPTION  
Positive-squelch receiver threshold voltage  
MIN  
MIN  
TYP  
250  
–250  
75  
MAX  
MAX  
UNIT  
mV  
V
thp  
V
thn  
V
thd  
Negative-squelch receiver threshold voltage  
Data receiver threshold voltage  
mV  
mV  
100BASE-TX  
PARAMETER  
DESCRIPTION  
Receiver differential voltage to maintain link  
TYP  
UNIT  
V
th  
200  
mV  
PARAMETER MEASUREMENT INFORMATION  
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V.  
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the  
level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8 V.  
For a low-to-high transition, the level at which the signal is no longer said to be low is 0.8 V and the level at which  
the signal is said to be high is 2 V, as shown in the following diagram.  
2 V (high)  
0.8 V (low)  
The rise and fall times are not specified, but are assumed to be those of standard TTL devices, which are typically  
1.5 ns.  
test measurement  
The test and load circuit shown in Figure 27 represents the programmable load of the tester-terminal electronics  
used to verify timing parameters of the TNETE2101 output signals.  
I
OL  
Test  
Point  
TTL  
Output  
Under  
Test  
V
LOAD  
C
L
I
OH  
TTL OUTPUT TEST LOAD  
Where: I  
I
=
=
=
Refer to I  
Refer to I  
1.5 V, typical dc-level verification or  
1.5 V, typical timing verification  
in recommended operating conditions.  
in recommended operating conditions.  
OL  
OH  
LOAD  
OL  
OH  
V
C
=
45 pF, typical load-circuit capacitance  
L
Figure 27. Test and Load Circuit  
36  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
MECHANICAL DATA  
PZ (S-PQFP-G100)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
75  
M
0,08  
51  
50  
76  
26  
100  
0,13 NOM  
1
25  
12,00 TYP  
Gage Plane  
14,20  
SQ  
13,80  
0,25  
16,20  
SQ  
0,05 MIN  
0°–7°  
15,80  
1,45  
1,35  
0,75  
0,45  
Seating Plane  
0,08  
1,60 MAX  
4040149/B 11/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
37  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jun-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LQFP  
LQFP  
LQFP  
LQFP  
Drawing  
TNETE2101APZ  
TNETE2101PZ  
TNETE2101PZ-R  
XTNETE2101PZ  
OBSOLETE  
OBSOLETE  
OBSOLETE  
OBSOLETE  
PZ  
100  
100  
100  
100  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
PZ  
PZ  
PZ  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  
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