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WV3DG72256V-AD2

型号：

WV3DG72256V-AD2

描述：

2GB - 2x128Mx72 SDRAM ，注册[ 2GB - 2x128Mx72 SDRAM, REGISTERED ]

品牌：

WEDC[ WHITE ELECTRONIC DESIGNS CORPORATION ]

页数：

9 页

PDF大小：

254 K

下载PDF手册
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY  
2GB – 2x128Mx72 SDRAM, REGISTERED  
FEATURES  
DESCRIPTION  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Burst Mode Operation  
The WV3DG72256V is a 2x128Mx72 synchronous DRAM  
module which consists of eighteen 256Mx4 stack SDRAM  
components (stacked from 128Mx4) in TSOP II package,  
two 18 bit Drive ICs for input control signal and one 2Kb  
EEPROM in an 8 pin TSSOP package for Serial Presence  
Detect which are mounted on a 168 pin DIMM multilayer  
FR4 Substrate.  
Auto and Self Refresh capability  
LVTTL compatible inputs and outputs  
Serial Presence Detect with EEPROM  
Fully synchronous: All signals are registered on the  
positive edge of the system clock  
ꢀ
Programmable Burst Lengths: 1, 2, 4, 8 or Full  
Page  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
ꢀ
ꢀ
ꢀ
3.3V 0.3V Power Supply  
Dual Rank  
NOTE: Consult factory for availability of:  
• RoHS compliant products  
• Vendor source control options  
• Industrial temperature option  
168 Pin DIMM JEDEC  
• PCB - AD2: 28.58mm (1.125”) TYP  
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)  
PIN NAMES  
A0 – A12  
BA0-1  
DQ0-63  
CB0-7  
CLK0  
Address Input (Multiplexed)  
Select Bank  
PIN FRONT PIN  
BACK  
DQM1  
CS0#  
NC  
PIN FRONT PIN  
BACK  
PIN  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
BACK  
DQM5  
CS1#  
RAS#  
VSS  
PIN  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
BACK  
DQ50  
DQ51  
VCC  
DQ52  
NC  
*VREF  
REGE  
VSS  
DQ53  
DQ54  
DQ55  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VCC  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
1
2
3
4
5
6
7
8
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
VSS  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
VCC  
DQ14  
DQ15  
CB0  
CB1  
VSS  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DQ18  
DQ19  
VCC  
DQ20  
NC  
*VREF  
*CKE1  
VSS  
DQ21  
DQ22  
DQ23  
VSS  
DQ24  
DQ25  
DQ26  
DQ27  
VCC  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
VSS  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
VSS  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
VCC  
DQ46  
DQ47  
CB4  
Data Input/Output  
Check Bit (Data-In/Data-Out)  
Clock Input  
VSS  
A0  
A2  
A4  
A6  
A8  
A10/AP  
BA1  
VCC  
A1  
A3  
A5  
A7  
A9  
BA0  
A11  
VCC  
NC  
CKE0  
Clock Enable Input  
CS0# - CS3# Chip Select Input  
RAS#  
CAS#  
WE#  
DQM0-7  
VCC  
VSS  
VREF  
REGE  
SDA  
SCL  
SA0-2  
NC  
Row Address Strobe  
Column Address Strobe  
Write Enable  
DQM  
Power Supply (3.3V)  
Ground  
Power Supply for Reference  
Register Enable  
Serial Data I/O  
Serial Clock  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VCC  
CLK0  
VSS  
A12  
VSS  
NC  
CKE0  
CS3#  
DQM6  
DQM7  
NC  
VCC  
NC  
NC  
CB6  
CB7  
VSS  
DQ48  
DQ49  
CS2#  
DQM2  
DQM3  
NC  
VCC  
NC  
Address in EEPROM  
No Connect  
* Pins not used in this module.  
CB5  
VSS  
NC  
NC  
VCC  
CAS#  
DQM4  
NC  
NC  
NC  
WP  
SDA  
SCL  
NC  
NC  
SA0  
SA1  
SA2  
VCC  
NC  
NC  
VCC  
WE#  
DQM0  
CB2  
CB3  
VSS  
DQ16  
DQ17  
VCC  
January 2006  
Rev. 0  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
FUNCTIONAL BLOCK DIAGRAM  
BCS1#, B  
BCS0#, B  
2
0
CKE0  
CKE0  
PCLK0  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
B
0
RAS#, B  
0
CAS#, B  
0
WE#, B  
0
BA0, B  
0
BA1  
Add  
Add  
Add  
Add  
B
0
A0~B  
0
A12  
DQM  
DQ0~3  
DQM  
DQ0~3  
DQM  
DQ0~3  
DQM  
DQ0~3  
BDQM0  
BDQM4  
DQ32~35  
DQ0~3  
10  
10  
10  
PCLK1  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
Add  
DQM  
Add  
DQM  
Add  
DQM  
Add  
DQM  
DQ0~7  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
DQ36~39  
10  
PCLK2  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
Add  
Add  
Add  
Add  
DQM  
DQ0~3  
DQM  
DQ0~3  
DQM  
DQ0~3  
DQM  
DQ0~3  
BDQM5  
DQ0~11  
DQ0~15  
CB0~3  
DQ40~43  
10  
PCLK3  
10  
10  
10  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
Add  
DQM  
Add  
DQM  
Add  
DQM  
Add  
DQM  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
DQ44~47  
DQ4~7  
10  
PCLK4  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
Add  
DQM  
Add  
DQM  
Add  
DQM  
Add  
DQM  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
10  
BCS3#, B CKE0  
BCS2, B  
1
3CKE0  
PCLK5  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
Add  
Add  
Add  
Add  
BDQM2  
DQM  
DQ0~3  
DQM  
DQ0~3  
BDQM6  
DQM  
DQ0~3  
DQM  
DQ0~3  
DQ48~51  
DQ16~19  
DQ20~23  
10  
10  
10  
PCLK6  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
Add  
DQM  
Add  
DQM  
Add  
DQM  
Add  
DQM  
DQ52~55  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
10  
PCLK7  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
Add  
Add  
Add  
Add  
BDQM3  
DQM  
DQM  
DQM  
DQM  
DQ24~27  
DQ56~59  
DQ60~63  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
10  
PCLK8  
10  
10  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
CLK#  
CS1, CKE  
CTL  
CLK#  
CS0, CKE  
CTL  
B
1
RAS#, B  
1
CAS#, B  
1
WE#, B  
1
BA0, B  
1
BA1  
A12  
Add  
DQM  
Add  
DQM  
Add  
DQM  
Add  
DQM  
B
1
A0~B  
1
DQ28~31  
DQ0~3  
DQ0~3  
DQ0~3  
DQ0~3  
V
SS  
V
CC  
PCLK0  
PCLK1  
PCLK2  
PCLK3  
PCLK4  
PCLK5  
PCLK6  
PCLK7  
PCLK8  
PCLK9  
IY0  
IY1  
IY2  
IY3  
IY4  
IY5  
IY6  
IY7  
IY8  
IY9  
B
1
0A3  
3
~B0  
1
A1100, B0  
1BA0  
A
3
~A10, BA0  
B A ~B  
A
, B BA0  
10  
CLK1,2,3  
V
CC  
12pF  
74ALVCF162835  
CDCF2510  
10k  
PCLK9  
REGE  
10  
LE  
OE#  
CLK0,2,3  
CLK  
FBIN  
FBOUT  
12pF  
A
11, A12, BA1  
B0  
1
A1111, B0  
1
A1122, B0  
BA1  
B A , B  
A , B BA1  
1
CS2#, CS3#  
CKE0  
*1  
BCS2, BCS3  
Cb  
B0CKE0,B 1CKE0  
B
CKE0, B CKE0  
74ALVCF162835  
Note  
D2QM2, 3, 63 , 7  
1. The actual values of Cb will depend upon the PLL chosen.  
DQM2, 3, 6, 7  
LE  
OE#  
Serial PD  
A0, A1, A2  
B A , B  
A
B
BA  
2
B0A0, B0  
1
A1,  
1
,B0BA2  
B1R0AS#, BC1AS#, B WE#  
SCL  
WP  
SDA  
B
1
0RAS#, BCAS#, B0  
1
WE#  
RAS#, CAS#, WE#  
A0  
A1  
A2  
74ALVCF162835  
BCS0, BCS1  
DQM0, 1, 4, 5  
CS0#, CS1#  
47K  
DQM0, 1, 4, 5  
SA0  
SA1  
SA2  
LE  
OE#  
January 2006  
Rev. 0  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
VIN, VOUT  
VCC, VCCQ  
TSTG  
Value  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
Units  
V
V
°C  
W
mA  
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
Power Dissipation  
Short Circuit Current  
-55 ~ +150  
PD  
IOS  
36  
50  
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ 70°  
Parameter  
Supply Voltage  
Symbol  
VCC  
VIH  
Min  
3.0  
2.0  
-0.3  
2.4  
—
Typ  
3.3  
3.0  
—
—
—
Max  
3.6  
VCCQ+0.3  
0.8  
—
0.4  
Unit  
V
V
Note  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
1
VIL  
V
V
V
μA  
2
VOH  
VOL  
ILI  
IOH= -2mA  
IOL= -2mA  
3
-10  
—
10  
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.  
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.  
3. Any input 0V ≤ VIN ≤ VCCQ  
Input leakage currents include Hi-Z output leakage for all bi-directional buffers  
with Tri-State outputs.  
CAPACITANCE  
TA = 25 °C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV  
Parameter  
Symbol  
CIN1  
Max  
15  
Unit  
pF  
Input Capacitance (A0-A12, BA0-BA1)  
Input Capacitance (RAS#, CAS#, WE#)  
CIN2  
15  
pF  
Input Capacitance (CKE0)  
Input Capacitance (CLK0)  
CIN3  
CIN4  
15  
20  
pF  
pF  
Input Capacitance (CS0# - CS3#)  
CIN5  
CIN6  
COUT  
15  
15  
22  
pF  
pF  
pF  
Input Capacitance (DQM0-DQM7)  
Data input/output capacitance (DQ0-DQ63), (CB0-BC7)  
January 2006  
Rev. 0  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
OPERATING CURRENT CHARACTERISTICS  
VCC = 3.3V, 0°C ≤ TA ≤ 70°C  
Versions  
Parameters  
Symbol  
Conditions  
Units  
Note  
133/100  
Burst Length = 1  
tRC ≥ tRC(min)  
IOL = 0mA  
Operating Current  
(One bank active)  
ICC1  
2,520  
mA  
1
ICC2P  
530  
130  
mA  
mA  
CKE ≤ VIL(max), tCC = 10ns  
Precharge Standby Current  
in Power Down Mode  
ICC2PS  
CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns  
Input signals are charged one time during 20  
ICC2N  
1,170  
410  
mA  
mA  
Precharge Standby Current  
in Non-Power Down Mode  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC= ∞  
Input signals are stable  
ICC2NS  
ICC3P  
670  
270  
mA  
mA  
CKE ≥ VIL(max), tCC = 10ns  
Active standby current in  
power-down mode  
ICC3PS  
CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns  
ICC3N  
1,530  
950  
mA  
mA  
Input signals are charged one time during 20ns  
Active standby in current non power-  
down mode  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
input signals are stable  
ICC3NS  
Io = mA  
Page burst  
ICC4  
2,610  
mA  
1
2
Operating current (Burst mode)  
4 Banks activated  
tCCD = 2CLK  
Refresh current  
ICC5  
ICC6  
4,590  
420  
mA  
mA  
tRC ≥ tRC(min)  
CKE ≤ 0.2V  
Self refresh current  
Notes: 1. Measured with outputs open.  
2. Refresh period is 64ms.  
January 2006  
Rev. 0  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
AC OPERATING TEST CONDITIONS  
VCC = 3.3V, 0°C ≤ TA ≤ 70°C  
Parameter  
AC Input level (VIN/VIL)  
Value  
2.4/0.4  
Units  
V
Input timing measurement reference level  
Input rise and fall time  
Output timing measurement reference level  
Output load condition  
1.4  
tr/tf = 1/1  
1.4  
V
ns  
V
See Fig. 2  
3.3V  
VTT=1.4V  
1220  
50  
V
OH (DC)=2.4V, IOH=-2mA  
OL (DC)=2.4V, IOL=-2mA  
Output  
870  
Output  
Z0 = 50  
V
50pF  
50pF  
(Fig. 1) DC output load circuit  
(Fig. 2) AC output load circuit  
AC OPERATING TEST CONDITIONS  
Value  
133/100  
Parameter  
Symbol  
Units  
Notes  
Row active to row active delay  
RAS# to CAS# delay  
Row Precharge time  
tRRD(MIN)  
tRCD(MIN)  
tRP(MIN)  
tRAS(MIN)  
tRAS(MAX)  
15  
ns  
ns  
ns  
ns  
µs  
1
1
1
1
20  
20  
45  
100  
Row active time  
Row cycle time  
tRC(MIN)  
tRDL(MIN)  
tDAL(MIN)  
tCDL(MIN)  
tBDL(MIN)  
tCCD(MIN)  
65  
2
ns  
CLK  
—
CLK  
CLK  
CLK  
CLK  
ea  
1
2
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
2 CLK + tRP  
1
1
1
2
1
1
2
2
3
4
Col. address to col. address delay  
CAS Latency = 3  
Cas Latency = 2  
Number of valid output data  
Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
January 2006  
Rev. 0  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
OPERATING AC PARAMETER  
133/100  
Parameter  
Symbol  
Units  
ns  
Notes  
Min  
7.5  
–
Max  
CAS latency = 3  
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
CAS latency = 3  
CAS latency = 2  
CLK cycle time  
tCC  
1,000  
1
1, 2  
2
5.4  
–
CLK to valid output delay  
Output data hold time  
tSAC  
ns  
3
–
tOH  
ns  
CLK high pulse width  
CLK low pulse width  
Input setup time  
Input hold time  
CLK to output in Low-z  
tCH  
tCL  
tSS  
tSH  
tSLZ  
2.5  
2.5  
1.5  
0.8  
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
CAS latency = 3  
CAS latency = 2  
5.4  
–
CLK to output in Hi-z  
tHZ  
ns  
Notes: 1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time  
compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter.  
January 2006  
Rev. 0  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
ORDERING INFORMATION FOR AD2  
Part Number  
Clock Speed  
100MHz  
CAS Latency  
CL=2  
Height*  
WV3DG72256V10AD2xx  
WV3DG72256V7AD2xx  
WV3DG72256V75AD2xx  
28.58 (1.25”) TYP  
28.58 (1.25”) TYP  
28.58 (1.25”) TYP  
133MHz  
CL=2  
133MHz  
CL=3  
NOTES:  
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)  
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be  
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR AD2  
133.350  
5.250  
1.372  
0.054  
127.350  
5.014  
3.00  
0.118  
2.000  
0.079  
0.157 0.004  
(4.000 0.100)  
?
ꢀ
118DIA 0.004  
3.000DIA 0.100  
6.350  
0.250  
6.350  
0.250  
8.890  
0.350  
36.830  
1.450  
54.64  
2.150  
11.430  
(0.450)  
115.57  
4.550  
8.86 Max  
(0.270 Max)  
1.270 0.10  
0.050 0.0039  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
January 2006  
Rev. 0  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
PART NUMBERING GUIDE  
WV 3 D G 72 256 V xx AD2 I- x G  
WEDC  
MEMORY  
SDRAM  
GOLD  
BUS WIDTH  
DEPTH  
3.3 VOLTS  
CLOCK SPEED (MHz)  
10 = 100MHz @ CL = 2  
7 = 133MHz @ CL = 2  
75 = 133MHz @ CL = 3  
PACKAGE 168 PIN DIMM  
AD2: 28.58mm (1.125”)  
INDUSTRIAL TEMP  
COMPONENT VENDOR NAME  
(M = Micron)  
(S = Samsung)  
G = ROHS COMPLIANT  
January 2006  
Rev. 0  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG72256V-AD2  
White Electronic Designs  
PRELIMINARY*  
Document Title  
2GB- 2x128Mx72 SDRAM, REGISTERED  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Created Data sheet  
January 2006  
Advanced  
January 2006  
Rev. 0  
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
厂商 型号 描述 页数 下载

WEDC

 		WV3DG64127V-D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V10D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V75D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V75D2F [ DRAM, ] 8 页

WEDC

 		WV3DG64127V75D2G [ 暂无描述 ] 8 页

WEDC

 		WV3DG64127V7D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V7D2F [ DRAM, ] 8 页

WEDC

 		WV3DG64127V7D2G [ 暂无描述 ] 8 页

MICROSEMI

 		WV3DG72256V10AD2MG [ Synchronous DRAM Module, 256MX72, 5.4ns, CMOS, ROHS COMPLIANT, DIMM-168 ] 9 页

MICROSEMI

 		WV3DG72256V10AD2SG [ Synchronous DRAM Module, 256MX72, 5.4ns, CMOS, ROHS COMPLIANT, DIMM-168 ] 9 页

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