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OZ962

型号：

OZ962

描述：

高效率逆变控制器[ High-Efficiency Inverter Controller ]

品牌：

ETC[ ETC ]

页数：

6 页

PDF大小：

54 K

下载PDF手册
OZ962  
High-Efficiency Inverter Controller  
GENERAL DESCRIPTION  
FEATURES  
The OZ962 is a unique high-efficiency, CCFL  
backlight controller. It generates symmetrical,  
near sinusoidal output voltage and current  
waveforms for driving a CCFL backlight. The  
OZ962 operates in a single, constant frequency,  
pulse-width-modulation (PWM) mode. Typical  
operating frequency ranges between 30 KHz to  
100 KHz, depending on the CCFL and the  
transformer’s characteristics.  
·
·
·
·
Single-stage power conversion, input voltage  
range of 5V to 18V  
Reduces the number of components and board  
size by 30% compared with conventional design  
Supports both floating and grounded secondary  
designs  
90% efficiency vs. typical 75% efficiency of  
conventional designs  
Internal open-lamp and short-circuit protections  
Wide dimming range  
Supports synchronization among multiple  
inverter modules  
Reliable 2-winding transformer design,  
eliminates arcing problems  
Constant frequency, symmetrical, sinusoidal  
drive  
·
·
·
Operating in a PWM push-pull manner, the  
transformer in the OZ962 backlight inverter  
requires only one primary winding and one  
secondary winding, with the secondary winding  
requiring no fold-back treatment.  
·
·
The OZ962 is available in both 16-pin SOIC and  
TSSOP packages. It is specified over the  
o
o
commercial temperature range: 0 C to +70 C.  
ORDERING INFORMATION  
OZ962R - 16 lead TSSOP  
OZ962G - 16-pin plastic SOP  
TYPICAL APPLICATION CIRCUIT  
F1  
1A Fast Fuse  
VDD (+12V)  
ENA  
+
-
C1  
22u  
25V  
R10  
100  
GND  
CN1  
R5  
10K  
C7  
U1  
3
U2  
Q2  
1
16  
REF  
VDD  
OZ962G  
*
*
C8  
68p  
3KV  
2
3
4
5
6
7
8
15  
14  
33T  
2200T  
0.22u  
RT  
CT  
OVP  
4
2
R9  
R1  
C6 2.2u  
50V  
3.5W  
220K 200K C9  
5,6  
-
NC  
.01u  
R7  
100K  
C5  
+
13  
12  
11  
10  
9
SI4559EY  
SCP  
ADJ  
FB  
CLK  
ENA  
NDR  
PDR  
SST  
R14  
220p  
7,8  
R2  
10K  
1.0K  
R6  
30  
C2  
C3  
Q1  
R3  
5.1K  
0.1u  
CMP  
GND  
1
330p  
C4  
0.1u  
R8  
0.5  
R11  
1M  
R4  
15K  
R12  
750  
R13  
100  
Figure 1. Typical Floating Secondary Application  
03/01/00  
ÓCopyright 1999 by O2Micro  
OZ962-SF-2.7  
All Rights Reserved  
Page 1  
U.S. Patent #5,619,402  
OZ962  
FUNCTIONAL BLOCK DIAGRAM  
Ct(14) Rt(15)  
OVP(2)  
Under Voltage  
Lockout  
OVP Voltage  
Generator  
RAMP  
OSC  
OVP  
NDR(11)  
PDR(10)  
Break  
Before  
Make  
OVP=Vref-(Vdd - 1)(12.5/150)  
D=1.1(OVP)/2.5 - 0.2  
VDD(16)  
N-Clamp  
Band Gap  
Reference  
Vref (2.5V)  
OSC  
P-Clamp  
1/2F  
REF(1)  
S
R
Q
Q
RAMP  
Error  
Amp.  
CLK(13)  
Ve  
ADJ(5)  
FB(6)  
40k  
Ve=Vcmp-2*(Vcmp-SST-Vgs)  
Vcmp  
60k  
3V  
30k  
SST  
1k  
9k  
CMP(7)  
Dmax  
Clamp  
Vdd  
OVP  
3mA  
10mA  
ENA(12)  
SST  
SST(9)  
OVP  
OVP  
SCP  
UVL  
shut  
2.0v  
SCP & OVP inhibited during  
start-up  
2mA  
GND(8)  
down  
latch  
ADJ  
SCP(4)  
Note:  
OVP – Over Voltage Protection  
SCP – Short-Circuit Protection  
UVL – Under Voltage Lockout  
Figure 2. Functional Block Diagram  
OZ962-SF-2.7  
Page 2  
OZ962  
PIN DESCRIPTION  
Names  
REF  
OVP  
Pin No.  
I/O  
O
I
Description  
Reference voltage output. Nominal voltage is 2.5 V.  
Over-voltage protection setting. Refer to formula for OVP in block diagram  
on page 2 of this document.  
1
2
NC  
SCP  
ADJ  
FB  
CMP  
GND  
SST  
3
4
5
6
7
8
9
-
I
I
I
O
No connection.  
Short-circuit protection input.  
Reference voltage input for dimming control.  
Current sense feedback.  
Compensation for the current sense feedback.  
GND  
I
Ground.  
Tsst ~ 0.2 Csst (Vdd - 5), where Csst is the soft start capacitor value in mF  
and Tsst value is in ms.  
PDR  
NDR  
ENA  
CLK  
CT  
RT  
VDD  
10  
11  
12  
13  
14  
15  
16  
O
O
I
Gate drive output for the P-MOSFET.  
Gate drive output for the N-MOSFET.  
Enable input, active high (Vth is about 1.7 V).  
Open-drain clock output.  
Timing capacitor. CT and RT set the clock frequency.  
Timing resistor.  
O
I/O  
I/O  
PWR  
Supply voltage input.  
ABSOLUTE MAXIMUM RATINGS  
VDD  
GND  
Logic inputs  
Power dissipation  
18 V  
+/- 0.3 V  
Operating temp.  
Operating junction temp.  
Storage temp.  
0 oC to 70 oC  
150 oC  
-0.3 V to VDD+0.3 V  
-55 to 150 oC  
800 mW at 25 oC  
RECOMMENDED OPERATING RANGE  
VDD  
Fosc  
Rosc  
5V to 18V  
30 KHz to 100 KHz  
50 k to 150 k  
OZ962-SF-2.7  
Page 3  
OZ962  
FUNCTIONAL SPECIFICATIONS  
Parameter  
Symbol  
Test Conditions  
Limits  
Unit  
5 V < VDD < 15 V  
Min  
Typ  
Max  
Reference Voltage  
Nominal voltage  
Vref  
Iload = 0.25 mA,  
2.37  
2.50  
2.63  
V
VDD = 5 V  
Line regulation  
Load regulation  
Oscillator  
-
-
8
1
-
-
mV/V  
Iload = 0.2 mA to 1.0 mA  
mV/mA  
Initial accuracy  
Ramp peak  
fosc  
Ct = 220 pF, Rt = 120 k  
TA = 0 oC to 70 oC  
48  
2.45  
0.40  
-
53  
2.55  
0.45  
-
58  
KHz  
2.65  
0.50  
200  
V
Ramp valley  
V
Temp. stability  
Error Amplifier  
Input bias current  
Input offset voltage  
Input voltage range  
ppm/ oC  
VADJ=VFB=2.0 V  
VFB = 4.0 V  
-
-
25  
5
500  
10  
nA  
mV  
V
0
-
VDD-  
1.5  
Open loop voltage gain  
Unity gain bandwidth  
50  
1
60  
1.5  
60  
-
-
-
dB  
MHz  
dB  
Power supply rejection  
Under-Voltage Lockout  
Positive-going threshold voltage  
Negative-going threshold voltage  
Supply  
50  
-
3.8  
3.6  
4
-
V
V
3.4  
Supply current - Enable Low  
Adj, CT = Open  
IOFF  
VDD = 5.0 V  
VDD = 15 V  
-
-
25  
25  
120  
120  
mA  
mA  
Supply current - Enable Low  
Adj, CT = Open  
IOFF  
Supply current - Enable High  
Supply current - Enable High  
NDR output  
ION  
ION  
VDD = 5.0 V  
VDD = 15 V  
-
-
0.6  
0.6  
1.5  
1.5  
mA  
mA  
Output high voltage  
VOH  
Isink = 10 mA,  
VDD < 7.8 V  
VDD >7.8 V  
VDD-  
0.3  
VDD-  
0.5  
-
V
7.0  
8.0  
0.3  
50  
9.0  
0.8  
80  
V
Output low voltage  
Output resistance  
VOL  
Isource = 10 mA  
VDD = 5.0 V  
-
-
V
ROUT  
W
PDR output  
Output high voltage  
VOH  
VOL  
Isink = 10 mA  
VDD-  
0.6  
VDD-  
0.3  
-
V
V
Output low voltage  
Isource = 10 mA,  
VDD < 7.8 V  
0.4  
0.5  
0.8  
VDD > 7.8 V  
-
-
VDD-  
6.0  
VDD-  
4.0  
Output resistance  
ROUT  
VDD = 5.0 V  
50  
80  
W
Break-Before-Make  
Qn off to Qp on delay  
Qp off to Qn on delay  
THL  
TLH  
200  
220  
240  
260  
280  
300  
ns  
ns  
OZ962-SF-2.7  
Page 4  
OZ962  
PACKAGE INFORMATION  
A2 A1  
A
TSSOP-16  
PACKAGE  
E
E1  
1
q
2
D
R1  
Gauge Plane  
R
b
e
b
q
1
L
c
c1  
q
3
L1  
b1  
DIM  
INCHES  
MILLIMETERS  
MIN  
-
0.002  
0.031  
0.020  
-
MAX  
0.043  
0.006  
0.041  
0.030  
-
MIN  
-
MAX  
1.20  
0.15  
1.05  
0.75  
5.10  
4.50  
A
A1  
A2  
L
0.05  
0.80  
0.45  
4.90  
4.30  
D
E1  
E
0.169  
0.177  
0.252BSC  
6.40BSC  
R
R1  
b
b1  
c
c1  
L1  
e
0.004  
0.004  
0.007  
0.007  
0.004  
0.004  
0.039REF  
0.026BSC  
0° 8°  
-
-
0.09  
0.09  
0.19  
0.19  
0.09  
0.09  
1.0REF  
0.65BSC  
0° 8°  
-
-
0.012  
0.010  
0.008  
0.006  
0.30  
0.25  
0.20  
0.16  
q1  
q2  
q3  
12°REF  
12°REF  
12°REF  
12°REF  
OZ962-SF-2.7  
Page 5  
OZ962  
DIM  
INCHES  
MIN MAX  
0.0532 0.0688  
0.0040 0.0098  
MILLIMETERS  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
A
A1  
B
C
D
E
0.013  
0.020  
SOP-16  
PACKAGE  
0.0075 0.0098  
0.3859 0.3937  
0.1497 0.1574  
0.050 BCS.  
E H  
e
1.27 BCS.  
H
0.2284  
0.244  
0
0.050  
5.80  
6.20  
1
L
0.016  
0.40  
1.27  
0°  
8°  
0°  
8°  
a
D
C
a
A
L
B
e
A1  
OZ962-SF-2.7  
Page 6  
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