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QT1100A-ISG

型号：

QT1100A-ISG

描述：

10键的QTouch传感器IC[ 10 KEY QTOUCH SENSOR IC ]

品牌：

QUANTUM[ QUANTUM RESEARCH GROUP ]

页数：

42 页

PDF大小：

562 K

下载PDF手册

QT1100A-ISG

ADVANCED

NFORMATION

10 KEY QTOUCH™ SENSOR IC

10 independent touch sensing fields

100% autocal for life - no adjustments required

SPI and UART serial interfaces

Scanport output - simulates a membrane keypad

Simple external per channel passive circuit

User-defined setups of operating parameters

3.3V~5.0V single supply operation

AKS™ Adjacent Key Suppression for tight key layouts

Sleep mode for low power operation

Spread spectrum modulated bursts - superior noise rejection

Sync pin for superior mains frequency noise rejection

FMEA compliant design features - self detects faults

Lower per key cost than many mechanical switches

Lead-free package

APPLICATIONS

Actual Size

PC peripherals

Appliance controls

Pointing devices

Gaming machines

Television controls

Instrument panels

QT1100A charge-transfer (“QT”) QTouch ICs are self-contained digital controllers capable of detecting near-proximity or touch on up to

10 electrodes. This device allows each electrode to project an independent sense field through glass or plastic. These devices require

only a few inexpensive passive components per sensing channel. The devices are designed specifically for human interfaces, such as

control panels, appliances, gaming devices, lighting controls, or anywhere a mechanical switch may be found.

Each key channel operates independently, and can be tuned to a unique sensitivity level by simply changing setup values in an

EEPROM or via a serial interface. An external EEPROM can store the setups permanently for standalone applications, for example

when using the scanport, or, the EEPROM can be omitted if the serial port is used to send setup information after each power-up.

Included is patent pending AKS™ Adjacent Key Suppression which suppresses touch from weakly responding keys and allows only a

dominant key to detect, to solve the problem of large fingers on tightly spaced keys. Modulated burst technology provides superior

noise rejection. ‘Fast-DI’ operation works to further suppress false activations due to noise.

These devices also have a Sync pin to suppress some forms of external interference. A Sleep mode is also available for very low

power standby operation.

The QT1100A is designed specifically to assist in creating FMEA compliant designs, allowing it to be used in applications such as

appliance controls.

Using the charge transfer principle, these devices deliver a level of performance which is clearly superior to older technologies yet

extremely cost-effective.

AVAILABLE OPTIONS

T_A

SSOP-48

LEAD-FREE

-40ºC to +85ºC

QT1100A-ISG

Yes

QT1100A-ISG R3.02/1105

Contents

3.5.3 Detect Integrator for Key ‘k’ - 0x6k

. . . . . . . . . . . . . . . . 19

3.5.4 Status for Key ‘k’ - 0x8k

1 Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 1.1 Scanport / UART Pinlist

Table 1.2 Standalone Pinlist

Table 1.3 Standalone Pinlist

Table 1.4 SPI Pinlist

Table 1.5 Pin Descriptions

Figure 1.1 SPI Connection Diagram

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . 19

. . . . . . . . . . . . . . . . . . . . . 20

3.5.5 Report 1st Key - 0xC0

3.5.6 Report All Keys - 0xC1

3.5.7 Device Status - 0xC2

3.5.8 EEPROM CRC - 0xC3

3.5.9 RAM CRC - 0xC4

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . 20

3.5.10 Error Flags for Group - 0xC5

3.5.11 Internal Code - 0xC6

Figure 1.2 UART / Scanport Connection Diagram

Figure 1.3 Scanport Only Connection Diagram+

. . . . . . . . . . 10

. . . . . . . . . . . 11

. . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . . . . . 21

3.5.12 Return Last Command - 0xC7

3.5.13 Dump Setups Block - 0xC8

3.5.14 Quick Report First Key - 0xC9

3.6 Command Sequencing

Figure 3-1 Suggested Serial Flow

Table 3-1 Control Commands

Table 3-2 Status Commands

2 Device Control & Wiring

. . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . 21

2.1 Oscillator

2.2 Spread Spectrum Modulation

2.3 Cs Sample Capacitors

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . 21

2.4 Sensitivity

2.5 Sensitivity Balance

2.6 Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . 22

. . . . . . . . . . . . . . . . . . . . 23

. . . . . . . . . . . . . . . . . . . . 24

. . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 PCB Layout and Construction

2.8 ESD Protection

2.9 Noise Issues

4 Setup Block Functions

. . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 NTHR - Negative Threshold Bits

4.2 NHYS - Negative Hysteresis Bits

4.3 NDCR / PDCR - Drift Comp Bits

4.4 NRD - Negative Recal Delay Bits

4.5 PRD - Positive Recal Delay Bits

. . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . 26

. . . . . . . . . . . . . . . . . 26

2.9.1 LED Traces and Other Switching Signals

. . . . . . . . . . . . . 13

2.9.2 External Fields

. . . . . . . . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 Start-up Time

2.11 Operating Parameter Setups

2.12 Standalone Operation, No EEPROM

2.13 EEPROM Functionality

2.14 Scanport Interface

2.15 Start-up Sequencing

4.6 AKS - Adjacent Key Suppression Bits

4.7 EK - Error Key Control Bits

4.8 K2L / LEDP / KEYO Control Bits

4.9 NDIL, FDIL - Detect Integrator Bits

4.10 PTHR - Positive Threshold Bits

4.11 PHYS - Positive Hysteresis Bits

4.12 SE, SYNC Control Bits

. . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . 26

. . . . . . . . . . . . . . 14

. . . . . . . . . . . . . . . . . . . 27

. . . . . . . . . . . . . . . . . 27

. . . . . . . . . . . . . . . . . . . . . 14

. . . . . . . . . . . . . . . . . . . . . . . 14

. . . . . . . . . . . . . . . . . . . . . . 14

. . . . . . . . . . . . . . . . 27

. . . . . . . . . . . . . . . . . 28

. . . . . . . . . . . . . . . . 28

2.16 Error Detection and Reporting

. . . . . . . . . . . . . . . . . 14

3 Serial Operation

. . . . . . . . . . . . . . . . . . . . . . . . . 15

. . . . . . . . . . . . . . . . . . . . . 28

3.1 UART Interface

4.13 LBLL - Lower Burst Length Limit

. . . . . . . . . . . . . . . . 29

. . . . . . . . . . . . . . . . . . 29

3.1.1 TX Pin

4.14 BS - Burst Spacing Control Bits

4.15 BR - Baud Rate Control Bits

4.16 HCRC - Host CRC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 Sleep/Wake Operation in UART Mode

. . . . . . . . . . . . . . 15

3.1.3 CRDY Operation in UART Mode

. . . . . . . . . . . . . . . . 15

. . . . . . . . . . . . . . . . . . . . . . . 30

3.2 SPI Operation

Table 4-1 Serial / EEPROM Setups Block

. . . . . . . . . . . . . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . 31

. . . . . . . . . . . . . . . . . . . . . . . . . 32

. . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.1 Multi-Drop SPI Capability

4.17 Timing Tables

5 - Specifications

. . . . . . . . . . . . . . . . . . . . 16

3.2.2 Sleep/Wake Operation in SPI Mode

. . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . . . . 16

3.2.3 CRDY Operation in SPI Mode

3.3 Communication Error Handling

3.4 Control Commands

5.1 Absolute Maximum Specifications

5.2 Recommended Operating Conditions

5.3 AC Specifications

. . . . . . . . . . . . . . . . 36

. . . . . . . . . . . . . . 36

. . . . . . . . . . . . . . . . . . . . . . . 17

. . . . . . . . . . . . . . . . . . . . . 17

. . . . . . . . . . . . . . . . . . . . . . . . 36

. . . . . . . . . . . . . . . . . . . . . . . 37

. . . . . . . . . . . . . . . . . . . . . . 38

3.4.1 Null Command - 0x00

5.4 DC Specifications

5.5 Burst / Sync Timing

5.6 SPI Timing Diagram

5.7 QT1100A Timing Parameters - with Fosc = 12MHz

5.8 Current vs Vdd

3.4.2 Enter Setups Load Mode - 0x01

3.4.3 Enter Run Mode - 0x02

. . . . . . . . . . . . . . . . . 17

. . . . . . . . . . . . . . . . . . . . 18

. . . . . . . . . . . . . . . . . . . . . 18

. . . . . . . . . . . . . . . . . . . . . . 18

3.4.4 Enter Cal Mode - 0x03

3.4.5 Force Reset - 0x04

3.4.6 Sleep - 0x05

. . . . . . . 39

. . . . . . . . . . . . . . . . . . . . . . . . . 40

. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.9 Mechanical

5.10 Marking

. . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4.7 Cal Key ‘k’ - 0x1k

. . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Status Commands

3.5.1 Signal for 1 Key - 0x2k

6 Appendix A - 8-Bit CRC C Algorithm

. . . . . . . . . . . . . . . . . . . . . . . 19

. . . . . . . . . . . . . 41

. . . . . . . . . . . . . . . . . . . . . 19

3.5.2 Reference for Key ‘k’ - 0x4k

. . . . . . . . . . . . . . . . . . 19

QT1100A-ISG R3.02/1105

Detection confirmation occurs by means of a ‘detect

integrator’ mechanism that requires multiple confirmations of

detection over a number of key bursts. The bursts operate at

alternating frequencies, so that external fields will have a

minimal effect on key operation. This spread-spectrum

mode of operation also reduces RF noise emissions.

1 Overview

The QT1100A is a 10 touch-key sensor IC based on

Quantum’s patented charge-transfer principles for robust

operation and ease of design. This device has many

advanced features which provide for reliable, trouble-free

operation over the life of the product. It can operate in either

a standalone mode or under host control via a serial

interface. Output options include UART and SPI serial types

and parallel scanport. In any interface mode, a low-cost

optional EEPROM can be used to determine the device

configuration using a stored Setup block.

The device also features the ability to acquire and lock onto

touch signals very rapidly, greatly improving response time

through the use of the ‘fast detect integration’ or ‘Fast-DI’

feature.

Sync Mode: The QT1100A features a Sync mode to allow

the device to slave to an external signal source, such as a

mains signal (50/60Hz), to limit interference effects. This is

performed using a special Sync pin.

FMEA self-testing: This part has been designed specifically

for demanding appliance applications requiring FMEA

certification. The part has many advanced features that

check for and report failures, to allow the designer to create

a safer product. It also features two robust serial interfaces

with sophisticated CRC error checking to permit validation of

commands and responses in real time.

Low Power Sleep Mode: The device features a low power

Sleep mode for microamp levels of current drain when not in

use. The part can be put into sleep for a certain percentage

of the time, so that it can still respond to touch but with lower

levels of current drain.

Burst mode: The device operates in ‘burst mode’. Each key

is acquired using a burst of charge-transfer sensing pulses

whose count can vary tremendously depending on the value

of the reference capacitor Cs and the load capacitance Cx.

The keys (also called ‘channels’) are acquired time

sequentially within fixed timeslots whose width can be

controlled by user-defined Setups.

AKS™ Adjacent Key Suppression works to prevent

multiple keys responding to a single touch, a common

complaint of capacitive touch panels. This system operates

by comparing signal strengths from keys within a defined

group to suppress touch detections from those with a weaker

signal change than the dominant key. The QT1100A allows

any AKS grouping of two or more keys, under user control.

Self-calibration: On power-up, all keys are self-calibrated

within a few hundred milliseconds to provide reliable

operation under almost any set of conditions.

Unique to this device is the ability for the designer to treat

each key as an individual sensor for configuration purposes.

Each key can be programmed separately for sensitivity, drift

compensation, recalibration timeouts, adjacent key

suppression, and the like.

The device is designed to support FMEA-qualified

applications using a variety of checks and redundancies.

Among other checks the component uses CRC codes in all

critical communication transfers, and can also output error

condition codes via redundant signaling paths.

Auto-recalibration: The device can time out and recalibrate

each key independently after a fixed interval of continuous

detection, so that the keys can never become ‘stuck on’ due

to foreign objects or sudden influences. After recalibration

the key will continue to function normally.

Drift compensation operates to correct the reference level

of each key slowly but automatically over time, to suppress

false detections caused by changes such as temperature,

humidity, dirt and other environmental effects.

Spread Spectrum operation: The bursts operate over a

spread of frequencies, so that external fields will have

minimal effect on key operation and emissions are very

weak. Spread-spectrum operation works with the ‘detect

integrator’ (DI) mechanism to dramatically reduce the

probability of false detection due to noise.

QT1100A-ISG R3.02/1105

Table 1.1 Scanport / UART Pinlist

With or without EEPROM; either UART or Scanport or both may be used

Name

Type

Function

Notes

If Unused

SNS3

SNS3K

SNS4

SNS4K

SNS5

SNS5K

SNS6

SNS6K

SNS7

SNS7K

n/c

I/O

Sense pin

Unused

To CS3

Open

Vss or open

Open

To CS3 + Key

To CS4

To CS4 + Key

Vss or open

Open

To CS5

To CS5 + Key

Vss or open

Open

To CS6

To CS6 + Key

Vss or open

Open

To CS7

To CS7 + Key

Vss or open

n/c

Unused

SNS8

SNS8K

SNS9

SNS9K

Vss

I/O

Pwr

Sense pin

Ground

To CS8

Open

To CS8 + Key

Vss or open

Open

To CS9

To CS9 + Key

Vss or open

CKEE

DOEE

DIEE

EEPROM

UART

Clock to EEPROM

Data out to EEPROM

Data in from EEPROM

Serial to host; If used, use pull-up-R

Serial in / Wake from sleep

1 = Comms ready; use pull-up-R

EEPROM chip select; use pull-down-R

Open

I/O, OD

Open

Vdd

Vss

RX/WAKE

CRDY

CSEE

UART, Wakeup

Handshake

EEPROM

Vdd

10K ~ 220K to Vdd

Open

SCANO_0

SCANO_1

SCANO_2

SCANO_3

SCANI_2

SCANI_1

SCANI_0

CMODE

SYNC

Scanport out

Scanport in

Comms select

Sync in

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Vss

See Table 2.1

Vss

See Table 2.1

Vss

To Vss

I/O

Always use pull-up R

20K ~ 220K to Vdd

LED/STAT

RST

LED & Status

Reset input

Power

Open

Active low

Vdd

Pwr

+3.3 ~ +5V

OSC1

Resonator

Unused

12MHz - Can also be ext clock in

OSC2

Open

n/c

Unused

n/c

Unused

n/c

Unused

SNS0

I/O

Sense pin

To CS0 + Key

To CS0

To CS1 + Key

To CS1

To CS2 + Key

To CS2

Open

SNS0K

SNS1

Vss or open

Open

SNS1K

SNS2

Vss or open

Open

SNS2K

Vss or open

CMOS input

CMOS I/O

I/O

CMOS output (push-pull)

CMOS open drain I/O

Power / ground

Pwr

QT1100A-ISG R3.02/1105

Table 1.2 Standalone Pinlist

Scanport, with EEPROM; no serial interface

Name

Type

Function

Notes

If Unused

SNS3

SNS3K

SNS4

SNS4K

SNS5

SNS5K

SNS6

SNS6K

SNS7

SNS7K

n/c

I/O

Sense pin

Unused

To CS3

To CS3 + Key

To CS4

Open

Vss or open

Open

To CS4 + Key

To CS5

Vss or open

Open

To CS5 + Key

To CS6

Vss or open

Open

To CS6 + Key

To CS7

Vss or open

Open

To CS7 + Key

Vss or open

n/c

Unused

SNS8

SNS8K

SNS9

SNS9K

Vss

I/O

Pwr

Sense pin

Ground

To CS8

Open

To CS8 + Key

To CS9

Vss or open

Open

To CS9 + Key

Vss or open

CKEE

DOEE

DIEE

EEPROM

UART

Clock to EEPROM

Data out to EEPROM

Data in from EEPROM

To Vss

I/O, OD

RX/WAKE

CRDY

CSEE

UART, Wakeup

Handshake

EEPROM

To Vdd

Leave open

EEPROM chip select

SCANO_0

SCANO_1

SCANO_2

SCANO_3

SCANI_2

SCANI_1

SCANI_0

CMODE

SYNC

Scanport out

Scanport in

Comms select

Sync in

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Vss

See Table 2.1

Vss

See Table 2.1

Vss

To Vss

I/O

Always use pull-up R

20K ~ 220K to Vdd

LED/STAT

RST

LED & Status

Reset input

Power

Open

Active low

Vdd

Pwr

+3.3 ~ +5V

OSC1

Resonator

Unused

12MHz - Can also be ext clock in

OSC2

Open

n/c

Unused

n/c

Unused

n/c

Unused

SNS0

I/O

Sense pin

To CS0 + Key

To CS0

To CS1 + Key

To CS1

To CS2 + Key

To CS2

Open

SNS0K

SNS1

Vss or open

Open

SNS1K

SNS2

Vss or open

Open

SNS2K

Vss or open

CMOS input

CMOS I/O

I/O

CMOS output (push-pull)

CMOS open drain I/O

Power / ground

Pwr

QT1100A-ISG R3.02/1105

Table 1.3 Standalone Pinlist

Scanport, without EEPROM; no serial interface

Name

Type

Function

Notes

If Unused

SNS3

SNS3K

SNS4

SNS4K

SNS5

SNS5K

SNS6

SNS6K

SNS7

SNS7K

n/c

I/O

Sense pin

Unused

To CS3

To CS3 + Key

To CS4

Open

Vss or open

Open

To CS4 + Key

To CS5

Vss or open

Open

To CS5 + Key

To CS6

Vss or open

Open

To CS6 + Key

To CS7

Vss or open

Open

To CS7 + Key

Vss or open

n/c

Unused

SNS8

SNS8K

SNS9

SNS9K

Vss

I/O

Pwr

Sense pin

Ground

To CS8

Open

To CS8 + Key

To CS9

Vss or open

Open

To CS9 + Key

Vss or open

CKEE

DOEE

DIEE

EEPROM

UART

Open

I/O, OD

Connect DOEE, DIEE together

To Vss

To Vdd

Leave open

Open

RX/WAKE

CRDY

CSEE

UART, Wakeup

Handshake

EEPROM

SCANO_0

SCANO_1

SCANO_2

SCANO_3

SCANI_2

SCANI_1

SCANI_0

CMODE

SYNC

Scanport out

Scanport in

Comms select

Sync in

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Open

See Table 2.1

Vss

See Table 2.1

Vss

See Table 2.1

Vss

To Vss

I/O

Always use pull-up R

20K ~ 220K to Vdd

LED/STAT

RST

LED & Status

Reset input

Power

Open

Active low

Vdd

Pwr

+3.3 ~ +5V

OSC1

Resonator

Unused

12MHz - Can also be ext clock in

OSC2

Open

n/c

Unused

n/c

Unused

n/c

Unused

SNS0

I/O

Sense pin

To CS0 + Key

To CS0

To CS1 + Key

To CS1

To CS2 + Key

To CS2

Open

SNS0K

SNS1

Vss or open

Open

SNS1K

SNS2

Vss or open

Open

SNS2K

Vss or open

CMOS input

CMOS I/O

I/O

CMOS output (push-pull)

CMOS open drain I/O

Power / ground

Pwr

QT1100A-ISG R3.02/1105

Table 1.4 SPI Pinlist

With or without EEPROM

Name

Type

Function

Notes

If Unused

SNS3

SNS3K

SNS4

SNS4K

SNS5

SNS5K

SNS6

SNS6K

SNS7

SNS7K

n/c

I/O

Sense pin

Unused

To CS3

Open

Vss or open

Open

To CS3 + Key

To CS4

To CS4 + Key

Vss or open

Open

To CS5

To CS5 + Key

Vss or open

Open

To CS6

To CS6 + Key

Vss or open

Open

To CS7

To CS7 + Key

Vss or open

n/c

Unused

To CS8

SNS8

SNS8K

SNS9

SNS9K

Vss

I/O

Pwr

Sense pin

Ground

Open

To CS8 + Key

Vss or open

Open

To CS9

To CS9 + Key

Vss or open

CKEE

DOEE

DIEE

EEPROM

Unused

Wake

SPI handshake

EEPROM

Clock to EEPROM

Data out to EEPROM

Data in from EEPROM

To Vss

Open

Vdd

n/c

WAKE

CRDY

CSEE

Wake from sleep

1 = Comms ready; Use pull-up R

EEPROM chip select; Use pull-down R

Vdd

Open

n/c

CLK

unused

SPI clock

SPI data

Vss

I/O

From host

To host; use pull-up R

SPI data

From host

/SS

SPI Slave select

Unused

From host

n/c

To Vss

n/c

Unused

To Vss

CMODE

SYNC

LED/STAT

RST

Comms select

Sync In

To Vdd

I/O

Always use pull-up R

20K ~ 220K to Vdd

LED & Status

Reset input

Power

Open

Active low

Vdd

Pwr

+3.3 ~ +5V

OSC1

OSC2

n/c

Resonator

Unused

12MHz - Can also be ext clock in

Open

n/c

Unused

n/c

Unused

n/c

Unused

SNS0

SNS0K

SNS1

SNS1K

SNS2

SNS2K

I/O

Sense pin

To CS0 + Key

To CS0

To CS1 + Key

To CS1

To CS2 + Key

To CS2

Open

Vss or open

Open

Vss or open

Open

Vss or open

CMOS input

CMOS I/O

I/O

CMOS output (push-pull)

CMOS open drain I/O

Power / ground

Pwr

QT1100A-ISG R3.02/1105

Table 1.5 Pin Descriptions

Description

SNSn

Sense pin, to Cs reference capacitor

Sense pin, to Cs and to key electrode

Clock line output, to drive serial EEPROM

Output data line, to serial EEPROM

Input data line, from serial EEPROM

Serial port pin for UART

SNSnK

CKEE

DOEE

DIEE

RX/WAKE Receive pin in UART mode; alternately or in addition, Wake from sleep

CRDY

Serial interface handshake pin; bidirectional in UART mode, output only in SPI

mode. Always use a pull-up resistor on this pin.

CSEE

CLK

Chip select drive to serial EEPROM. Always use a pull-down resistor on this pin.

SPI clock input from host

SPI data output to host. Always use a pull-up resistor on this pin.

SPI data in from host

/SS

SPI Slave select from host

SCANO_x Output scan lines

SCANI_x

CMODE

Input scan lines

Communications mode select pin. For UART or scanport operation, connect to

Vss. For SPI mode, connect to Vdd.

SYNC

Sync Input to synchronize acquisitions to an external source or another QT chip.

Always use a pull-up resistor on this pin.

LED/STAT LED & Status output pin. This pin can sink 1mA to drive a status LED, or be used

by a host controller to determine device error condition or status .

/RST

Reset input, low resets device. Normally this pin can be tied to Vdd, or driven from

a host controller.

OSC1

OSC2

Connect to 12MHz resonator; can also be an external clock input

Connect to 12MHz resonator; leave open if external clock is used

QT1100A-ISG R3.02/1105

Figure 1.1 SPI Connection Diagram

Regulator

VUNREG

VDD

*100nF

*One bypass capacitor to be tightly coupled to pins 36 and 17.

Follow regulator manufacturer's recommendations

for input and output capacitors.

*10uF

*4.7uF

QT1100A-AS

4.7K

2.2K

22nF

2.2K

KEY2

KEY1

KEY0

4.7K

22nF

KEY3

KEY4

KEY5

KEY6

KEY7

2.2K

4.7K

22nF

2.2K

22nF

VDD

12MHz 3-TERM

RESONATOR

2.2K

22K

22nF

4.7K

RESET

4.7K

KEY8

KEY9

SYNC

22K

VSS

DOUT

DIN

CLK

/SS

VDD

CLK

93LC46A

10K

CRDY

WAKE

22K

Note 1: EEPROM is optional when using SPI interface.

Note 2: See Table 1.4 for unused pin connections.

QT1100A-ISG R3.02/1105

Figure 1.2 UART / Scanport Connection Diagram

Shown with optional EEPROM

Regulator

VUNREG

VDD

*100nF

*One bypass capacitor to be tightly coupled to pins 36 and 17.

Follow regulator manufacturer's recommendations

for input and output capacitors.

*10uF

*4.7uF

QT1100A-AS

4.7K

2.2K

22nF

2.2K

KEY2

KEY1

KEY0

4.7K

22nF

KEY3

KEY4

KEY5

KEY6

KEY7

2.2K

4.7K

22nF

2.2K

22nF

VDD

12MHz 3-PIN

RESONATOR

2.2K

22K

22nF

4.7K

RESET

4.7K

KEY8

KEY9

SYNC

22K

VSS

DOUT

DIN

CLK

SCANI_0

SCANI_1

SCANI_2

SCANO_3

SCANO_2

SCANO_1

SCANO_0

VDD

93LC46A

10K

22K

CRDY

RX/WAKE

Note 1: EEPROM is optional when using UART interface in this drawing.

Note 2: UART interface is not normally used when using Scanport interface and vice versa.

Note 3: See Table 1.1 for unused pin connections

QT1100A-ISG R3.02/1105

Figure 1.3 Scanport Only Connection Diagram+

Without EEPROM

Regulator

VUNREG

VDD

*100nF

*One bypass capacitor to be tightly coupled to pins 36 and 17.

Follow regulator manufacturer's recommendations

for input and output capacitors.

*10uF

*4.7uF

QT1100A-AS

4.7K

2.2K

22nF

2.2K

KEY2

KEY1

KEY0

4.7K

22nF

KEY3

KEY4

KEY5

KEY6

KEY7

2.2K

22nF

2.2K

22nF

VDD

12MHz 3-PIN

RESONATOR

2.2K

22K

22nF

4.7K

RESET

4.7K

KEY8

KEY9

SYNC

22K

SCANI_0

SCANI_1

SCANI_2

SCANO_3

SCANO_2

SCANO_1

SCANO_0

QT1100A-ISG R3.02/1105

2.5 Sensitivity Balance

2 Device Control & Wiring

A number of factors can cause sensitivity imbalances among

the keys. Notably, SNS wiring to electrodes can have

differing stray amounts of capacitance to ground, perhaps

due to trace length differences or the presence of ground,

power, or other signal wiring near the SNS traces. Increasing

load capacitance (Cx) will cause a decrease in gain. Key

size differences, and proximity to other metal surfaces can

also impact gain.

2.1 Oscillator

The QT1100A uses an external 12MHz resonator as its

frequency reference. This frequency can be lowered for

lower average power, however all functions will also slow

down including response time and communications

parameters. It is not advised to change the operating

frequency without a good reason.

The keys may thus require ‘balancing’ to achieve similar

sensitivity levels. The NTHR parameter in the Setups

functions is one easy way to trim and balance key sensitivity

(Section 4.1).

The oscillator source can be from an external circuit, so that

two or more circuits can share the same oscillator. If an

external frequency source is used, it should be fed to OSC1,

pin 37. OSC2 should be left open-circuit.

Balancing can also be achieved by adjusting the Cs

capacitor values to achieve equilibrium. The Rs resistors

have no effect on sensitivity and should not be altered. Load

capacitance to ground (to boost Cx) can also be added to

overly sensitive channels to reduce gain; these should be on

the order of a few picofarads.

2.2 Spread Spectrum Modulation

The device features spread spectrum modulation of its

acquisition bursts to dramatically reduce both RF emissions

and susceptibility to external AC fields. This feature cannot

be disabled or modified.

Spread spectrum modulation works together with the

detection integrator (‘DI’) process to eliminate external

interference in almost all cases.

2.6 Power Supply

The power supply can range from 3.3 to 5.0 volts. If this

fluctuates slowly with temperature, the device will track and

compensate for these changes automatically with only minor

changes in sensitivity. If the supply voltage drifts or shifts

quickly, the drift compensation mechanism will not be able to

keep up, causing sensitivity anomalies or false detections.

2.3 Cs Sample Capacitors

The Cs sample capacitors accumulate the charge from the

key electrodes and determine sensitivity. (See Section 2.4)

The Cs capacitors can be virtually any plastic film or low to

medium-K ceramic capacitor. The ‘normal’ Cs range is 2.2nF

to 100nF depending on the sensitivity required; larger values

of Cs require higher stability to ensure reliable sensing.

Acceptable capacitor types for most uses include PPS film,

polypropylene film, and NP0 and X7R ceramics. Lower

grades than X7R are not advised.

The Cs capacitors and all associated wiring should be

placed and wired very tight to the body of the IC for noise

immunity to very high frequency RF fields. See Section 2.7.

The power supply should be locally regulated using a

3-terminal device. If the supply is shared with another

electronic system, care should be taken to ensure that the

supply is free of digital spikes, sags, and surges which can

cause adverse effects.

For proper operation a 0.1µF or greater bypass capacitor

must be used between Vdd and Vss; the bypass capacitor

should be routed with very short tracks to the device’s Vss

and Vdd pins.

2.7 PCB Layout and Construction

Ground Planes: The PCB should if possible include a

copper pour under and around the IC, but not under the SNS

lines after the Rsns resistors. Ground planes increase

loading capacitance (Cx) on the SNS lines and can

dramatically degrade sensitivity.

2.4 Sensitivity

Sensitivity can be altered to suit various applications and

situations on a key-by-key basis. One way to impact

sensitivity is to alter the value of each Cs when the device is

in NTM = 0 mode (see page 25); higher values of Cs will

yield higher sensitivity; each key has its own Cs value and

so can be adjusted independently. The Setups block can

also be used to alter sensitivity, using an external EEPROM,

serial communications, or both (Section 4.1).

Part Placement: The resistors and capacitors associated

with each key should be placed physically as close to the

body of the QT1100A as possible, with the shortest possible

trace lengths, to minimize the influence of external fields

(see Section 2.9.2). The QT1100A should be placed as close

to the key electrodes as possible to reduce wiring lengths, to

minimize stray capacitances on and between SNS traces

and to reduce interference problems.

Sensitivity can also be increased by using bigger electrode

areas, reducing panel thickness, or using a panel material

with a higher dielectric constant (e.g. glass instead of

plastic).

In some cases the keys may be too sensitive. Gain ca n be

lowered by:

PCB Cleanliness: All capacitive sensors should be treated

as highly sensitive analog circuits which can be influenced

by stray conductive leakage paths. QT devices have a basic

resolution in the femtofarad range; in this range, there is no

such thing as ‘no-clean flux’. Flux absorbs moisture and

becomes conductive between solder joints, causing signal

drift, false detections, and transient instabilities. Conformal

coatings will trap in existing amounts of moisture which will

then become highly temperature sensitive.

a) making the electrode smaller, or,

b) making the electrode into a sparse mesh using a high

space-to-conductor ratio, or,

c) by decreasing the Cs capacitors (if NTM = 0).

Sensitivity trimming is usually done through a process of trial

and error, using a range of ‘standard fingers’ made of

earthed conductive rubber on the end of a plastic rod.

The designer should specify ultrasonic cleaning as part of

the manufacturing process, and in cases where a high level

of humidity is anticipated, the use of conformal coatings after

cleaning to keep out moisture.

QT1100A-ISG R3.02/1105

0.15mm) and relieve the ground plane widely around

them (e.g. 5mm clear space on all sides).

2.8 ESD Protection

Normally, only a series resistor is required for ESD

suppression. A 10K to 22K Rsns resistor in series with each

sense trace to each key is normally sufficient. The dielectric

panel (glass or plastic) usually provides a high degree of

isolation to prevent ESD discharge from reaching the circuit.

5. Do use a ground plane under and around the chip

itself, back to the regulator and power connector (but

not beyond the Rs/Cs/Rsns networks).

6. To prevent cross interference, do not place an

electrode or SNS traces of one QT1100A near the

electrode or the SNS traces of another QT1100A or

similar device, unless they are synchronized with a

Sync signal in a way that adjacent traces and keys do

not have acquisition bursts on them at the same time.

The Rsns resistors should be placed close to and wired

tightly to the chip, not the keys.

If the Cx load is high, Rsns can prevent total charge and

transfer and as a result gain can deteriorate. If a reduction in

Rsns increases gain noticeably, the lower value should be

used. Conversely, increasing the Rsns can result in added

ESD and EMC benefits provided that the increase in

resistance does not decrease sensitivity.

7. Keep the electrodes (and wiring) away from other

traces carrying AC or switched signals.

8. If there are switched LEDs or related wiring near an

electrode or SNS traces (e.g. for backlighting of a key),

bypass the switched traces to ground.

2.9 Noise Issues

9. Use a voltage regulator just for the QT1100A to

eliminate noise coupling from other switching sources

via Vdd. Make sure the regulator’s transient load

stability provides for a stable, settled voltage just

before each burst commences.

2.9.1 LED Traces and Other Switching Signals

Digital switching signals near the SNS lines will induce

transients into the acquired signals, deteriorating the SNR

performance of the device. Such signals should be routed

away from the SNS lines, or the design should be such that

these lines are not switched during the course of signal

acquisition (bursts).

LED terminals which are multiplexed or switched into a

floating state and which are within or physically very near a

key structure (even if on another nearby PCB) should be

bypassed to either Vss or Vdd with at least a 10nF capacitor

of any type, to suppress capacitive coupling effects which

can induce false signal shifts. LED terminals which are

constantly connected to Vss or Vdd do not need bypassing.

2.10 Start-up Time

After a reset or power-up event, the device requires 400ms

to read the EEPROM, if one is connected, initialize the

device, and start acquiring signals. After this time, the part

will calibrate all keys. The calibration time depends on the

burst spacing but is about 450ms for a burst spacing of 3ms.

This time is proportional to the burst spacing (Section 4.14).

The burst spacing governs the time from the start of one key

acquisition cycle to the next, and can be set via serial Setups

or via the external EEPROM. Thus, the total start-up time

after a reset is about 850ms if the burst spacing is set to

3ms.

2.9.2 External Fields

External AC fields (EMI) due to RF transmitters or electrical

noise sources can cause false detections or unexplained

shifts in sensitivity.

The device will communicate immediately after the Setup

block is loaded (from EEPROM. if any, or from defaults).

The influence of external fields on the sensor is reduced by

means of the Rsns series resistors. The Cs capacitors and

the Rsns resistors form a natural low-pass filter for incoming

RF signals; the roll-off frequency of this network is defined

by -

2.11 Operating Parameter Setups

The device features a Setups block area in internal RAM that

holds numerous configuration parameters determining how

the part will operate. Each key can be configured individually

for a wide variety of parameters as discussed in Section 4. In

addition, the device can be configured for the AKS™ function

which treats participating keys as a group in which only the

key with the strongest signal will generate a response.

F_R=

2✜R_SNSC_S

If for example Cs = 4.7nF, and Rsns = 10K, the EMI rolloff

frequency is ~3.4kHz, which is much lower than most noise

sources (except for mains frequencies i.e. 50/60Hz).

Standalone (with EEPROM) Setups: In standalone mode

with EEPROM, device setups are configured using an

external 93LC46A byte-mode EEPROM (see Table 1.2, page

5). This part can be programmed separately using a

commercially obtainable programming device then inserted

into the circuit, or, it can be programmed using a QT1100A in

serial mode via a PC interface with the 93LC46A in a socket

so that it can be transferred to the target PCB.

The EEPROM contents and default values are detailed in

Table 4-1, page 31. The last EEPROM entry should be a

CRC check byte. If the CRC byte is set to 0xD6, the CRC will

be ignored.

Rsns and Cs must both be placed very close to the body of

the IC so that the lead lengths between them and the IC do

not form an unfiltered antenna at very high frequencies.

PCB layout, grounding, and the structure of the input

circuitry have a great bearing on the success of a design to

withstand electromagnetic fields and be relatively noise-free.

These design rules should be adhered to for best ESD and

EMC results:

1. Use only SMT components.

2. Keep all Cs, Rs, Rsns, and the Vdd/Vss bypass

capacitor components wired tightly to the IC.

In standalone mode the EEPROM must have the first byte in

location 0 set to the value 0xD6 for the EEPROM to be read.

The rest of the Setup table must follow, starting at location 1

in the EEPROM.

3. Place the QT1100A as close to the keys themselves as

possible.

4. Do not place electrodes or associated wiring near

other signals, or near a ground plane. If a ground plane

is unavoidable, keep the SNS tracks very thin (e.g.

QT1100A-ISG R3.02/1105

Without the EEPROM the QT1100A will operate in a default

mode, designed to accommodate most touch sensing

requirements (Section 2.12, below).

All logic on the scanport is ‘active high’ for both Scan_In and

Scan_Out. The scanport maps to the Scan_In and Scan_Out

pins as per Table 2.1.

Serial Mode Setups: The two serial interfaces permit a

host MCU to program control setups into the QT1100A on

power-up or even during normal operation, allowing low cost

reconfigurability. This is performed with a block of data,

referred to as a Setups block.

The Setups block must end with a CRC check byte. If the

optional 93LC46A EEPROM is also used, the Setups block

will be stored locally so that there is no need to reload after

each power-up.

Table 2.1 - Scanport I/O Mapping

Scan Out Scan Out Scan Out

Scan Out

Key 0

Key 4

Key 8

Key 1

Key 5

Key 9

Key 2

Key 6

Key 3

Key 7

Scan In 0

Scan In 1

Scan In 2

The scanport is enabled if the CMODE pin is strapped low.

The UART is also enabled in this mode but it can be ignored ;

if UART serial is not used, TX should be connected to Vss.

2.12 Standalone Operation, No EEPROM

The device can operate in Standalone Mode without serial

communications or EEPROM using only its parallel scanport

interface. (See Table 1.3, page 6 and Figure 1.3, page11)

There are some minor differences in the default settings and

behaviour in Standalone Mode without EEPROM compared

with other modes:

Scanport Latency: The latency of the scanport from

Scan_In to Scan_Out is 120µs maximum. UART transfers do

not affect this response time. Scanning software has to take

this delay into account, i.e. it should not expect the

Scan_Out pins to be stable until 120µs after setting the

Scan_In pins.

One easy way to use the scanport is to read the scanport

before changing the Scan_In signals. Normally, Scan_In

should be changed to a new state every 1 ~ 2ms. Faster

scanning than this will not result in a perceptibly faster

response time. Therefore, if the Scan_Out lines are read

immediately before changing the Scan_In signals, the host

controller will not have to wait for the 120µs scanport

latency.

1. K2L is enabled on all keys*

2. SYNC is enabled (SE = 1)*

3. No serial comms - CRDY is always clamped low

*These exceptions are noted in Table 4-1, page 31.

2.13 EEPROM Functionality

The serial EEPROM is used to store Setups information

which alters the device behavior. If the EEPROM is not used,

the device uses default parameters to operate, or,

customized parameters loaded into the device via serial

interface.

System Response Time: The setting of the two detection

integrators (see Section 4.9) strongly affects the basic

device response time. The host’s scan rate adds to this time.

If the basic QT1100A response time is set to 80ms, and the

host completely scans the device every 50ms, the total

response time can be a very slow 130ms.

The EEPROM’s functionality is not necessary when used

with a serial interface. The host serial controller can send the

Setups to the QT1100A following each power-up. In a serial

mode, the EEPROM eliminates the need to send Setups

after each power-up since they are stored locally.

One way to maintain good response time while minimizing

host activity is to have the host monitor the LED/STAT pin,

perhaps via interrupt, and service the scanport only when the

LED/STAT pin becomes active. (See Section 4.8, page 27)

The EEPROM must contain the value 0xD6 as its first byte

or it will not be read. The table on page 31 shows the

contents required for this EEPROM. A CRC must be

appended to the end of the EEPROM table, or, the CRC can

be replaced by a 0xD6 code, in which case no CRC

checking will be performed (not recommended except as a

development shortcut). A blank EEPROM will be

Sleep/Wake Function: Sleep/Wake can only be used in

conjunction with a serial mode which sets the sleep state via

a command, and so Sleep is not possible in Scanport mode

without a serial interface.

Sync Mode with Scanport: Sync mode can be enabled

using an EEPROM having the correct Setups; Sync mode

programmed properly when the host sends a Setups block to also works in standalone mode without an EEPROM (see

the device.

also Section 4.12). In Sync mode the acquire bursts are

synchronized to the external clock source; the scanport will

operate correctly while the device is waiting for a sync edge.

EEPROM corruption is automatically detected every 2

seconds during normal run operation. If the EEPROM is

found to be corrupt or erased, the EEPROM error flag is set

in the device status byte (command 0xC2); the EEPROM

itself is not corrected. If the device is using serial

communications, the host controller should reload the

Setups and then reset the device.

2.15 Start-up Sequencing

After power-up or reset the flag ‘Reset Occurred’ will be set.

The user can read this flag with command 0xC2. This flag

can be reset by issuing a ‘0xC2 0xC7’ command sequence.

If in a serial mode an EEPROM is not installed, pin DIEE

should be connected to Vdd.

If an EEPROM is installed and the EEPROM’s CRC does not

match its contents, or the first byte is not 0xD6, the error flag

“EEPROM Error” will be set. In this case, the default Setup

settings will be used but the EEPROM contents will stay

unchanged.

2.14 Scanport Interface

The scanport functions as a ‘legacy replacement’ for a matrix

scanned XY keyboard. Single inputs (one-of-three) on

Scan_In lines result in a pattern of bits on Scan_out pins

depending on the keys that are active. If no keys are active

the Scan_out pins remain inactive. See connection pinlists,

Tables 1.1 and 1.2.

2.16 Error Detection and Reporting

A ‘major error’ is one where an enabled key signal falls

below LBLL (Section 4.13) or rises above a value of 4095, or

where there is a CRC error in RAM or EEPROM Setups. The

QT1100A-ISG R3.02/1105

former can occur if the Cs capacitor fails or there is a short

in the SNS circuit; if this happens, the affected key is shut

down immediately and the key is switched off.

control. The UART mode operates in the same way and with

the same protocol and commands as the SPI interface.

UART mode is selected by strapping the CMODE pin low.

UART mode and Scanport mode can operate together. If

only UART mode is desired, the Scan_In pins need to be

grounded. If only the Scanport is used, the UART can be

ignored. An unused RX line should be connected directly to

Vdd.

Keys that are intentionally disabled will not burst, and so

cannot show an error. In standalone mode with no EEPROM

present (Scanport mode), keys are disabled by strapping the

SNS pins to ‘unused’ settings (Table 1.1 page 4), and this

will not generate a ‘major error’, unless the error occurs after

the part has gone through power-up calibration successfully

without detecting that the key is disabled via SNS pin

configuration.

In any mode that uses an EEPROM or uses either UART or

SPI communications, keys must be disabled by setting the

NTHR parameter to zero for the key(s) (Section 4.1). If in

EEPROM or serial mode a key is disabled via SNS pin wiring

only, it will be classified as a ‘major error’.

UART transmission parameters are (Fosc = 12MHz):

Baud rate options:

Start bits:

4800, 9600, 19.2K, 28.8K

Data bits:

Parity:

None

Stop bits:

UART Operation with Scanport: Scanport and UART

operation can be used together. (See Section 2.14)

3.1.1 TX Pin

3 Serial Operation

The TX pin has an open-drain drive to allow bussing with

other similar parts. The TX line can thus be shared with other

UART based peripherals such as a second QT1100A.

There are two serial interfaces in the QT1100A: UART, and

SPI.

UART provides a simple solution using well known

asynchronous signalling. Many MCUs contain UART or

USART blocks which are perfectly suited to this mode.

MCUs without a UART hardware function can easily use a

firmware UART function in most cases. The chief advantage

of UART mode is wiring simplicity: only 3 wires, (TX, RX, and

CRDY) are required.

TX must be pulled high to Vdd with a resistor in UART mode.

The resistor value will depend on the total amount of stray

capacitance on TX - more capacitance will require lower

values of pull-up resistor, especially at higher Baud rates.

The risetime of the signals on this line should be 1/10th of

the bit width, i.e., if running at 9600 Baud, the bit width is

about 100µs, and the risetime should be 10µs or less. In

most cases, a 47K resistor is low enough, however this

should be confirmed using an oscilloscope.

SPI communications are based on the well known

synchronous interface used extensively between

microcontrollers and peripherals. The QT1100A uses

slave-only SPI mode. This interface does not require an

accurate clock rate, and can operate faster than UART

mode. However, SPI operation requires 5 wires.

An unused TX pin should be connected to Vss.

3.1.2 Sleep/Wake Operation in UART Mode

The device can be put into sleep mode with a serial

command (0x05). The device can sleep for up to 700ms;

some time after this it will self-reset. The Wake and RX

functions are on the same pin, which allows a host to

conveniently wake the device with a dummy character (e.g.

0x00 null) before communicating with it. Wake operates on

the falling edge; the negative-going level must be at least

40µs wide to be recognized.

The host device always initiates communications

sequences; the QT1100A is incapable of chattering data

back to the host. A command from the host to the QT1100A

always ends in a one or more byte response from the

QT1100A. Some transmission types from the host require

the use of a CRC check byte to provide for robust

communications. This command/response design is

intentional for FMEA purposes so that the host always has

total control over the communications with the QT1100A.

Effectively this behavior forces designs to have inherently

self-checking ‘loop back’ characteristics.

See also Section 3.5.7.

4.8 K2L / LEDP / KEYO Control Bits

K2L: Bytes 20 - 29, Bit 4 (one per key)

LEDP: Byte 32, Bit 3

KEYO: Byte 34, Bit 7

Default K2L value:

Default LEDP value:

Default KEYO value:

0 (off)

4.9 NDIL, FDIL - Detect Integrator Bits

NDIL: Bytes 20 - 29, Bits 3..0

0 (active low)

0 (off)

FDIL: Byte 32, Bits 7..4

Default NDIL value:

Default FDIL value:

Typical values:

The LED pin can be used as a health indicator, key detect

indicator, and an error status. This pin can act as a backup

information source for a host microcontroller to provide for

redundant signalling. The LED pin is a full push-pull CMOS

driver.

NDIL = 2, FDIL = 5

To suppress false detections caused by spurious events like

electrical noise, the device incorporates a 'detection

integrator' or DI counter mechanism that acts to confirm a

detection by consensus (all detections in sequence must

agree). The DI mechanism counts sequential detections of a

key that appears to be touched, after each burst for the key.

For a key to be declared touched, the DI mechanism must

count to completion without even one detection failure.

K2L Key-To-LED Function: This bit (one per key) enables

the associated key, when active, to force the LED pin active

for one and only one complete burst cycle (during all 10 keys

starting from timeslot 0); this is a one-shot output. If there is

also an ongoing major error, the major error takes

precedence and LED stays solid-active. The 10µs Heartbeat

pulse (see below) still exists after timeslot 9. It is possible to

have multiple keys’ K2L bits enabled. K2L can be used to

establish a redundant signalling path for important ‘Halt’ or

‘Panic’ keys etc. The KEYO function is overridden by K2L for

one scan cycle.

The DI mechanism uses two counters. The first is the ‘fast

DI’ counter FDIL. When a key’s signal is first noted to be

below the negative threshold, the key enters ‘fast burst’

mode. In this mode the burst is rapidly repeated for up to the

specified limit count of the fast DI counter. Each key has its

own counter and its own specified fast-DI limit (FDIL), which

can range from 1 to 15. When fast-burst is entered the

device locks onto the key and repeats the acquire burst until

the fast-DI counter reaches FDIL, or, the detection fails

beforehand. After this the device resumes normal

K2L in Standalone Mode: K2L is automatically enabled on

all keys in standalone mode when no EEPROM is present.

This can be used to interrupt a host controller whenever any

enabled key is touched.

Heartbeat Pulses: At the end of each complete keyscan

after the timeslot for key 9, the LED pin will pulse low for

10µs as a ‘health’ indicator. The exception to this is if the

LEDP control bit is high (active high LED drive), in which

case Heartbeat pulses are disabled. It is possible to monitor

the Heartbeat pulse in a way that confirms the device is

operating properly.

keyscanning and goes on to the next key.

The ‘Normal DI’ counter counts the number of times the

fast-DI counter reached its FDIL value. The Normal DI

counter can only increment once per complete scan of all

keys. Only when the Normal DI counter reaches NDIL does

the key become tagged ‘active’.

The net effect of this is that the sensor can rapidly lock onto

and confirm a detection with many confirmations, while still

LEDP LED Polarity Function Control Bit. This bit controls

the active polarity of the LED output. If it is 0, the LED pin is

QT1100A-ISG R3.02/1105

scanning other keys. The ratio of ‘fast’ to ‘normal’ counts is

completely user-settable via the Setups process. The total

number of required confirmations is equal to the product of

FDIL and NDIL.

Positive drift compensation (PDCR) also works to restore

signal levels that are erroneously positive. However this

mechanism is much slower and is used primarily to

compensate for longer term drift factors, whereas PTHR is

used to compensate more quickly for fast rises in signal

value.

Example: If FDIL = 5 and NDIL = 2, the total DI count

required is 10, even though the device only scanned through

all keys twice.

The DI mechanism is extremely effective at reducing false

detections at the expense of slower reaction times. In some

applications a slow reaction time is desirable; the DI

mechanism can be used to intentionally slow down touch

response to require the user to touch longer to operate the

key.

The PTHR parameter is global to all keys; it is a single byte

parameter common to all. It is measured in counts of signal

and can be set from 2..15.

4.11 PHYS - Positive Hysteresis Bits

Byte 30, Bit 3..0

Default value:

Typical value: 10% of PTHR or 1 count

If FDIL = 1, the device functions conventionally; each

channel acquires only once in rotation, and the normal

detect integrator counter (NDIL) operates to confirm a

detection. The Fast-DI feature is effectively disabled.

(whichever is greater)

Positive hysteresis is used in setting the drop out level at

which a positive detection ceases (see PTHR above).

If FDIL m 2, then the fast-DI counter also operates in addition

The value is expressed as a signal count from the positive

threshold value back down towards the reference. Thus

given a scenario:

to the NDIL counter.

If the key has not yet been declared active, the following

takes place:

1. If (Signal [NTHR): The signal is strong, and the fast-DI

counter is incremented towards FDIL. Once FDIL is

reached, the Normal DI counter increments once.

Reference = 732

PTHR = 5 counts

PHYS = 1,

then the signal has to rise to 732 + 5 = 737 to cause a

positive detection. At this point the positive recal delay (PRD)

engages and starts timing the signal excursion. Providing

that the signal level does not fall below 736 (1 count of

hysteresis below 737) the timer will continue until it expires,

at which point the affected key is fully recalibrated (and only

that key).

2. If (Signal > NTHR): Both the fast-DI and normal DI

counters are cleared due to lack of sufficient signal.

3. If (Normal DI counter = NDIL): The key is declared

active.

Once the key is declared active, the following takes place:

The PHYS parameter is global to all keys; it is a single byte

parameter common to all. It is measured in counts of signal

and can be set from 0..15.

1. If (Signal [ NTHR): The signal is still strong enough to

sustain key detection. The key remains in detection,

and the Normal DI counter increments if it is less than

NDIL.

4.12 SE, SYNC Control Bits

2. If (Signal > NTHR) and (Signal [ NHYS): The key

signal is weak, however the key remains in detection

and the Normal DI counter remains unchanged.

3. If (Signal > NHYS): There is insufficient signal to

sustain key detection, and the Normal DI counter is

decremented towards 0.

Byte 32, Bits 1, 0

Default SE value:

0 (off)

Default SYNC value:

0 (level sensing)

The Sync functions allow the device to synchronize to

external clock sources or to other similar devices to prevent

interference effects.

Most interference in capacitance sensors comes from beat

frequency and alias generation due to non-coherency

between the sampling rate of the sensor and an external

noise source. Another similar sensor can be considered a

noise source.

4. If (Normal DI counter = 0), the key is declared inactive.

4.10 PTHR - Positive Threshold Bits

Byte 30, Bits 7..4

Default value:

Typical value: 4 - 10

The QT1100A offers two ways to limit this kind of

interference:

1. Level sensing: Make sure the QT1100A does not

sample at the same time as a similar device, where

physically adjacent keys are concerned.

The positive threshold is used to provide a mechanism for

recalibration of the reference point when a key signal moves

abruptly to the positive. This condition is abnormal; it usually

occurs after a prolonged touch has caused an automatic

recalibration via the NRD parameter, and a subsequent

removal of touch causes the signal to rise abruptly above the

reference level.

The normal desire is to recover from these events quickly,

usually in a second or two. PTHR is the upper threshold for

the detection of these anomalies; PHYS is the corresponding

hysteresis value (see below) used to provide a stable

detection criteria. Positive recal delay (PRD) is the timing

function used to time when the key is recalibrated once the

positive excursion has been noted.

2. Edge sensing: Synchronize the QT1100A to an external

repetitive noise source so that there are no beat

frequencies generated and the interference shows up as

a benign DC offset to the acquired signal.

The SE (‘Sync Enable’) bit determines whether or not Sync

is used. SYNC can be enabled by setting SE = 1. If SE = 0,

the part runs asynchronously regardless of the state of the

SYNC pin. The SYNC bit determines which mode, 1 or 2, the

device operates in if SE = 1.

For a further description see PHYS below.

QT1100A-ISG R3.02/1105

Upper errors are caught using a built-in, fixed upper burst

length limit of 4095; beyond this value of signal, the key is

tagged as being in error.

SE in Standalone Mode: SE is automatically enabled (= 1)

in standalone mode when no EEPROM is present.

SYNC Mode: If SYNC = 0, the device uses the Sync pin to

communicate to another similar part (e.g. one or more

additional QT1100A’s). QT1100A’s connected together in

this way will self- synchronize so that they all acquire on Key

0 at the same time. Provided that the devices run at a similar

clock rate and have the same burst spacing (BS) parameters

the devices will remain locked over their full acquisition

cycles, key for key. In this condition it is easy to design a

PCB where keys from multiple QT1100A’s are physically

adjacent but not of the same key number; thus ensuring that

adjacent keys are never acquiring at the same time and

cannot interfere with each other.

4.14 BS - Burst Spacing Control Bits

Byte 34, Bits 4,3,2

Default value: 2 (3ms)

Typical values: 1 - 4

The interval of time from the start of a burst on one key to

the start of the burst on the next key is known as the burst

spacing. This is an alterable parameter which affects all

keys. The burst spacing can be viewed as a timeslot in which

an acquisition burst occurs. This approach results in an

orderly and predictable sequencing of key scanning with

predictable response times.

Level Mode: If SYNC = 0, the device operates in a level

sensing mode. The open-drain SYNC pin is pulled low by

each device that is currently sensing on any key but key 0.

After the last key is sensed (key 9) the device floats the

SYNC pin and then waits until the SYNC pin actually floats

high. Any other devices sharing the SYNC pin will also clamp

the SYNC pin low until they are done sensing all their keys.

Finally when all devices are waiting to start acquiring on key

0, the SYNC line will actually float high, and the sensor

devices will then all acquire key 0 in unison.

Shorter spacings result in a faster response time to touch;

longer spacings permit higher burst lengths and longer

conversion times but slow down response time.

Standard BS settings from 2ms to 7ms are available. BS

should be set so that the acquire burst lengths themselves

are fully contained in their timeslots, plus 500µs left over.

This can be determined by using a 10x scope probe with a

470K resistor in series and examining the length of the

distorted waveform (this is done to minimize loading effects

which reduce the burst length).

Edge Mode: If SYNC = 1, the part waits for a positive edge

on the SYNC pin to begin acquiring on key 0. Thereafter the

other keys also acquire in sequence according to the BS

setup.

SYNC = 1 should be used for external noise source or power

line synchronization. A simple RC circuit can be connected

from a mains supply to the SYNC pin to ensure phase-

aligned triggering. SYNC can operate from 10Hz ~ 400Hz.

If an acquisition burst exceeds its timeslot, the device will still

operate properly except that time based parameters will be

increased in duration; the timeslots will expand to fill the

burst length which is always variable.

The BS value is obtained via a lookup table (LUT):

BS Value

Setting

2.0ms

2.5ms

3.0ms

3.5ms

4.0ms

5.0ms

6.0ms

7.0ms

If SE = 1 in UART mode, holding pin RX = 0 for excessive

periods, or in SPI mode, holding pin /SS = 0, will prevent

proper operation of SYNC. Since communication has higher

priority than SYNC, communicating during a SYNC active

edge will cause an additional delay of the SYNC process and

result in timing skews. Holding either /SS or RX low

continuously will inhibit SYNC.

These control bits apply to the device as a whole.

4.13 LBLL - Lower Burst Length Limit

Byte 33

4.15 BR - Baud Rate Control Bits

Byte 34, Bits 1, 0

Default value:

Typical value: 50 - 100

Default value: 1 (9600)

LBLL is an FMEA-oriented limits feature used to detect keys

that are not operating properly. If a key is short circuited, or

its Cs/Rs sensing circuit has failed, the acquired signal will

be either one count or attempt to be infinite.

The BR setting allows control over the baud rate, from 4800

to 28.8K Baud according to the following table:

BR Value

Setting

4,800

Lower errors are caught using the LBLL parameter which

can be set from 0 to 255. If {signal < LBLL}, the key is

flagged as having an error and the acquisition burst for that

key is also disabled until the part is reset or the key is

recalibrated. Setting LBLL = 0 will disable this error detection

feature and also stop the ability of a key to be self-disabled if

there is a serious hardware error.

A better method for disabling the LBLL feature is to set it to a

very low value such as 3. This way the device can still stop

acquiring on channels that have serious hardware problems,

yet not generate errors when signals are merely very low.

9,600

19,200

28,800

If the Baud rate is altered via serial communications, the new

Baud rate is effective immediately after the Setup block

loads are complete, that is, after the QT1100A sends the

final response from the Load Setup command (0x01).

If LBLL is set too high, it could cause legitimate touch

detections to trigger an error flag and self-disable a channel.

QT1100A-ISG R3.02/1105

4.16 HCRC - Host CRC

Byte 35

HCRC is an 8-bit CRC code calculated according to CCITT-8

(see page 41) appended to the end of the Setups table. This

code must be sent with each serial transmission of the

Setups block.

An error in the CRC will manifest itself as an error code, and

if this occurs, factory default parameters will be automatically

loaded to provide a ‘safe’, defined recovery.

The CRC can also be replaced with a 0xD6 which will inhibit

CRC checking. Care should be taken so that the CRC is

never actually 0xD6 (if CRC checking is desired). This can

be done by altering any unused Setup parameter.

QT1100A-ISG R3.02/1105

Table 4-1 Serial / EEPROM Setups Block

Data can be sent from the host to the QT1100A in a block of hex data over a serial port. A Setups block received via serial transmission is loaded into RAM (and also into EEPROM

if one is connected). Setups mode is initiated by sending two sequential 0x01 commands to the device. If each byte in the block load sequence is not within 100ms of the preceding

byte, the command will fail and default values or EEPROM values will be used instead of the received Setups block.

EEPROM Setups are a copy of RAM Setups except that EEPROM location 0 will contain 0xD6. Location 0 of the EEPROM must contain 0xD6 or it will not be read. The Setups

block can also be preloaded into EEPROM to control stand-alone (scanport) mode. If the initial 0xD6 is read at power-up, the remainder of the EEPROM is then loaded (provided

the EEPROM CRC is acceptable). EEPROM address location 1 corresponds to Setups block byte 0. If the last EEPROM byte is also fixed at 0xD6 in place of a CRC, EEPROM

CRC checking is disabled.

Note: After any Setups changes, the part should be recalibrated using 0x03 (Enter Cal mode).

Byte

Valid

Key

Default

Value

Block Byte # Parameter

Sym

Len Range Bits Scope

Description

Page

Neg thresh

NTHR

Unused

NHYS

0..15

Upper nibble = Neg threshold; 0 = key disabled

Bit_3, 2: Unused

0..9

0x00..0x09 Unused

Neg hyst

0..3

Lower nibble = Neg hysteresis, 3 = 12.5%, 2 = 25%, 1 = 50%, 0 = 0%

Neg drift comp rate

NDCR

0..15

7 (2.18s @3ms) Upper nibble = NDCR; 0 = no NDC (via LUT, page 32)

10..19 0x0A..0x13

Neg recal delay

NRD

0..15

5 (14.42s @3ms) Lower nibble = NRD; 0 = infinite (via LUT, page 34)

AKS enable

Unused

AKS

Unused

Bit_7: 1 = AKS enable (each key)

0, 1

0 (disable)

Bit_6: Unused

Error Key

Key To LED

Bit_5: EK - Key forced active on major error (each key)

Bit_4: 1 = Key to LED function enable (each key)

Note: In Standalone Mode with no EEPROM, K2L = 1 (enabled) on all keys

Lower nibble = Norm DI Limit; Thresh crossings to detection; min = 1

0, 1

0 (off)

0 (off)*

20..29 0x14..0x1D

K2L

Normal det int limit

NDIL

1..15

Pos thresh

PTHR

2..15

Upper nibble = Pos threshold; sets sensitivity to +recal

0x1E

0x1F

Pos hyst

PHYS

0..15

Lower nibble = Pos hysteresis, counts down from +thresh

Pos drift comp rate

Pos recal delay

PDCR

PRD

0..15

5 (0.68s @3ms) Upper nibble = PDCR; 0 = no PDC; (via LUT, page 33)

7 (1.03s @3ms) Lower nibble = PRD; (via LUT, page 35)

Fast (neg) DI Limit

FDIL

LEDP

NTM

1..15

0, 1

Upper nibble = Fast Neg DI limit; min = 1

LED Polarity

Device

0 (normal)

0 (fixed)

0 (off)*

Bit_3: 1 = LED pin is inverted

Neg Thresh Mode

Sync Enable

Bit_2: 1 = Ratiometric neg thesh; 0 = fixed thresholds.

Bit_1: 1 = Sync enabled (default = 0, disabled)

Note: In Standalone Mode with no EEPROM, SYNC = 1 (enabled)

Bit_0: SYNC mode (default = 0, level; 1 = edge)

0x20

0x21

Device

Sync pin mode

Lower BL Limit

SYNC

LBLL

0, 1

Device

0 (level)

0x03

Lower limit of acceptable burst length; below this, declares error.

0..255

Default = 3 (error on catastrophic channel failure)

KEYO

Unused

0 (disable)

3 (binary ‘11’)

2 (3ms)

Bit_7 = LED pin also shows keypress if KEYO = 1

Bit_6,5 = Unused

Bit_4,3,2 = Burst spacing (BS), 8 values in increasing order -

2ms, 2.5ms, 3ms, 3.5ms, 4ms, 5ms, 6ms, 7ms settings

Bit_1,0 = Baud rate (BR); 4 values; UART mode only

4800, 9600 (default), 19.2K, 28.8K in increasing order

0, 1

Device

0x22

0x23

Control bits

0..7

Device

1 (9600)

0..3

Device

CRC of above Setups block (0xD6 disables CRC checking).

Host CRC

HCRC

Device <computed value>

See page 41 for algorithm.

Data area is 35 bytes; plus CRC makes 36.

Block length

EEPROM area has 37 bytes which also includes an initial 0xD6 byte.

QT1100A-ISG R3.02/1105

Table 4-2 NTHR Ratiometric Threshold Values

This section assumes bit NTM = 1 (in byte 32 - see Table 4-1). Threshold values established by the NTHR Setup are made in terms of signal deviation expressed as a percentage

of the reference value. This gives key sensitivity a great tolerance towards part variances, deviations in Cs , and to a good extent, Cx. Settings are subject to a minimum of 3 counts

of signal, which can come into play with short burst lengths and low percentages. The values are as follows:

Setup Value

Sensitivity

Less sensitive

More sensitive

✁

Percentage of Reference disabled

6.25%

5.47%

4.69%

3.91%

3.13%

2.73%

2.34%

1.95%

1.56%

1.37%

1.17%

0.98%

0.78%

0.59%

0.39%

If NTM = 0, the threshold is based on the raw numerical value entered for each channel in the NTHR parameter in Setup bytes 0..9 plus 5 co unts, and can thus range from

5 to 20 (0 + 5... 15 + 5). NTM = 0 (the default setting) is useful in standalone applications, where key gains are adjusted by changing the value of Cs or Cx for each key.

4.17 Timing Tables

Lookup tables (LUTs) translate several Setups values into actual internal parameters. NDCR example: BS = 4ms, NDCR = 6. The actual NDCR is then 2.46s per adjustment.

Table 4-3 NDCR Negative Drift Compensation Rate Lookup Table (LUT)

Setups

Value

1.23

LUT

NDCR Time, Seconds

Value

BS = 2ms

BS = 2.5ms BS = 3ms BS = 3.5ms BS = 4ms

BS = 5ms

BS = 6ms

BS = 7ms

-7

-9

Disabled

0.45

0.57

0.69

0.81

0.99

1.23

1.47

1.83

2.25

2.73

3.33

4.11

5.07

6.21

7.65

Disabled

0.56

0.71

0.86

1.01

1.24

1.54

1.84

2.29

2.81

3.41

4.16

5.14

6.34

7.76

9.56

Disabled

0.67

0.85

1.04

1.22

1.49

1.85

2.21

2.75

3.38

4.10

4.99

6.16

7.60

9.31

11.48

Disabled

0.79

1.00

1.21

1.42

1.73

2.15

2.57

3.20

3.94

4.78

5.83

7.19

8.87

10.87

13.39

Disabled

0.90

Disabled

1.13

Disabled

1.35

Disabled

1.58

1.14

1.43

1.71

2.00

-11

-13

-16

-20

-24

-30

-37

-45

-55

-68

-84

-103

-127

1.38

1.62

1.98

2.46

2.94

3.66

4.50

5.46

6.66

8.22

10.14

12.42

15.30

1.73

2.03

2.48

3.08

3.68

4.58

5.62

6.82

2.07

2.43

2.97

3.69

4.41

5.49

6.75

8.19

2.42

2.84

3.47

4.31

5.14

6.40

7.87

9.55

11.66

14.39

17.75

21.74

26.78

8.32

9.99

10.28

12.68

15.53

19.13

12.33

15.21

18.63

22.95

Gray numbers are preferred values for most touch control applications

QT1100A-ISG R3.02/1105

Table 4-4 PDCR Positive Drift Compensation Lookup Table (LUT)

Setups

Value

1.23

LUT

PDCR Time, Seconds

Value

BS = 2ms

BS = 2.5ms BS = 3ms BS = 3.5ms BS = 4ms

BS = 5ms

BS = 6ms

BS = 7ms

Disabled

0.21

0.27

0.33

0.39

0.51

0.57

0.69

0.87

1.05

1.29

1.59

1.95

2.43

2.97

3.60

Disabled

0.26

0.34

0.41

0.49

0.64

0.71

0.86

1.09

1.31

1.61

1.99

2.44

3.04

3.71

4.54

Disabled

0.32

0.41

0.50

0.58

0.76

0.85

1.04

1.31

1.58

1.94

2.39

2.93

3.65

4.46

5.44

Disabled

0.37

0.47

0.58

0.68

0.89

1.00

1.21

1.52

1.84

2.26

2.78

3.41

4.25

5.20

6.35

Disabled

0.42

0.54

0.66

0.78

1.02

1.14

1.38

1.74

2.10

2.58

3.18

3.90

4.86

5.94

7.26

Disabled

0.52

0.67

0.82

0.97

1.28

1.43

1.73

2.18

2.63

3.23

3.98

4.87

6.07

7.42

9.07

Disabled

0.63

0.81

0.99

1.17

1.53

1.71

2.07

2.61

3.15

3.87

4.77

5.85

7.29

8.91

10.89

Disabled

0.73

0.94

1.16

1.37

1.79

2.00

2.42

3.05

3.68

4.52

5.56

6.82

8.50

10.40

12.71

Gray numbers are preferred values for most touch control applications

QT1100A-ISG R3.02/1105

Table 4-5 NRD Negative Recal Delay Lookup Table (LUT)

Setups

Value

1.23

LUT

NRD Time, Seconds

BS = 3.5ms BS = 4ms

Value

BS = 2ms

BS = 2.5ms BS = 3ms

BS = 5ms

BS = 6ms

BS = 7ms

Infinite

4.5

5.7

6.9

8.1

Infinite

5.6

7.1

Infinite

6.8

8.6

Infinite

7.9

Infinite

9.0

Infinite

11.3

14.3

17.3

20.3

24.8

30.8

36.8

45.8

56.3

68.3

83.3

102.8

126.8

155.3

191.3

Infinite

13.5

17.1

20.7

24.3

29.7

36.9

44.1

54.9

67.5

81.9

99.9

123.3

152.1

186.3

229.5

Infinite

15.8

19.9

24.1

28.4

34.6

43.0

51.5

64.0

78.8

95.5

116.6

143.8

177.4

217.3

267.8

-7

-9

10.0

12.1

14.2

17.3

21.5

25.7

32.0

39.4

47.8

58.3

71.9

88.7

108.7

133.9

11.4

13.8

16.2

19.8

24.6

29.4

36.6

45.0

54.6

66.6

82.2

101.4

124.2

153.0

-11

-13

-16

-20

-24

-30

-37

-45

-55

-68

-84

-103

-127

8.6

10.4

12.2

14.9

18.4

22.1

27.4

33.8

41.0

50.0

61.6

76.0

93.2

114.8

10.1

12.4

15.4

18.4

22.9

28.1

34.1

41.6

51.4

63.4

77.6

95.6

9.9

12.3

14.7

18.3

22.5

27.3

33.3

41.1

50.7

62.1

76.5

Gray numbers are preferred values for most touch control applications

QT1100A-ISG R3.02/1105

Table 4-6 PRD Positive Recal Delay Lookup Table (LUT)

Setups

Value

1.23

LUT

PRD Time, Seconds

Value

BS = 2ms

BS = 2.5ms BS = 3ms BS = 3.5ms BS = 4ms

BS = 5ms

BS = 6ms

BS = 7ms

Infinite

0.21

0.27

0.33

0.39

0.51

0.57

0.69

0.87

1.05

1.29

1.59

1.95

2.43

2.97

3.63

Infinite

0.26

0.34

0.41

0.49

0.64

0.71

0.86

1.09

1.31

1.61

1.99

2.44

3.04

3.71

4.54

Infinite

0.32

0.41

0.50

0.58

0.76

0.85

1.04

1.31

1.58

1.94

2.39

2.93

3.65

4.46

5.44

Infinite

0.37

0.47

0.58

0.68

0.89

1.00

1.21

1.52

1.84

2.26

2.78

3.41

4.25

5.20

6.35

Infinite

0.42

0.54

0.66

0.78

1.02

1.14

1.38

1.74

2.10

2.58

3.18

3.90

4.86

5.94

7.26

Infinite

0.52

0.67

0.82

0.97

1.28

1.43

1.73

2.18

2.63

3.23

3.98

4.87

6.07

7.42

9.07

Infinite

0.63

0.81

0.99

1.17

1.53

1.71

2.07

2.61

3.15

3.87

4.77

5.85

7.29

8.91

10.89

Infinite

0.73

0.94

1.16

1.37

1.79

2.00

2.42

3.05

3.68

4.52

5.56

6.82

8.50

10.40

12.71

Gray numbers are preferred values for most touch control applications

QT1100A-ISG R3.02/1105

5 - Specifications

5.1 Absolute Maximum Specifications

Operating temp,Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 ~ +85C

Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 ~ +125C

Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 ~ +5.5V

Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite

Short circuit duration to Vdd, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite

Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (Vdd + 0.3) Volts

5.2 Recommended Operating Conditions

DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3 ~ +5.0V

Fosc (resonator). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12MHz

Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV/s

Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV

Cs value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nF to 100nF

Cx value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 100pF

5.3 AC Specifications

Vdd = 5.0V, Ta = recommended, Cx = 5pF, Cs = 22nF, Fosc = 12MHz

Parameter Description

Min

Typ

Max

Units

Notes

Fosc

Tsu

Trc

Oscillator range

Start-up time from cold start

Recalibration time

400

450

MHz

Resonator frequency

Does not include recalibration time

Burst Spacing = 3ms; changes

proportionately at other spacings

500

Tcs

Comms start-up time from

reset

Comms start-up time from

Wake

Tsu+Trc

150

Tws

160

120

µs

From Sleep mode

Tsl

Tpc

Tac

Scanport latency

Charge-transfer duration

Acquisition time, all

channels

µs

Burst Spacing = 3ms

Nbl

Fqt

Burst length, each channel

Burst frequency range

Response time

500

counts

kHz

175

235

700

Spread spectrum range

BS = 3ms, DI = 3, FDI = 1

Tsm

Max allowable sleep time

5.4 DC Specifications

Vdd = 5.0V, Cs = 22nF, Cx = 5pF, Fosc = 12MHz; Ta = recommended range, unless noted

Parameter

Description

Min

Typ

Max

Units

Notes

DDR

Supply current, run mode

2.9

@ Vdd = 5.0

@ Vdd = 4.0

@ Vdd = 3.6

@ Vdd = 3.3

1.7

1.4

DDS

Supply current, sleep mode

µA

@ Vdd = 5.0

@ Vdd = 3.3

DDS

Supply turn-on slope

Low input logic level

High input logic level

Low output voltage

High output voltage

Input leakage current

Acquisition resolution

100

3.5

V/s

Req’d for start-up, w/o external reset ckt

0.7

0.5

±1

7mA sink

Vdd-0.5

2.5mA source

µA

bits

QT1100A-ISG R3.02/1105

5.5 Burst / Sync Timing

See Section 5.7 for timing parameters

Twbl

floats high

Mode 0 (level sensing) Sync shown

SYNC

Key 0 Burst

Burst_Key0

Twbs

Key 1 Burst

Burst_Key1

CRDY

Twcrdy

QT1100A-ISG R3.02/1105

5.6 SPI Timing Diagram

See Section 5.7 for timing parameters

1. Host first waits for QT1100A to float CRDY high (using pull-up resistor)

2. Host asserts /SS line low

3. Host shifts out byte to QT1100A using 8 falling edges of CLK, on QT1100A pin DI

4. QT1100A shifts data out back to host on the same falling edges of CLK, on QT1100A pin DO

5. QT1100A and host both shift data in on the rising edges of CLK

6. Host releases /SS high

7. CRDY may be pulled low again by QT1100A at any time after /SS is pulled low

8. Host must send nulls to shift out expected return data

Twcrdy

pulled (floats) high

CRDY from QT

/SS from host

clamped low by QT

Tcyc

data shifts out on falling edge

CLK from Host

Host Data Output

(Slave Input - DI)

QT Data Output

(Slave Out - DO)

3-state

Data shifts in on rising edge of SCK

QT1100A-ISG R3.02/1105

5.7 QT1100A Timing Parameters - with Fosc = 12MHz

Parameter

Description

CRDY high (ready to communicate)

Acquisition burst length

Burst spacing time

Min

Typ

Max

Units

Notes

240

Twbs - Twbl

Twcrdy

Twbl

Twbs

µs

2.5

100

2, 3

Burst to CRDY delay

CRDY to /SS max delay (grace period)

/SS to CLK duration

/SS high min recovery time

Setup time, DI to CLK

Hold time, CLK to DI

Delay time, CLK to DO

CLK period

Twbs

100

1,000

Tcyc

Note 1: Twcrdy can last from the end of a burst until the completion of the inter-burst dead-time, i .e. just before the next channel’s burst.

Note 2: Burst spacing will be expanded if the burst time + burst processing time is longer.

Note 3: This setting is determined by Setups, or defaults to 3ms

Note 4: Min time that DI pin must be valid prior to CLK going high

Note 5: 100kHz max clock rate

QT1100A-ISG R3.02/1105

5.8 Current vs Vdd

Fosc = 12MHz, Ta = 20ºC, Cs = 22nF, Cx = 5pF

Typ Idd Vs. Vdd

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

3.5

4.0

4.5

5.0

5.5

Vdd (V)

5.9 Mechanical

All dimensions in thousandths of an inch (Imperial mils)

5.10 Marking

T_A

SSOP Part Number

QT1100A-ISG

Keys

Marking

QT1100A-ISG

Lead-Free

-40ºC to +85ºC

Yes

QT1100A-ISG R3.02/1105

6 Appendix A - 8-Bit CRC C Algorithm

// 8-bit crc calculation. Initial value is 0.

// polynomial = X⁸+ X⁵+ X⁴+ 1

// data is an 8 bit number; crc is an 8-bit number

int eight_bit_crc(int crc, int data)

{

int

index;

fb;

// shift counter

index = 8;

// initialise the shift counter

{

fb = (crc ^ data) & 0x01;

data >>= 1;

crc >>= 1;

if(fb)

{

}

crc ^= 0x8c;

} while(--index);

return crc;

}

A CRC calculator for Windows is available free of charge from Quantum Research.

QT1100A-ISG R3.02/1105

Patented and patents pending worldwide

Corporate Headquarters

1 Mitchell Point

Ensign Way, Hamble SO31 4RF

Great Britain

Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 80565600

www.qprox.com

North America

651 Holiday Drive Bldg. 5 / 300

Pittsburgh, PA 15220 USA

Tel: 412-391-7367 Fax: 412-291-1015

This device covered under one or more of the following United States and international patents: 5,730,165, 6,288,707, 6,377,009,

6,452,514, 6,457,355, 6,466,036, 6,535,200. Numerous further patents are pending which may apply to this device or the applications

thereof.

The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are

subject to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with

every order acknowledgement. QProx, QTouch, QMatrix, QLevel, and QSlide are trademarks of QRG. QRG products are not suitable for

medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in

QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in

connection with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and

customers are entirely responsible for their products and applications which incorporate QRG's products.

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