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QST108

Capacitive touch sensor device

8 keys with individual key state outputs or I2C interface

Preliminary Data

Features

■ Patented charge-transfer design

■ Up to 8 independent QTouch™ keys supported

2

■ Individual key state outputs or I C interface

LQFP32 (7 x 7 mm)

■ Fully “debounced” results

■ Patented AKS™ Adjacent Key Suppression

■ Self-calibration and auto drift compensation

■ Spread-spectrum bursts to reduce EMI

■ Up to 5 general-purpose outputs

Description

The QST108 is the ideal solution for the design of

capacitive touch sensing user interfaces.

Applications

Touch-sensitive controls are increasingly

replacing electromechanical switches in home

appliances, consumer and mobile electronics,

and in computers and peripherals. Capacitive

touch controls allow designers to create stylish,

functional, and economical designs which are

highly valued by consumers, often at lower cost

than the electromechanical solutions they

replace.

This device specifically targets human interfaces

and front panels for a wide range of applications

such as PC peripherals, home entertainment

systems, gaming devices, lighting and appliance

controls, remote controls, etc.

QST devices are designed to replace mechanical

switching/control devices and the reduced

number of moving parts in the end product

provide the following advantages:

The QST108 QTouch™ sensor IC is a pure digital

solution based on Quantum's patented charge-

transfer (QProx™) capacitive technology.

■ Lower customer service costs

■ Reduced manufacturing costs

■ Increased product lifetime

QTouch™ and QProx™ are trademarks of the

Quantum Research Group.

Table 1.

Device summary

Feature

Operating supply voltage 2.4 to 5.5 V

QST108KT6

Individual key state

Supported interfaces

outputs or I²C Interface

Operating temperature

Package

-40° to +85° C

32-pin LQFP

September 2007

Rev 3

1/38

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

QST108

Contents

1

2

3

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Faulty and unused keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Forced key recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Max On-Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.10 Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.11 Adjacent key suppression (AKS™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

4.4

Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4.1

4.4.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Option descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5

I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General-purpose outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Communication packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5

Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1

C_Ssense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/38

QST108

Contents

5.2

Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.1

5.2.2

5.2.3

Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3

5.4

5.5

5.6

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2

6.3

6.4

6.5

6.6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

KOUTn/OPTn/GPOn pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.6.1

6.6.2

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7

6.8

RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

I2C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7

8

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3/38

Device overview

QST108

1

Device overview

The QST108 capacitive touch sensor IC is a pure digital solution based on Quantum's

patented charge-transfer (QProx™) capacitive technology.

This technology allows users to create simple touch panel sensing electrode interfaces for

conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of

the PCB layout (copper pattern or printed conductive ink) and may used in various shapes

(circle, rectangular, etc.).

By implementing the QProx™ charge-transfer algorithm, the QST108 detects finger

presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only

one external sampling capacitor by channel is used in the measuring circuitry to control the

detection.

QST technology also incorporates advanced processing techniques such as drift

compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key

Suppression (AKS) to ensure maximum usability and control integrity.

4/38

QST108

Pin description

2

Pin description

Figure 1.

32-pin package pinout

32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

GPO4/KOUT4/OPT4

SNS_SCK6

SNSK_SCK5

SNS_SCK5

SNSK_SCK4

SNS_SCK4

SNSK_SCK3

SNS_SCK3

SNSK_SCK2

GPO5/KOUT5/OPT5

IRQ/KOUT6/OPT6

I2C_SDA/KOUT7¹⁾

I2C_SCL/KOUT8¹⁾

RESET

QST108KT6

NC

V_{DD_1}

9 10 11 12 13 14 15 16

1. An external pull-up is required on these pins.

Table 2.

Device pin description

Pin name

Type ⁽¹⁾Stand-alone mode function

I²C mode function

If unused

General purpose output 4

and I²C address bit 2

option resistor

Key 4 output / BCD output 4

and MOD_0 option resistor

Option

resistor

1

2

3

OPT4/KOUT4/GPO4 ⁽²⁾

OPT5/KOUT5/GPO5 ⁽²⁾

OPT6/KOUT6/IRQ ⁽²⁾

O

Open or

Key 5 output and

MOD_1 option resistor

General purpose output 5 option

resistor

Open or

Interrupt line (active low) option

resistor

Key 6 output and

OM_0 option resistor

O/OD

4

5

KOUT7/I2C_SDA⁽³⁾

KOUT8/I2C_SCL⁽³⁾

TOD

Key 7 output

Key 8 output

I²C serial data

I²C serial clock

Open

10nF

6

RESET

BD

S

Reset (active low)

capacitor to

ground

7

8

NC

Not Connected

Supply voltage

V_{DD_1}

-

5/38

Pin description

QST108

If unused

Table 2.

Device pin description (continued)

Pin name

Type ⁽¹⁾Stand-alone mode function

I²C mode function

9

V_{SS_1}

S

Ground voltage

-

10 V_{SS_2}

11 V_{SS_3}

12 V_{SS_4}

13 V_{DD_2}

S

Ground voltage

S

Ground voltage

S

Ground voltage

S

Supply voltage

14 SNS_SCK1

15 SNSK_SCK1

16 SNS_SCK2

17 SNSK_SCK2

18 SNS_SCK3

19 SNSK_SCK3

20 SNS_SCK4

21 SNSK_SCK4

22 SNS_SCK5

23 SNSK_SCK5

24 SNS_SCK6

25 SNSK_SCK6

26 SNS_SCK7

27 SNSK_SCK7

28 SNS_SCK8

29 SNSK_SCK8

SNS

Key 1 sense pin to Cs/Rs

Key 1 sense pin to Cs/electrode

Key 2 sense pin to Cs/Rs

Key 2 sense pin to Cs/electrode

Key 3 sense pin to Cs/Rs

Key 3 sense pin to Cs/electrode

Key 4 sense pin to Cs/Rs

Key 4 sense pin to Cs/electrode

Key 5 sense pin to Cs/Rs

Key 5 sense pin to Cs/electrode

Key 6 sense pin to Cs/Rs

Key 6 sense pin to Cs/electrode

Key 7 sense pin to Cs/Rs

Key 7 sense pin to Cs/electrode

Key 8 sense pin to Cs/Rs

Key 8 sense pin to Cs/electrode

Open

Key 1 output / BCD output 1

and MODE option resistor

General purpose output 1 Option

and MODE option resistor resistor

30 OPT1/KOUT1/GPO1 ⁽²⁾

O

General purpose output 2

Option

Key 2 output / BCD output 2

and AKS option resistor

31 OPT2/KOUT2/GPO2 ⁽²⁾

and I²C address bit 0

resistor

option resistor

General purpose output 3

Option

Key 3 output / BCD output 3

and LP option resistor

32 OPT3/KOUT3/GPO3 ⁽²⁾

O

and I²C address bit 1

resistor

option resistor

1. S: supply pin, BD: bidirectional pin, SNS: capacitive sensing pin, O: Output push-pull, OD: Output open-drain and

TOD: True open-drain.

2. During the reset phase, these pins are floating and the state depends on the option resistor.

3. An external pull-up is required on these pins.

6/38

QST108

QST touch sensing technology

3

QST touch sensing technology

3.1

Functional description

QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits

low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields,

and yet permits excellent speed. These devices process all signals using a number of

algorithms pioneered by Quantum. Signals are then digitally processed using algorithms

specifically designed to provide reliable, trouble-free operation over the life of the product.

The QST switches and charge measurement hardware functions are all internal to the

device. An external C capacitor accumulates the charge from sense-plate C , which is

S

X

then measured. Larger values of C cause the charge transferred into C to rise more

X

S

rapidly, reducing available resolution. As a minimum resolution is required for proper

operation, this can result in dramatically reduced gain. Larger values of C reduce the rise

S

of differential voltage across it, increasing available resolution by permitting longer QT

bursts. The value of C can thus be increased to allow larger values of C to be tolerated.

S

X

The device is responsive to both C and C , and changes in either can result in substantial

X

S

changes in sensor gain.

Figure 2. QTouch™ measuring circuitry

C

T

(~5 pF)

SNSK_SCKn

Sense capacitor

(a few nF)

C

S

SNS_SCKn

C

x

(2 to 10 pF)

Ai12569

3.2

Spread-spectrum operation

The bursts operate over a spread of frequencies, so that external fields will have minimal

effect on key operation and emissions are very weak. Spread-spectrum operation works

with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false

detection due to noise.

7/38

QST touch sensing technology

QST108

3.3

Faulty and unused keys

Any sensing channel that does not have its sense capacitor (C ) fitted is assumed to be

S

either faulty or unused. This channel takes no further part in operation unless a Master-

commanded recalibration operation shows it to have an in-range burst count again.

This is important for sensing channels that have an open or short circuit fault across C .

S

Such channels would otherwise cause very long acquire bursts, and in consequence would

slow the operation of the entire QST device.

To optimize touch response time and device power consumption, if some keys are not used,

we recommend to try suppressing the ones which belong to the same burst. Bursts which

do not have any keys implemented will then not be processed.

3.4

3.5

Detection threshold levels

The key capacitance change induced by the presence of a finger is sensed by the variation

in the number of charge transfer pulses to load the capacitor. The difference in the pulse

count number is compared to a threshold in order to detect the key as pressed or not.

Two different thresholds, one for detection and one for the end of detection, create an

hysteresis in order to prevent erratic behavior.

The default threshold levels and hysteresis values are described in Section 6.5: Capacitive

sensing characteristics on page 30.

Detection integrator filter

Detect Integrator (DI) filter mechanism works together with spread spectrum operation to

dramatically reduce the effects of noise on key states. The DI mechanism requires a

specified number of measurements that qualify as detections (and these must occur in a

row) or the detection will not be reported.

In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several

measurements. This process acts as a type of “debounce” mechanism against noise.

The default DI value for confirming start of touch and end of touch is described in

Section 6.5: Capacitive sensing characteristics on page 30.

3.6

3.7

Self-calibration

On power-up, all keys are self-calibrated to provide reliable operation under almost any

conditions. For calibration duration (t

characteristics on page 30.

), please refer to Section 6.5: Capacitive sensing

CAL

Fast positive recalibration

The device autorecalibrates a key when its signal reflects a decrease in capacitance higher

than a fixed threshold (PosRecalTh). In this case, the device recalibrates after approximately

t

so as to recover normal operation quickly.

PosRecal

8/38

QST108

QST touch sensing technology

3.8

Forced key recalibration

A recalibration of the device may be issued at any time by sending to the QST device the

2

appropriate I C command or by tying the RESET pin to ground.

2

It is possible to recalibrate independently any individual key using an I C command.

3.9

Max On-Duration

The device can time out and automatically recalibrate each key independently after a fixed

duration of continuous touch detection. This prevents the keys from becoming ‘stuck on’ due

to foreign objects or other sudden influences. This is known as the Max On-Duration feature.

After recalibration, the key will continue to function normally, even if partially or fully

obstructed. Max On-Duration works independently per channel: a timeout on one channel

has no effect on another channel.

Infinite timeout is useful in applications where a prolonged detection can occur and where

the output must reflect the detection no matter how long. In infinite timeout mode, the

designer should take care to ensure that drift in C , C , and V do not cause the device to

S

X

DD

remain “stuck on” inadvertently even when the touching object is removed from the sense

field. Timeout durations are not accurate and can vary substantially depending on V and

DD

temperature values, and should not be relied upon for critical functions.

3.10

Drift compensation

Signal drift can occur because of changes in C , C , and V over time. Depending on the

X

S

DD

C type and quality, the signal may vary substantially with temperature and veiling. If keys

S

are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that

drift be compensated, otherwise false detections, non detections, and sensitivity shifts will

follow.

Drift compensation slowly corrects the reference level of each key while no detection is in

effect. The rate of reference adjustment must be performed slowly or else legitimate

detections can also be ignored. The device compensates drift on each channel

independently using a maximum compensation rate to the reference level.

Once a touch is sensed, the drift compensation mechanism ceases since the signal is

legitimately high, and therefore should not cause the reference level to change.

The signal drift compensation is “asymmetric”: the reference level compensates drift in one

direction faster than it does in the other. Specifically, it compensates faster for decreasing

signals than for increasing signals. Increasing signals should not be compensated for

quickly, since an approaching finger could be compensated for partially or entirely while

approaching the sense electrode. However, an obstruction over the sense pad, for which the

sensor has already made full allowance, could suddenly be removed leaving the sensor with

an artificially elevated reference level and thus become insensitive to touch. In this latter

case, the sensor will compensate for the object's removal very quickly, usually in only a few

seconds.

Increasing C or decreasing C values will slow down drift compensation.

S

X

9/38

QST touch sensing technology

QST108

3.11

Adjacent key suppression (AKS™)

Adjacent key suppression (AKS™) is a Quantum-patented feature which prevents multiple

keys from responding to a single touch. This can happen with closely spaced keys, or a

scroll wheel that has buttons very near it.

AKS operates by comparing signal strengths from keys within a group of keys to suppress

touch detections from those that have a weaker signal change than the dominant one.

The QST108 supports two AKS algorithms:

●

Locking AKS

Once a key is considered as “touched”, all other keys are locked in an untouched state.

To unlock these keys, the touched key must return to an untouched state. Then, the key

having the highest signal level is declared as the “touched” one.

●

Unlocking AKS

On each acquisition, the signal strengths from each key are compared and the key with

the highest signal level is declared as the “touched” one.

2

In I C mode, up to 8 AKS groups can be specified.

10/38

QST108

Device operating modes

4

Device operating modes

4.1

Mode selection

The device options are configured by connecting pull-up or pull-down resistors on OPTn

pins. The device operating mode is selected using option pin 1 (OPT1) while the device

settings are configured using option pins OPT2 to OPT6 (Table 3). Option pins are sampled

at power-up and after a reset.

To fit most applications, the QST108 device offers two different operating modes:

●

Stand-alone mode

This mode allows the user to simply replace existing mechanical switches with a

capacitive sensing solution. It is designed for maximum flexibility and can

accommodate most popular sensing requirements via option resistors (AKS, Low

power, Max On-Duration and output modes).

In this mode, the 8 output pins reflect the status of the 8 sensing channels.

2

●

I C mode

2

In this mode, which is the most open one, the device is driven using the I C interface.

To avoid polling, the QST device features an output interrupt pin (IRQ). The IRQ line

reports all key changes to the Master device. The QST (Slave) device can drive up to

five general-purpose outputs.

Table 3.

Operating modes

Option resistor function

OPT1: Mode selection

OPT2

OPT3

OPT4

OPT5

OPT6

Pin OPT1 is high at start-up Stand-alone mode

Pin OPT1 is low at start-up I²C mode

AKS

LP

MOD_0 MOD_1

OM

ADD0

ADD1

ADD2 Unused Unused

4.2

Reset and power-up

At power-up, the device configures itself according to the pull-up or pull-down option

resistors present on pins OPT1 to OPT6. The device start-up and configuration may take up

to t

.

Setup

When the power is established, it is possible to force a new device configuration by applying

a negative pulse on the RESET pin.

The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the

device resets itself (through an I²C command, for example).

A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise

immunity.

11/38

Device operating modes

QST108

4.3

Burst operation

The device operates in “Burst” mode. Each key touch is acquired using a burst of charge-

transfer sensing pulses whose count varies depending on the value of the sense capacitor

C and the load capacitance C . Key touches are acquired using two successive bursts of

S

X

pulses:

●

Burst A: Keys 1, 2, 3, and 4

Burst B: Keys 5, 6, 7, and 8

●

Bursts always operate in an A-B sequence. If Keys 5 to 8 are not implemented, the QST

device will not perform the Burst B to improve the response time and reduce the power

consumption when in Low Power (LP) mode.

In Low Power mode, the device sleeps in an ultra-low current state between bursts to

conserve power.

4.4

Stand-alone mode

This mode allows the user to simply replace existing mechanical switch interface with a

capacitive sensing solution. It is designed for maximum flexibility and can accommodate

most popular sensing requirements via option resistors (see Figure 3).

4.4.1

Main features

●

Pins KOUT1 to KOUT8 directly reflect the state of keys

Selectable global adjacent key suppression (AKS™)

Selectable sleep duration

Selectable Max On-Duration values

Selectable BCD mode

12/38

QST108

Device operating modes

Figure 3.

Stand-alone mode typical schematic

V_DD

2.4~5.5V

Volt. Reg.

V_UNREG

100nF

4.7µF

8

13

V_{DD_1}

V_{DD_2}

Keep these parts close to IC

R_S8

6

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET

To Host

Key8

Key7

Key6

Key5

Key4

Key3

Key2

SNSK_SCK8

SNS_SCK8

SNSK_SCK7

SNS_SCK7

SNSK_SCK6

SNS_SCK6

SNSK_SCK5

SNS_SCK5

SNSK_SCK4

SNS_SCK4

SNSK_SCK3

SNS_SCK3

SNSK_SCK2

SNS_SCK2

10kΩ

10nF

C_S8

C_S7

C_S6

C_S5

C_S4

C_S3

C_S2

R_S7

10kΩ

V_DDV_DD

47kΩ

R_S6

10kΩ

5

4

3

KOUT8

KOUT7

R_S5

10kΩ

KOUT7

OM/KOUT6

KOUT6

V_DD

V_SS

R_S4

10kΩ

1MΩ

2

MOD_1/KOUT5

MOD_0/KOUT4

LP/KOUT3

KOUT5

V_DD

V_SS

R_S3

10kΩ

1

KOUT4

V_DD

V_SS

Binary-

coded

Output

Mode

R_S2

32

31

30

KOUT3

V_DD

V_SS

10kΩ

AKS/KOUT2

KOUT2

V_DD

V_SS

R_S1

10kΩ

15

14

Key1

SNSK_SCK1

SNS_SCK1

C_S1

MODE/KOUT1

KOUT1

V_DD

V_{SS_1}

V_{SS_2}

V_{SS_3}

V_{SS_4}

12

9

10

11

Ai12560

13/38

Device operating modes

QST108

4.4.2

Option descriptions

Adjacent key suppression (AKS™)

The QST108 features an adjacent key suppression (AKS™) function.

This function is enabled using the AKS option resistor (OPT2) in standard output mode as

described in Table 4. In BCD output mode, the AKS function is always enabled, regardless

of the option resistor configuration.

Table 4.

AKS truth table

OPT2/AKS

Description

V_SS

V_DD

Disabled

Global locking AKS on all available keys

Low Power mode option

This option resistor (OPT3) selects whether the device is always sensing the keys or if a low

power consumption phase is introduced between bursts as described in Table 5.

In Low Power mode, a very low consumption (sleep) phase of 100ms is inserted between

the Group B burst and the Group A burst. This significantly reduces the overall consumption

of the device. Sleep duration is not accurate and can vary substantially depending on V

and temperature values.

DD

Note:

In Low Power mode, the response time is increased.

Table 5.

Low power (LP) mode truth table

OPT3/LP

Description

V_SS

V_DD

Free running mode

100ms sleep duration

Max On-Duration

There are four recalibration timing options (“Max On-Duration”). The recalibration option

resistors (OPT4 and OPT5) control how long it takes for a continuous detection to trigger a

recalibration on a key as described in Table 6. When such an event occurs, only the “stuck”

key is recalibrated.

Table 6.

Max On-Duration (MOD) truth table

OPT4/MOD_0 OPT5/MOD_1

Description

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

Infinite

60s

20s

10s

14/38

QST108

Device operating modes

Output mode option

The QST108 offers several outputs mode to fit any existing application.

Table 7.

OPT6/OM

Output mode (OM) truth table

Description

V_SS

V_DD

Individual key state output mode: One output per sensing channel

BCD output mode: Binary-coded touched key number (see Table 8)⁽¹⁾

1. In BCD mode, the AKS function is always active.

Table 8.

Binary code truth table

KOUT4 KOUT3 KOUT2 KOUT1

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

All released

Key 1 pressed

Key 2 pressed

Key 3 pressed

Key 4 pressed

Key 5 pressed

Key 6 pressed

Key 7 pressed

Key 8 pressed

Not used

Other

4.5

I²C mode

2

The I C mode offers the largest configurability and functionality of the QST108.

4.5.1

Main features

●

Five general-purpose outputs

Configuration of up to 8 AKS groups

Additional low power modes

Accessible internal capacitive sensing parameters

Continuous range of Max On-Duration

15/38

Device operating modes

Figure 4.

QST108

2

I C mode typical schematic

V_DD

2.4~5.5V

Volt. Reg.

V_UNREG

100nF

4.7µF

8

13

V_DD

V_{DD_1}V_{DD_2}

Keep these parts close to IC

R_S8

29

Key8

SNSK_SCK8

10kΩ

R_S7

10kΩ

R_S6

10kΩ

R_S5

10kΩ

R_S4

10kΩ

R_S3

10kΩ

R_S2

10kΩ

R_S1

10kΩ

C_S8

C_S7

C_S6

C_S5

C_S4

C_S3

C_S2

C_S1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

SNS_SCK8

SNSK_SCK7

SNS_SCK7

SNSK_SCK6

SNS_SCK6

SNSK_SCK5

SNS_SCK5

SNSK_SCK4

SNS_SCK4

SNSK_SCK3

SNS_SCK3

SNSK_SCK2

SNS_SCK2

SNSK_SCK1

SNS_SCK1

5

4

3

I2C_SCL

I2C_SDA

IRQ

To

Host

MCU

Key7

Key6

Key5

Key4

Key3

Key2

Key1

6

RESET

To Host

GPO5

10nF

2

GPO5

ADD2/GPO4

ADD1/GPO3

ADD0/GPO2

MODE/GPO1

1

GPO4

V_DD

V_SS

1MΩ

32

31

30

GPO3

V_DD

V_SS

GPO2

V_DD

V_SS

GPO1

V_SS

V_{SS_1}V_{SS_2}V_{SS_3}V_{SS_4}

9

10

11

12

Ai12559

4.5.2

General-purpose outputs

2

I C mode allows to drive up to 5 general purpose outputs. Theses output pins are

configured in output push pull mode 0 by default. Their state can be changed using a

2

specific I C command.

16/38

QST108

Device operating modes

4.5.3

IRQ pin

2

The IRQ pin is an open drain output with an internal pull-up. This pin (available in I C mode

only) can be used to inform the Master device about any change in the key status. The IRQ

line is pulled low every time the state of any of the enabled keys changes. This includes any

change in the touch state of the key or faulty key. The reported changes may then be

accessed by the Master device by using the GET_KEY_STATE command.

To improve communication response time, this signal suspends Low Power mode until the

Master device has issued a communication with the QST device.

4.5.4

Communication packet

The communication between the Master device and the QST108 (Slave) consists of two

2

standard I C frames.

The first frame is sent by the Master device using the QST108 device address with the write

bit set. The data bytes consist of the command byte which is eventually followed by the

parameters and a checksum byte.

The second one is sent by the Master device using the QST108 device address with the

write bit reset. The QST108 complete the frame with data according to the command

previously sent by the Master device. The device finishes the frame by sending a checksum

byte for communication integrity verification.

The QST108 slave address is programmable using the option resistors mapped on pins

OPT2 to OPT4 (see Table 9).

If the read frame is omitted, the command may not be taken into account.

To initiate the communicate with the QST108, the Master device must send the

GET_DEVICE_INFO command in order to unlock access to all the other commands.

Table 9.

I²C address versus option resistor

Option configuration

I²C Address

ADD1

OPT4

OPT3

OPT2

ADD[6:3]

ADD2

ADD0

Hex value

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

V_SS

V_DD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0101

17/38

Device operating modes

Figure 5.

QST108

Optional LED schematic

V_UNREG

R

GPOn

C (10 nF)

Ai12570

4.5.5

Supported commands

Table 10 lists the supported I²C commands and available arguments.

2

Note:

For more information on the supported commands and I C protocol, please refer to the QST

standard communication protocol reference manual.

Table 10. Supported commands

I²C commands

Description

RESET_DEVICE

Write

Read

0xFD

Restarts the device (options Read and Calibration) after

reading the ErrCode (see Table 11).

ErrCode

GET_DEVICE_INFO

Write

0x85

Returns the QST108 device version and ASCII-coded device

name. This command must be sent first to enable the

communication flow.

0x15 MainVers SubVers

NbSCkey NbMCkey

MainVers: Device main version

SubVer: Device sub-version

NbSCkey: 0x08 single-channel keys

NbMCkey: 0x00 multi-channel keys

Q S T 1 0 8: ASCII-coded device name

Read

‘Q’ ’S’ ‘T’ ‘1’ ‘0’ ‘8’

Checksum

GET_PROTOCOL_VERSION

Write

0x80

Returns the QST108 protocol version.

MainVers: Protocol main version

SubVer: Protocol sub-version

MainVers SubVer

I2CSpeed Checksum

Read

I2CSpeed: 0x01 (400 kHz maximum)

CALIBRATE_KEY (All keys)

Write

Read

0x98

Forces the recalibration of all keys.

ErrCode: Standard Error code (see Table 11)

ErrCode

18/38

QST108

Device operating modes

Table 10. Supported commands (continued)

I²C commands

Description

CALIBRATE_KEY (Single key)

Write

Read

0x9B KeyID Checksum Forces the recalibration of a single key.

KeyId: Binary-coded key number (see Table 14)

ErrCode: Standard Error code (see Table 11)

ErrCode

GET_KEY_STATE

Write

0xC1

Returns the state of all keys.

AllKeyState: Touched/untouched state for all 8 keys. Refer to

Table 13: AllKeyState.

KeyError: Refer to Table 12: KeyError byte description

0x03 AllKeyState

KeyError Checksum

Read

GET_DEBUG_INFO

Write

0xF4 Checksum

Returns the debug info of all keys.

KeyDbgState: Current Key Debug state (see Table 18)

RefMSB: Reference Count MSB

RefLSB: Reference Count LSB

BCMSB: Burst Count MSB

0x0D KeyDbgState1

RefMSB1 RefLSB1

BCMSB1 BCLSB1 ...

RefMSB8 RefLSB8

BCMSB8 BCLSB8

Checksum

Read

BCLSB: Burst Count LSB

SET_KEY_ACTIVATION

0x97 KeyActivation

Checksum

Enables or disables a single key.

Write

Read

KeyActivation: Byte containing the key number selection and

requested state.

ErrCode: Standard Error code (see Table 11)

ErrCode

SET_MAX_ON_DURATION

0x8A MaxOnDuration

Checksum

Sets the maximum detected ON time before triggering an

automatic recalibration.

Write

MaxOnDuration: Time, in second (0 for infinite)

ErrCode: Standard Error code (see Table 11)

Read

ErrCode

SET_LOW_POWER_MODE

0x92 LowPowerMode

Checksum

Selects standard or Low Power mode.

Write

LowPowerMode: Configure Low Power mode (see Table 15)

ErrCode: Standard Error code (see Table 11)

Read

ErrCode

SET_GPIO_STATE

0x9E GPOState

Checksum

Controls the state of the general-purpose outputs.

GPOState: State of general-purpose outputs

ErrCode: Standard Error code (see Table 11)

Write

Read

ErrCode

19/38

Device operating modes

Table 10. Supported commands (continued)

QST108

I²C commands

Description

SET_SCKEY_PARAMETERS

0x01 0X04 KeyID DeTh Sets the Detection, End Of Detection and Positive

Write

Read

EofDeTh PosRecalTh

Checksum

Recalibration Thresholds for a single key.

KeyID: 0x00 (settings applied to all keys)

DeTh: Detection Threshold

EofDeTh: End of Detection Threshold

PosRecalTh: Positive Recalibration Threshold

ErrCode: Standard Error code (see Table 11)

ErrCode

SET_KEY_GROUP

0x00 0x09

AKSGrpMode Key1Grp

Defines the AKS groups for each key.

Key2Grp Key3Grp

Key4Grp Key5Grp

Key6Grp Key7Grp

Key8Grp CheckSum

AKSGrpMode: AKS mode selection of each group (see

Table 16)

KeynGrp: AKS group selection for key n (see Table 17)

ErrCode: Standard Error code (see Table 11)

Write

Read

ErrCode

SET_SYSTEM_INTEGRATORS

0x03 0x04 KeyID DI EDI Sets the detection, End Of Detection and Positive Recalibration

Write

Read

PosRecaI CheckSum

Integrators for all keys.

KeyID: 0x00 (settings applied to all keys)

DI: Detection Integrator

EDI: End of Detection Integrator

PosRecaI: Positive Recalibration Integrator

ErrCode: Standard Error code (see Table 11)

ErrCode

GET_KEY_ERROR

Write

0xC4

Returns the error information on each key.

0x11 KeyError1

KeyError2 ... KeyError8

CheckSum

KeyErrorN: KeyError byte description (see Table 12)

Read

Error codes

2

Table 11 lists the I C error codes.

Table 11. ErrCode

ErrCode

Description

0x01

0x83

0x85

0xA1

0xA3

0xE0

No Error

Command not Supported

Parameter not Supported

Parity Error

Checksum Error

Initialization process

20/38

QST108

Device operating modes

KeyError byte description

Table 12. KeyError byte description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Key State

0

Key error codes

Key state (Bit 7)

When set to ‘1’, the corresponding key is touched. This bit is always cleared for the

Get_Key_State command.

Key error codes (Bits 2:0)

Key error code describes the errors in the system on all keys.

Bit 0: When set to ‘1’, calibration in progress

Bit 1: When set to ‘1’, maximum count reached

Bit 2: When set to ‘1’, minimum count not reached

All key state description

Table 13. AllKeyState

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Key 8 State Key 7 State Key 6 State Key 5 State Key 4 State Key 3 State Key 2 State Key 1 State

Key n state

When set to ‘1’, the corresponding key is touched.

Key activation description

Table 14. KeyActivation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Key

Activation

0

Key ID (binary coded)

Key activation (Bit 7)

0: Key enabled

1: Key disabled

Key identifier (Bits 3:0)

0000: All keys

0001: Key 1

0010: Key 2

0011: Key 3

0100: Key 4

0101: Key 5

0110: Key 6

0111: Key 7

1000: Key 8

21/38

Device operating modes

QST108

Low power mode description

Table 15. SetLowPower

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Free Run

in Detect

0

Sleep Duration Factor

Free Run in Detect (Bit 6)

1: Low power mode is suspended when detection is on-going.

0: Low power mode is authorized.

Sleep Duration Factor (Bits 5 to 0)

This value is between 1 and 62, in hexadecimal format. The Sleep duration is ‘Sleep

Duration Factor’ x 20 milliseconds.

0x00: Low power mode is disabled.

0x3F: Sleep is entered immediately with an infinite duration (deep sleep).

2

Note:

1

2

When the device is in sleep, any I C bus activity will wake up the device. If many ‘sleeping’

devices share the same bus, then any bus activity will wake up all of them.

The command sent to wake up the device is always lost (not acknowledged). The Master

device will have to repeat this command.

AKS group mode description

Table 16. AKSGrpnMode

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AKSGrp8 AKSGrp7 AKSGrp6 AKSGrp5 AKSGrp4 AKSGrp3 AKSGrp2 AKSGrp1

Mode

AKSGrpnMode

Defines the type of AKS for the Group n:

0: Locking AKS

1: Unlocking AKS

AKS group selection description

Table 17. KeynGrp

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Grp8

Grp7

Grp6

Grp5

Grp4

Grp3

Grp2

Grp1

Grpx

The selected key is a member of AKS Group x.

22/38

QST108

Device operating modes

Key debug state description

Table 18. KeyDbgState

Value

Description

0x01

0x02

0x04

0x08

0x11

0x14

0x18

0x24

On-going calibration

Key released

Key touched

Key in error

Key in pre-calibration

Key in pre-detect

Key in pre-error

Key in post-detect

23/38

Design guidelines

QST108

5

Design guidelines

5.1

C_Ssense capacitor

The C sense capacitors accumulate the charge from the key electrodes and determine

S

sensitivity. Higher values of C make the corresponding sensing channel more sensitive.

S

The values of C can differ for each channel, permitting differences in sensitivity from key to

S

key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and

placement differences and stray wiring capacitances. More stray capacitance on a sense

trace will desensitize the corresponding key. Increasing the C for that key will compensate

S

for the loss of sensitivity.

The C capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor.

S

The normal C range is 1nF to 50nF depending on the sensitivity required: larger values of

S

C require better quality to ensure reliable sensing. In certain circumstances the normal C

range may be exceeded. Acceptable capacitor types for most uses include PPS film,

S

polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are

not recommended.

5.2

Sensitivity tuning

Sensitivity can be altered to suit various applications and situations on a channel-by-

channel basis. The easiest and most direct way to impact sensitivity is to alter the value of

each C : more C yields higher sensitivity. Each channel has its own C value and can

S

therefore be independently adjusted.

5.2.1

5.2.2

Increasing sensitivity

Sensitivity can also be increased by using larger electrode areas, reducing panel thickness,

or using a panel material with a higher dielectric constant.

Decreasing sensitivity

In some cases the circuit may be too sensitive. Gain can be lowered further by a number of

strategies:

●

making the electrode smaller

making the electrode into a sparse mesh using a high space-to-conductor ratio

decreasing the C capacitors

S

5.2.3

Key balance

A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can

have differing stray amounts of capacitance to ground. Increasing load capacitance will

cause a decrease in gain. Key size differences, and proximity to other metal surfaces can

also impact gain.

The keys may thus require “balancing” to achieve similar sensitivity levels. This can be best

accomplished by trimming the values of the C capacitors to achieve equilibrium. The R

S

resistors have no effect on sensitivity and should not be altered. Load capacitances to

ground can also be added to overly sensitive channels to reduce their gain.

These should be in the order of a few picofarads.

24/38

QST108

Design guidelines

5.3

Power supply

If the power supply fluctuates slowly with temperature, the QST device compensates

automatically for these changes with only minor changes in sensitivity. However, if the

supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep

up, causing sensitivity anomalies or false detections.

The power supply should be locally regulated, using a three-terminal regulator. If the supply

is shared with another electronic system, care should be taken to ensure that the supply is

free of digital spikes, sags and surges which can cause adverse effects. It is not

recommended to include a series inductor in the power supply to the QST device.

For proper operation, a 0.1 µF or greater bypass capacitor must be used between V and

DD

V

. The bypass capacitor should be routed with very short tracks to the device’s V and

pins.

SS

DD

The PCB should, if possible, include a copper pour under and around the device, but not

extensively under the SNS lines.

5.4

5.5

ESD protection

In normal environmental conditions, only one series resistor is required for ESD

suppression. A 10 kOhm R resistor in series with the sense trace is sufficient in most

cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to

prevent ESD discharge from reaching the circuit. R should be placed close to the chip. If

S

the C load is high, R can prevent total charge and transfer and as a result gain can

X

S

deteriorate. If a reduction in R increases gain noticeably, the lower value should be used.

Conversely, increasing the R can result in added ESD and EMC benefits, provided that the

increase does not decrease sensitivity.

S

Crosstalk precautions

Adjacent sense traces might require intervening ground traces in order to reduce capacitive

cross bleed if high sensitivity is required or high values of delta-C are anticipated (for

X

example, from direct human touch to an electrode connection). In normal touch applications

behind plastic panels, this is rarely a problem regardless of how the electrodes are wired.

Higher values of R will make crosstalk problems worse; try to keep R to 22 kOhm or less

S

if possible. In general try to keep the QST device close to the electrodes and reduce the

adjacency of the sense wiring to ground planes and other signal traces; this will reduce the

C load, reduce interference effects, and increase signal gain. The one and only valid

x

reason to run ground near SNS traces is to provide crosstalk isolation between traces, and

then only on an as-needed basis.

5.6

PCB layout and construction

The PCB traces, wiring, and any components associated with or in contact with either SNS

pin will become touch sensitive and should be treated with caution to limit the touch area to

the desired location.

Multiple touch electrodes connected to any sensing channel can be used, for example, to

create control surfaces on both sides of an object.

25/38

Design guidelines

QST108

It is important to limit the amount of stray capacitance on the SNS terminals, for example by

minimizing trace lengths and widths to allow for higher gain without requiring higher values

of C . Under heavy delta-C loading of one key, cross coupling to another key’s trace can

S

X

cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be

run close to each other over long runs in order to minimize cross-coupling if large values of

delta-C are expected, for example when an electrode is directly touched. This is not a

X

problem when the electrodes are working through a plastic panel with normal touch

sensitivity.

For additional information on PCB layout and construction, please contact your local ST

Sales Office for a list of available application notes.

26/38

QST108

Electrical characteristics

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

6.1.1

Minimum and Maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max. (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

6.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the 4.5V ≤

A

DD

V

≤ 5.5 V voltage range) and V = 3.3 V (for the 3.0 V ≤ V ≤ 3.6 V voltage range).

DD

DD DD

They are given only as design guidelines and are not tested.

6.1.3

6.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 6.

Figure 6.

Pin loading conditions

Output pin

C

L

27/38

Electrical characteristics

QST108

6.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7.

Figure 7. Pin input voltage

Input pin

V

IN

6.2

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 19. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

−65 to +150

°C

Table 20. Voltage characteristics

Symbol

Ratings

Maximum value

Unit

V_DD− V_SSSupply voltage

7.0

V_SS−0.3 to V_DD+0.3

2000

V_IN

Input voltage on any pin ⁽¹⁾⁽²⁾

V

V_ESD(HBM)Electrostatic discharge voltage (Human Body Model)

V_ESD(CDM)Electrostatic discharge voltage (Charge Device Model)

500

1. Directly connecting the RESET and I/O pins to V_DDor V_SScould damage the device if an unintentional

internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a

corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up

or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os).

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be

respected.

28/38

QST108

Electrical characteristics

Table 21. Current characteristics

Symbol

Ratings

Maximum value

Unit

I_VDD

I_VSS

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by RESET pin

Output current sunk by output pin

75

150

20

40

− 25

5

I_IO

mA

Output current source by output pin

Injected current on RESET pin

(2)

I_INJ(PIN)

(3)

Injected current output pin

5

(2)

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)

20

1. All power (V_DD) and ground (V_SS) lines must always be connected to the external supply.

2. I_INJ(PIN)must never be exceeded. This is implicitly ensured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. For true open-drain

pads, there is no positive injection current, and the corresponding V_INmaximum must always be

respected.

3. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterisation with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

6.3

6.4

Operating conditions

Table 22. Operating conditions

Symbol

Feature

Value

Unit

V_DD

T_A

Operating supply voltage

Operating temperature

2.4 to 5.5

V

C

-40° to +85°

Supply current characteristics

Table 23. Supply current characteristics

Symbol

Parameter

Conditions

V_DD= 2.4 V

_DD= 3.3 V

Min.

Typ. ⁽¹⁾Max.

Unit

1.61

2.15

3.15

286

340

497

Average suppy current

Free Run mode

I_DD(FR)

V

mA

V_DD= 5 V

V_DD= 2.4 V

V_DD= 3.3 V

V_DD= 5 V

I_DD

(Sleep

100ms)

Average suppy current

100ms Sleep mode

µA

1. The results are based on C_S= 2.7nF and C_X= 12.5pF

29/38

Electrical characteristics

QST108

6.5

Capacitive sensing characteristics

Table 24. External sensing components

Symbol

Parameter

Min.

Typ.

Max.

Unit

C_S

C_X

C_T

R_S

Sense capacitor

100

nF

pF

Equivalent electrode capacitor

Equivalent touch capacitor

Serial resistance

5

pF

10

22

kOhm

Table 25. Capacitive sensing parameters

Symbol

Parameter

Calibration duration

Min.

Typ.

Max.

Unit

t_CAL

t_Setup

TBD

ms

Setup duration

TBD

2

DI

Default detection integrator

Counts

s

DeTh

Default detection threshold

– 10

2

EDI

Default end of detection integrator

Default end of detection threshold

Default positive recalibration integrator

Default positive recalibration threshold

Positive recalibration delay

EofDeTh

PosRecal

PosRecalTh

t_PosRecal

– 8

2

6

TBD

Infinite

TBD

MaxOnDuration Default max on-duration delay

s

PosDiffDrift

NegDiffDrift

Positive differential drift compensation rate

Negative differential drift compensation rate

ms/level

PosComDrift Positive common drift compensation rate

NegComDrift Negative common drift compensation rate

BurstCount

Burst length

20

2000 Counts

30/38

QST108

Electrical characteristics

6.6

KOUTn/OPTn/GPOn pin characteristics

6.6.1

General characteristics

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 26. General characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

V_IL

Input low level voltage ⁽¹⁾

V_SS−0.3

0.3x V_DD

V

V_DD

0.3

+

V_IH

Input high level voltage ⁽¹⁾

0.7x V_DD

V_Hys

I_L

Schmitt trigger voltage hysteresis⁽²⁾

Input leakage current

400

mV

μA

pF

V_SS≤ V_IN≤ V_DD

1

C_IO

I/O pin capacitance

5

C_L= 50 pF

t_f(IO)outOutput high to low level fall time ⁽²⁾Between 10%

and 90%

25

ns

t_r(IO)outOutput low to high level rise time ⁽²⁾

1. Not tested in production, guaranteed by characterization.

2. Data based on validation/design results.

6.6.2

Output pin characteristics

Subject to general operating conditions for V , f

, and T unless otherwise specified.

A

DD CPU

Table 27. Output pin current

Symbol

Parameter

Conditions

I_IO

Min.

Max.

Unit

=

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time (see

Figure 13)

1.3

(1)

+20mA

V_OL

I_IO= +8mA

0.75

Output high level voltage for an I/O pin when

4 pins are sourced at same time (see

Figure 18)

I_IO= -5mA V_DD−1.5

_IO= -2mA V_DD−0.8

(2)

V_OH

I

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time

(1)(3)

V_OL

I_IO= +8mA

_IO= -2mA V_DD−0.8

0.5

0.6

V

Output high level voltage for an I/O pin when

4 pins are sourced at same time (Figure 16)

(2)(3)

V_OH

I

Output low level voltage for a high sink I/O

pin when 4 pins are sunk at same time

(1)(3)

V_OL

I_IO= +8mA

Output high level voltage for an I/O pin when

4 pins are sourced at same time

(2)(3)

V_OH

I_IO= -2mA V_DD−0.9

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 21 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced must always respect the absolute maximum rating specified in Table 21 and the

sum of I_IO(output and RESET pins) must not exceed I_VDD..

3. Not tested in production, based on characterization results.

31/38

Electrical characteristics

QST108

Figure 8.

Typical V_OLat V_DD= 2.4 V

Figure 9.

Typical V_OLvs V_DDat I_load= 2 mA

V_OLvs V_DD@I_load=2 mA HS Pins

V_OLvs I_load@ V_DD= 2.4 V HS pins

120

110

100

90

-40°C

25°C

1200

-40°C

25°C

85°C

1000

800

600

400

200

0

125°C

85°C

125°C

80

70

60

50

40

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

I_load[mA]

Figure 10.

Typical V_OLat V_DD= 3 V

Figure 11.

Typical V_OLvs V_DDat I_load= 8 mA

V_OLvs V_DD@I_load= 8 mAHS Pins

V_OLvs I_load@ V_DD= 3 V HS pins

540

490

440

390

340

290

240

190

140

-40°C

25°C

1600

1400

1200

1000

800

600

400

200

0

-40°C

25°C

85°C

125°C

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

18

20

I_load[mA]

Figure 12.

Typical V_OLat V_DD= 5 V

Figure 13.

Typical V_OLvs V_DDat I_load= 12 mA

V_OLvs V_DD@I_load= 12 mA HS Pins

V_OLvs I_load@ V_DD= 5 V HS pins

1040

940

840

740

640

540

440

340

240

140

-40°C

25°C

900

800

700

600

500

400

300

200

100

0

-40°C

25°C

85°C

125°C

85°C

125°C

2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6

V_DD[V]

0

2

4

6

8

10

12

14

16

18

20

I_load[mA]

32/38

QST108

Electrical characteristics

Figure 14.

Typical V_DD-V_OHvs. I_loadat V_DD= 2.4 V Figure 15.

Typical V_DD-V_OHvs. V_DDat I_load= 2 mA

V_DD-V_OHvs I_load@ V_DD= 2.4 V HS Pins

V_DD-V_OHvs V_DD@I_load= 2 mA HS Pins

800

700

600

500

400

300

200

100

0

800

-40°C

25°C

85°C

125°C

-40°C

25°C

700

600

500

400

300

200

100

0

85°C

125°C

V_DD[V]

2

4

I_load[mA]

Figure 16.

Typical V_DD-V_OHvs. I_loadat V_DD= 3 V

Figure 17.

Typical V_DD-V_OHvs. V_DDat I_load= 4 mA

V_DD-V_OHvs I_load@ V_DD= 3 V HS Pins

V_DD-V_OHvs V_DD@I_load= 4 mA HS Pins

1800

1600

1400

1200

1000

800

1800

1600

1400

1200

1000

800

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

600

400

600

200

400

0

200

0

V_DD[V]

0

2

4

6

I_load[mA]

Figure 18.

Typical V_DD-V_OHvs. I_loadat V_DD= 5 V

V_DD-V_OHvs I_load@ V_DD= 5 V HS Pins

4500

4000

3500

3000

2500

2000

1500

1000

500

-40°C

25°C

85°C

125°C

0

2

4

6

8

10

12

14

I_load[mA]

33/38

Electrical characteristics

QST108

6.7

RESET pin

T = -40°C to 125°C, unless otherwise specified.

A

Table 28. RESET pin characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

V_IL

V_IH

Input low level voltage

Input high level voltage

V_SS− 0.3

0.3x V_DD

V_DD+ 0.3

V

0.7 x V_DD

Schmitt trigger voltage

hysteresis⁽¹⁾

V_hys

V_OL

2

V

Output low level

voltage⁽²⁾

V_DD= 5V I_IO= +2mA

200

TBD

70

mV

V_DD= 5V

V_IN= V_SS

30

20

50

Pull-up equivalent

resistor⁽³⁾

R_ON

kΩ

μs

V_DD= 3V

90⁽¹⁾

Generated reset pulse

duration

t_w(RSTL)out

Internal reset sources

90⁽¹⁾

External reset pulse

hold time⁽⁴⁾

t_h(RSTL)in

μs

t_g(RSTL)inFiltered glitch duration

200

ns

1. Data based on characterization results, not tested in production.

2. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 21: Current

characteristics on page 29 and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

3. The R_ONpull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin

between V_ILmaxand V_DD

.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses

applied on RESET pin with a duration below t_h(RSTL)incan be ignored.

34/38

QST108

Electrical characteristics

I²C control interface

6.8

Subject to general operating conditions for V , and T unless otherwise specified.

DD

A

2

The QST108 I C interface meets the requirements of the Standard I C communication

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Table 29. I²C characteristics

Standard mode

Fast mode

Symbol

Parameter

Unit

Min. ⁽¹⁾Max. ⁽¹⁾Min. ⁽¹⁾Max. ⁽¹⁾

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

1.3

0.6

µs

ns

250

0 ⁽³⁾

100

0 ⁽²⁾

t_h(SDA)

SDA data hold time

900 ⁽³⁾

300

t_r(SDA)

t_r(SCL)

SDA and SCL rise time

1000

300

ns

µs

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

300

t_h(STA)

START condition hold time

4.0

4.7

4.0

4.7

0.6

1.3

t_su(STA)

Repeated START condition setup time

t_su(STO)STOP condition setup time

μs

µs

pF

t_w(STO:STA)STOP to START condition time (bus free)

C_b

Capacitive load for each bus line

400

Data based on standard I²C protocol requirement, not tested in production.

1.

2. The device must internally proivde a hold time of at least 300ns for the SDA signal in order to bridge the

undefined region of the falling esdge of the SCL signal.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low

period of the SCL signal.

2

Typical application with I C bus and timing diagram

Figure 19.

V

DD

4.7kΩ

100Ω

SDA

SCL

2

I C BUS

QST108

REPEATED START

START

t

w(STO:STA)

su(STA)

START

SDA

t

r(SDA)

f(SDA)

STOP

t

h(SDA)

su(SDA)

SCL

t

su(STO)

t

h(STA)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

35/38

Package mechanical data

QST108

7

Package mechanical data

Figure 20. 32-Pin Low Profile Quad Flat Package (7x7) outline

D

A

D1

A2

A1

e

E

E1

b

c

L1

L

h

Table 30. 32-Pin Low Profile Quad Flat Package mechanical data

mm

inches⁽¹⁾

Dim.

Min.

Typ.

Max.

Min.

Typ.

Max.

A

A1

A2

b

1.60

0.15

1.45

0.45

0.20

0.063

0.006

0.057

0.018

0.008

0.05

1.35

0.30

0.09

0.002

0.053

0.012

0.004

1.40

0.37

0.055

0.015

C

D

9.00

7.00

9.00

7.00

0.80

3.5°

0.60

1.00

0.354

0.276

0.354

0.276

0.031

3.5°

D1

E

E1

e

θ

0°

7°

0°

7°

L

0.45

0.75

0.018

0.024

0.039

0.030

L1

Number of Pins

32

N

1. Values in inches are converted from mm and rounded to 3 decimal digits.

36/38

QST108

Revision history

8

Revision history

Table 31. Document revision history

Date

Revision

Changes

8-Jun-2007

1

2

Initial release.

15-Jun-2007

Datasheet status changed to Preliminary Data.

Removed Beeper function.

Changed LED output pins to GPO pins.

Updated pin names and functions in Section 2: Pin description on

page 5.

Added Figure 2: QTouch™ measuring circuitry on page 7.

Changed order of chapters in Section 3 for better comprehension.

Removed Simplified independent output mode from Section 4:

Device operating modes on page 11. Independent output mode

renamed Stand-alone mode.

Added Section 4.2: Reset and power-up on page 11.

Removed Power supply option chapter from Section 4.4.2: Option

descriptions on page 14.

26-Sep-2007

3

Updated Table 6: Max On-Duration (MOD) truth table on page 14

and Table 7: Output mode (OM) truth table on page 15.

Updated Figure 3: Stand-alone mode typical schematic on page 13

and Figure 4: I2C mode typical schematic on page 16.

Updated Table 9: I²C address versus option resistor on page 17.

Added Figure 5: Optional LED schematic on page 18.

Updated Section 4.5: I2C mode on page 15.

Added Section 5.2.3: Key balance on page 24.

Updated Section 6.4: Supply current characteristics on page 29.

Added Section 6.5: Capacitive sensing characteristics on page 30.

and Section 6.7: RESET pin on page 34.

Updated Table 29: I²C characteristics on page 35.

37/38

QST108

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38/38

厂商	型号	描述	页数
SAMTEC	QST-110-01-F-T	[ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ]	1 页
SAMTEC	QST-110-01-G-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-M-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-S-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-01-S-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-F-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-G-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-G-T-MW	[ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-L-5-MW	[ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ]	1 页
SAMTEC	QST-110-02-L-T	[ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ]	1 页