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THS6182

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SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

LOW-POWER DISSIPATION ADSL LINE DRIVER

FEATURES

DESCRIPTION

•

Low-Power Dissipation Increases ADSL Line

Card Density

The THS6182 is a current feedback differential line

driver ideal for full rate ADSL systems. Its extremely

low-power dissipation is ideal for ADSL systems that

must achieve high densities in ADSL central office

rack applications. The unique architecture of the

THS6182 allows the quiescent current to be much

lower than existing line drivers while still achieving

high linearity without the need for excess open loop

gain. Fixed multiple bias settings of the amplifiers

allow for enhanced power savings for line lengths

where the full performance of the amplifier is not

required. To allow for even more flexibility and power

savings, an I_ADJpin is available to further lower the

bias currents while maintaining stable operation with

as little as 1.8 mA per channel. The wide output

swing of 44 Vpp differentially with ±12-V power

supplies allows for more dynamic headroom, keeping

distortion at a minimum. With a low 3.2 nV/√Hz

voltage noise coupled with a low 10 pA/√Hz inverting

current noise, the THS6182 increases the sensitivity

of the receive signals, allowing for better margins and

reach.

•

Low THD of -88 dBc (100 Ω, 1 MHz)

Low MTPR Driving +20 dBm on the Line

– -76 dBc With High Bias Setting

– -74 dBc With Low Bias Setting

•

Wide Output Swing of 44 V_PPDifferential Into

a 200-Ω Differential Load (V_CC= ±12 V)

•

High Output Current of 600 mA (Typ)

Wide Supply Voltage Range of ±5 V to ±15 V

Pin Compatible with EL1503C and EL1508C

– Multiple Package Options

•

Multiple Power Control Modes

– 11 mA/ch Full Bias Mode

– 7.5 mA/ch Mid Bias Mode

– 4 mA/ch Low Bias Mode

– 0.25 mA/ch Shutdown Mode

– I_ADJPin for User Controlled Bias Current

– Stable Operation Down to 1.8 mA/ch

Low Noise for Increased Receiver Sensitivity

– 3.2 nV/√Hz Voltage Noise

TYPICAL ADSL CO-LINE DRIVER CIRCUIT

USING ACTIVE IMPEDANCE

•

1 k

Ω

– 1.5 pA/√Hz Noninverting Current Noise

– 10 pA/√Hz Inverting Current Noise

+12 V

8.68 Ω

−

APPLICATIONS

CODEC

V_IN+

+

THS6182a

−12 V

•

Ideal for Full Rate ADSL Applications

20-dBm

Line

Power

1.33 kΩ

1:1.2

953 Ω

1.33 kΩ

100

Ω

1 k

Ω

+12V

Ω

8.68

−

CODEC

V_IN−

+

THS6182b

−12 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PRODUCT

PACKAGE

PACKAGE CODE

SYMBOL

ORDER NUMBER

TRANSPORT MEDIA

Tape and reel

(3000 devices)

THS6182RHFR

Leadless 24-pin

4, mm x 5, mm PowerPAD™

THS6182RHF

RHF-24

6182

Tape and reel

(250 devices)

THS6182RHFT

THS6182D

Tube (40 devices)

THS6182D

THS6182DW

THS6182DWP

SOIC-16

SOIC-20

D-16

THS6182

Tape and reel

(2500 devices)

THS6832DR

THS6182DW

THS6182DWR

THS6182DWP

THS6182DWPR

Tube (25 devices)

DW-20

DWP-20

Tape and reel

(2000 devices)

Tube (25 devices)

SOIC-20 PowerPAD

Tape and reel

(2000 devices)

PACKAGE DISSIPATION RATINGS⁽¹⁾

PowerPAD SOLDERED⁽²⁾

θ_JA

PowerPAD NOT SOLDERED⁽³⁾

PACKAGE

θ_JC

RHF-24⁽²⁾

D-16

32°C/W

74°C/W

62.9°C/W

45.4°C/W

43.9°C/W

1.7°C/W

25.7°C/W

16.4°C/W

0.37°C/W

--

DW-20

DWP-20⁽²⁾

21.5°C/W

(1) θ_JAvalues shown are typical for standard test PCBs only.

(2) For high-power dissipation applications, use of the PowerPAD package with the PowerPad on the underside of the chip. This acts as a

heatsink and must be connected to a thermally dissipating plane for proper dissipation. Failure to do so may result in exceeding the

maximum junction temperature which could permanently damage and/or reduce the lifetime the device. See TI technical brief SLMA002

for more information about utilizing the PowerPAD thermally enhanced package.

(3) Use of packages without the PowerPAD or not soldering the PowerPAD to the PCB, should be limited to low-power dissipation

applications.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Dual supply

±5

±12

±15

V_CC+to V_CC-

Supply voltage

V

Single supply

10

24

30

2

THS6182

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SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

ELECTRICAL

THS6132

±16.5 V

±V_CC

V_CC

Supply voltage

V_I

Input voltage

I_O

Output current

1000 mA

±2 V

V_IO

Differential input voltage

THERMAL

Maximum junction temperature, any condition

150°C

T_J

(2)

Maximum junction temperature, continuous operation, long term reliability

Storage temperature

125°C

65°C to 150°C

300°C

T_Sgt

Lead temperature, 1,6 mm (1/16-inch) from case for 10 seconds

ESD

HBM

500 V

1500 V

200 V

ESD ratings

CDM

MM

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may

cause permanent damage. Exposure to absolute-maximum-rated conditions for extended periods may degrade device reliability. These

are stress ratings only, and functional operation of the device at these or any other conditions beyond those ispecified is not implied.

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability and/or lifetime of the device.

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, T_A= 25°C, V_CC= ±12 V, R_F= 2 kΩ,

Gain = +5, I_ADJ= Bias1 = Bias2 = 0 V, R_L= 50 Ω (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

NOISE/DISTORTION PERFORMANCE

Gain =+9.5, 163 kHz to 1.1 MHz DMT,

+20 dBm Line Power, See Figure 1 for circuit

MTPR

Multitone power ratio

-76

-95

dBc

Gain =+5, 25 kHz to 138 kHz with MTPR signal applied,

See Figure 1 for circuit

Receive band spill-over

Differential load = 200 Ω

2^ndharmonic

-88

-70

-107

-84

3.2

1.5

10

dBc

Differential load = 50 Ω

Harmonic distortion, V_O(PP)= 2 V

f = 1 MHz

HD

Differential load = 200 Ω

3^rdharmonic

dBc

Differential load = 50 Ω

V_n

I_n

Input voltage noise

V_CC= ±5 V, ±12 V, ±15 V, f = 100 kHz

nV/√Hz

pA/√Hz

+Input

Input current noise

-Input

R_L= 100 Ω

-65

-60

dBc

f = 1 MHz, V_O(PP)= 2 V,

V_CC= ±5 V, ±12 V, ±15 V

Crosstalk

R_L= 25 Ω

3

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

OUTPUT CHARACTERISTICS

R_L= 100 Ω

±3.9

±3.7

±4.1

±3.9

V_CC= ±5 V

V

R_L= 25 Ω

R_L= 100 Ω

R_L= 25 Ω

±10.7 ±11.0

±10 ±10.6

±13.5 ±13.9

±12.7 ±13.4

±350 ±400

±450 ±600

1000

V_O

Single-ended output voltage swing

V_CC= ±12 V

R_L= 100 Ω

R_L= 25 Ω

V_CC= ±15 V

R_L= 5 Ω

V_CC= ±5 V

V_CC= ±12 V

V_CC= ±15 V

V_CC= ±12 V

(1)

I_O

Output current

mA

R_L= 10 Ω

I_(SC)

Short-circuit current⁽¹⁾

R_L= 1 Ω

mA

Ω

Output resistance

Open-loop

f = 1 MHz,

6

Output resistance—terminate mode

Output resistance—shutdown mode

Gain = +10

Open-loop

0.05

Ω

8.5

kΩ

POWER SUPPLY

Dual supply

±4

±12 ±16.5

V_CCOperating range

V

Single supply

8

24

33

10.7

11.7

12

T_A= 25°C

9.7

V_CC= ± 5 V

V_CC= ± 12 V

V_CC= ±15 V

mA

T_A= full range

T_A= 25°C

Quiescent current (each driver)⁽²⁾

Full-bias mode (Bias-1 = 0,

Bias-2 = 0)

11

T_A= full range

T_A= 25°C

12.5

13

(Trimmed with V_CC= ±12 V at 25°C)

I_CC

11.5

T_A= full range

Mid; Bias-1 - 1, Bias-2 = 0

7.5

4

8.5

5

Quiescent current (each driver)

Variable bias modes, V_CC= ±12 V

Low; Bias-1 = 0, Bias-2 = 1

Shutdown; Bias-1 = 1, Bias-2 = 1

mA

dB

0.25

-56

0.9

T_A= 25°C

-50

-47

-56

-53

V_CC= ±5 V,

∆V_CC= ±0.5 V

T_A= full range

T_A= 25°C

PSRR

Power supply rejection ratio

-60

V_CC= ±12 V, ±15 V,

∆V_CC= ±1 V

T_A= full range

DYNAMIC PERFORMANCE

Gain = +1, RF = 1.2 kΩ

Gain = +2, RF = 1 kΩ

Gain = +5, RF = 1 kΩ

Gain = +10, RF = 1 kΩ

Gain = +1, RF = 1.5 kΩ

Gain = +2, RF = 1 kΩ

Gain = +5, RF = 1 kΩ

Gain = +10, RF = 1 kΩ

Gain = +5

100

80

R_L= 100 Ω

MHz

35

20

Single-ended small-signal bandwidth

(-3 dB), V_O= 0.1 Vrms

BW

65

60

R_L= 25 Ω

MHz

V/µs

40

22

(3)

SR

Single-ended slew rate

V_O= 10 Vpp,

450

(1) A heatsink is required to keep the junction temperature below absolute maximum rating when an output is heavily loaded or shorted.

See Absolute Maximum Ratings section for more information.

(2) Approximately 0.5 mA (total) flows from V_CC+to GND for internal logic control bias.

(3) Slew rate is defined from the 25% to the 75% output levels.

4

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

PARAMETER

DC PERFORMANCE

TEST CONDITIONS

MIN

TYP MAX

UNIT

T_A= 25°C

1

20

25

10

15

Input offset voltage

T_A= full range

mV

µV/°C

µA

V_OS

V_CC= ±5 V, ±12 V, ±15 V

T_A= 25°C

0.5

Differential offset voltage

Offset drift

T_A= full range

T_A= 25°C

50

8

15

20

15

20

-Input bias current

T_A= full range

T_A= 25°C

I_IB

V_CC= ±5 V, ±12 V, ±15 V

8

900

+Input bias current

T_A= full range

Z_OL

Open loop transimpedance

R_L= 1 kΩ, V_CC= ±12 V, ±15 V

kΩ

INPUT CHARACTERISTICS

T_A= 25°C

±2.7

±2.6

±9.5

±9.3

±3.0

±9.8

V_CC= ±5 V

V

T_A= full range

T_A= 25°C

V_ICR

Input common-mode voltage range

V_CC= ±12 V

T_A= full range

T_A= 25°C

±12.4 ±12.7

±12.1

V_CC= ±15 V

V

T_A= full range

T_A= 25°C

48

44

54

CMRR

Common-mode rejection ratio

V_CC= ±5 V, ±12 V, ±15 V

dB

T_A= full range

+Input

-Input

800

30

kΩ

Ω

R_I

C_i

Input resistance

Input capacitance

1.7

pF

LOGIC CONTROL CHARACTERISTICS

V_IH

V_IL

I_IH

Bias pin voltage for logic 1

Bias pin voltage for logic 0

Bias pin current for logic 1

2.0

Relative to GND pin voltage

V

0.8

30

10

V_IH= 3.3 V, GND = 0 V

V_IL= 0.5 V, GND = 0 V

4

1

µA

µs

I_IL

Bias pin current for logic 0

Transition time, logic 0 to logic 1⁽⁴⁾

Transition time, logic 1 to logic 0⁽⁴⁾

(4) Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final

value.

LOGIC TABLE⁽¹⁾⁽²⁾

BIAS-1

BIAS-2

FUNCTION

Full bias mode

Mid bias mode

Low bias mode

Shutdown mode

DESCRIPTION

0

1

0

1

0

1

Amplifiers ON with lowest distortion possible (default state)

Amplifiers ON with power savings with a reduction in distortion performance

Amplifiers ON with enhanced power savings and a reduction of distortion performance

Amplifiers OFF and output has high impedance

(1) The default state for all logic pins is a logic zero (0).

(2) The GND pin useable range is from V_CC-to (V_CC+- 4 V).

5

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

R

G

750

Ω

+18 V

4.87

Ω

−

CODEC

V_IN+

+

THS6182a

20-dBm

Line

1 kW

1:1.6

Power

R

G

1.33 kW

1 kW

100

Ω

R

F

750

Ω

+18 V

4.87

Ω

−

+

CODEC

V_IN−

THS6182b

Figure 1. Single-Supply ADSL CO Line Driver Circuit Utilizing Active Impedance (SF = 4)

PIN ASSIGNMENTS

THS6182

SOIC−20 (DW) AND

SOIC−20 PowerPAD (DWP) PACKAGES

(TOP VIEW)

THS6182

Leadless 24−pin PowerPAD

4 mm X 5 mm (RHF) PACKAGE

(TOP VIEW)

THS6182

SOIC−16 (D) PACKAGE

(TOP VIEW)

D1 IN−

1

2

3

4

5

6

7

8

9

10

20 D2 IN−

19 D2 OUT

18

D1 IN−

1

2

3

4

5

6

7

8

16 D2 IN−

D1 OUT

15 D2 OUT

V

−

V

−

V

+

14

V

+

CC

24 23 22 21 20

GND

17 GND

16 GND

15 GND

14 GND

GND

13 GND

12 GND

N/C

1

2

3

19

18

17

N/C

V

GND

D1 IN+

BIAS−2

BIAS−1

11 D2 IN+

V

CC−

N/C

CC+

Power

PAD

GND

10

9

I

TM

ADJ

N/C

4

5

16

15

14

13

N/C

D1 IN+

BIAS−2

BIAS−1

13 D2 IN+

12

11 N/C

N/C

I

N/C

6

7

ADJ

GND

8

9 10 11 12

A. The PowerPAD is electrically isolated from all active circuity and pins. Connection of the PowerPAD to the PCB

ground plane is highly recommended, although not required, as this plane is typically the largest copper plane on a

PCB. The thermal performance will be better with a large copper plane than a small one.

6

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

2

Output voltage headroom

Common-mode rejection ratio

Crosstalk

vs Output current

vs Frequency

3

4

Total quiescent current

Large signal output amplitude

Voltage and current noise

Overdrive recovery

5

vs Frequency

6-8

9

10

Power supply rejection ratio

Output amplitude

vs Frequency

11

vs Frequency

12-37

38

Slew rate

vs Output voltage

vs Frequency

Closed-loop output impedance

39

vs Supply voltage

vs Temperature

vs Common-mode voltage

vs Temperature

vs Frequency

40

Quiescent current

41

Common-mode rejection ratio

Input bias current

42

43

Input offset voltage

44

2nd Harmonic distribution

3rd Harmonic distribution

2nd Harmonic distribution

3rd Harmonic distribution

45-52

53-60

61-64

65-68

vs Frequency

vs Output voltage

COMMON-MODE REJECTION

OUTPUT VOLTAGE HEADROOM

RATIO

vs

CROSSTALK

vs

FREQUENCY

vs

OUTPUT CURRENT

FREQUENCY

2.5

2

80

70

60

50

0

−10

V

= ±12 V

V

= ±12 V

CC

R = 100 Ω

CC

Gain = 2

R = 25 Ω

L

−20

−30

−40

V

= ±12 V

CC

1.5

1

V

= ±5 V

Gain = +5

CC

40

30

20

10

0

−50

−60

−70

Gain = +1

0.5

0

−80

−90

100 k

1 M

10 M

100 M

0

200

400

600

mA

800

10 k

100 k

1 M

10 M

100 M

f − Frequency − Hz

Out p ut Curr ent

−

f − Frequency − Hz

Figure 2.

Figure 3.

Figure 4.

7

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

LARGE SIGNAL OUTPUT

AMPLITUDE

vs

LARGE SIGNAL OUTPUT

AMPLITUDE

vs

TOTAL QUIESCENT CURRENT

FREQUENCY

24

18

12

25

20

15

10

5

30

24

V

= ±12V

V

= ±12 V

CC

Gain = 5

V

= ±12 V

CC

Gain = 10

= 500 Ω

V

= 16 V

= 8 V

O

PP

V

= 8 V

PP

O

Full Bias M ode

R

= 500 Ω

F

PP

V

= 4 V

PP

O

R = 100 Ω

Full Bias

R = 100 Ω

L

18

12

Full Bias

V

= 4 V

O

PP

V

= 2 V

PP

O

6

0

V

= 2 V

= 1 V

O

PP

= 1 V

PP

M id Bias Mode

Low Bias Mode

6

0

PP

V

= 0.5 V

PP

O

V

= 0.5 V

PP

O

−6

V

= 0.25 V

PP

O

−12

−18

V

= 0.25 V

PP

0

−18

100 k

1 M

10 M

100 M

1 G

0.01

0.1

1

10

100

100 k

1 M

10 M

100 M

1 G

Rset t o GND − kΩ

f − Frequency − Hz

f

Figure 5.

Figure 6.

Figure 7.

LARGE SIGNAL OUTPUT

AMPLITUDE

vs

VOLTAGE AND CURRENT NOISE

vs

FREQUENCY

OVERDRIVE RECOVERY

1000

100

10

1000

18

3

2

15

V

= ± 5 V

V

= ±12 V

CC

Gain = 5

= 750 Ω

V

= 4 V

= 2 V

O

PP

Gain = 5

R = 100 Ω

10

5

12

6

R

F

L

R = 25 Ω

Full Bias

L

PP

In−

100

1

V

= 1 V

O

PP

0

V

= 0.5 V

PP

O

10

Vin

−1

−2

−3

−5

−10

−15

−6

−12

−18

Vn

In+

V

= 0.25 V

PP

O

Vout

1

10

100

1 k

10 k

100 k

0.0

0.5

Time (µS)

1.0

f − Frequency − Hz

100 k

1 M

10 M

100 M

1 G

f − Frequency − Hz

Figure 8.

Figure 9.

Figure 10.

POWER SUPPLY REJECTION RATIO

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

2

1

80

70

60

50

40

R

F

= 1.2 k

1

R

= 1 k

F

R = 1 k

F

R

F

= 1.2 k

0

Vcc+

−1

−2

−3

−4

−5

−6

−7

−1

−2

R

= 2 k

F

R

F

= 2 k

Vcc−

−3

−4

−5

−6

−7

30

20

10

V

= ±15 V

V

= ±15 V

CC

Gain = 1

= 25 Ω

CC

Gain = 1

V

=

±12 V

CC

R

V

Gain = 5

R

V

=

100 Ω

L

= 0.1 V

rms

= 500 Ω

100 Ω

= 0.1 V

O

F

O

rms

0

Full Bias

=

Full Bias

L

−10

100 k 1 M

10 M

100 M

1 G

1k

10k

100k

1M

10M

100M

100 k 1 M

10 M

100 M

1 G

f − Frequency − Hz

f −Frequency −Hz

Figure 11.

Figure 12.

Figure 13.

8

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FRQUENCY

FREQUENCY

16

15

14

13

12

11

10

9

16

15

14

13

12

21

R

= 750

R

F

= 500

F

20

19

R

= 750

F

R

F

= 500

R

F

= 500

18

17

16

15

14

13

12

R

= 1 k

F

R

F

= 1 k

11

10

9

R

F

= 2 k

V

= ±15 V

CC

Gain = 10

R

= 1 k

F

V

= ±15 V

CC

Gain = 5

R = 2 k

F

V

= ±15 V

CC

Gain = 5

R

V

= 25 Ω

L

R

V

= 100 Ω

= 0.1 V

L

O

rms

R

V

=

25 Ω

= 0.1 V

rms

R

= 2 k

L

F

= 0.1 V

Full Bias

O

rms

8

O

Full Bias

7

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

1 G

f − Frequency − Hz

Figure 14.

Figure 15.

Figure 16.

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

21

20

19

18

17

16

15

14

13

12

2

1

0

2

R

F

= 1.2 k

R

F

= 1.2 k

1

R

F

= 500

R

= 1 k

= 2 k

R

= 1 k

F

0

−1

−2

−1

−2

−3

−4

R

F

R

F

= 2 k

R

F

= 1 k

R

−3

−4

−5

−6

−7

V

= ±12 V

V

= ±15 V

CC

Gain = 1

V

= ±12 V

CC

Gain = 10

CC

Gain = 1

= 2 k

F

−5

−6

−7

R

V

= 100 Ω

R

V

= 100 Ω

L

R

V

= 25 Ω

L

= 0.1 V

rms

= 0.1 V

O

= 0.1 V

O

rms

lO

rms

Full Bias

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

1 G

100 k

1 M

10 M

100 M

1 G

f − Frequency − Hz

Figure 17.

Figure 18.

Figure 19.

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

10

9

8

7

6

5

4

3

2

1

12

9

16

15

14

13

12

11

10

9

R

= 750

F

R

F

= 825

R

F

= 500

R

= 500

F

R

= 500

F

6

3

R

F

= 1 k

R

= 1 k

R

F

R

= 2 k

F

= 2 k

F

R

= 2 k

F

0

V

= ±12 V

CC

V

= ±12 V

CC

Gain = 5

V

= ±12 V

CC

Gain = 2

= 25 Ω

= 0.1 V

−3

Gain =

R

V

2

= 100 Ω

L

R

V

= 25 Ω

= 0.1 V

L

R

V

L

= 0.1 V

−6

−9

O

rms

O

rms

8

O

rms

Full Bias

7

100 k

1 M

10 M

100 M

1 G

100 k

1 M

10 M

100 M

100 k 1 M

10 M

100 M

1 G

f − Frequency − Hz

Figure 20.

Figure 21.

Figure 22.

9

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

16

15

14

13

12

11

10

16

15

14

13

12

16

15

14

13

12

11

10

9

R

= 750

F

R

= 750

F

R

F

= 500

R

= 500

R = 750

F

R

F

= 500

R

= 1 k

R

= 1 k

R

F

R

= 1 k

F

= 2 k

F

R

= 2 k

F

11

10

9

R

F

= 2 k

V

= ±12 V

V

= ±12 V

CC

Gain = 5

V

= ±12 V

CC

Gain =

Gain = 5

R

V

5

9

8

7

R

V

= 100 Ω

= 25 Ω

L

R

V

= 25 Ω

L

= 0.1 V

rms

= 0.1 V

O

= 0.1 V

O

rms

O

rms

8

Full Bias

Low Bias

Mid Bias

7

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

f − Frequency − Hz

Figure 23.

Figure 24.

Figure 25.

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

16

15

14

13

12

16

21

20

19

18

17

R

= 750

F

R

= 750

F

R

F

= 500

15

14

13

12

11

10

9

R

F

= 500

R

= 1 k

R

= 1 k

F

R

= 1 k

F

R

= 500

F

R

F

= 2 k

11

10

9

16

15

14

13

12

R

F

= 2 k

R

F

= 2 k

V

= ±12 V

V

= ±12 V

CC

V

= ±12 V

CC

Gain = 10

CC

Gain = 5

R

V

= 100 Ω

R

V

= 25 Ω

L

R

V

=

100 Ω

L

= 0.1 V

O

rms

= 0.1 V

O

rms

O

rms

8

Low Bias

Full Bias

Mid Bias

7

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

f − Frequency − Hz

Figure 26.

Figure 27.

Figure 28.

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

21

20

19

18

17

16

15

14

13

12

16

15

16

15

14

R

F

= 500

R = 500

F

R

F

= 500

14

13

12

11

10

9

13

12

11

10

R

F

= 1 k

R

F

= 1 k

R

F

= 1 k

R

F

= 2 k

V

= ±12 V

CC

V

= ±12 V

CC

Gain = −5

V

= ±12 V

CC

Gain = 10

Gain = −5

R

V

9

8

7

= 25 Ω

R

V

= 100 Ω

L

R

V

= 100 Ω

L

= 0.1 V

O

rms

O

rms

= 0.1 V

rms

O

8

Full Bias

7

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

f − Frequency − Hz

Figure 29.

Figure 30.

Figure 31.

10

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

3

2

3

2

16

R

= 1.2 k

R

= 500

F

R

= 1 k

F

15

14

13

12

11

10

R

= 750

= 2 k

F

R

= 1 k

F

R

= 1.2 k

F

1

0

R

F

−1

−2

−3

−1

−2

−3

−4

−5

−6

R

= 2 k

F

R

F

= 2 k

V

= ±5 V

V

= ±5 V

CC

Gain = 1

V

= ±5 V

CC

Gain = 1

= 100 Ω

CC

Gain = 5

−4

−5

−6

9

8

7

R

V

= 25 Ω

= 0.1 V

R

V

= 25 Ω

L

R

V

L

= 0.1 V

O

rms

= 0.1 V

rms

Full Bias

O

rms

O

Full Bias

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

1 G

100 k

1 M

10 M

100 M

1 G

f − Frequency − Hz

Figure 32.

Figure 33.

Figure 34.

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

OUTPUT AMPLITUDE

vs

FREQUENCY

16

15

14

21

20

19

18

17

R

F

= 500

R

F

= 500

R

F

= 500

20

19

18

17

16

15

R

= 750

F

13

12

11

10

R

= 1 k

R = 1 k

F

R

F

= 1 k

R

F

= 2 k

R

F

= 2 k

16

15

14

13

12

R

= 2 k

F

V

= ±5 V

V

= ±5 V

CC

Gain = 10

V

= ±5 V

CC

Gain = 10

CC

Gain = 5

9

8

7

14

R

V

= 25 Ω

= 0.1 V

R

V

= 25 Ω

= 0.1 V

L

R

V

= 100 Ω

L

O

rms

= 0.1 V

rms

lO

rms

13

12

O

Full Bias

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

f − Frequency − Hz

Figure 35.

Figure 36.

Figure 37.

CLOSED LOOP OUTPUT

IMPEDANCE

vs

SLEW RATE

vs

OUTPUT VOLTAGE

QUIESCENT CURRENT

vs

SUPPLY VOLTAGE

FREQUENCY

500

1000

100

10

25

20

15

10

5

Ta = 25 deg.C

Icc+ (Full)

SR+

Shutdown

Icc− (Full)

400

300

SR−

Mid Bias

Low Bias

Icc+ (Mid)

Icc− (Mid)

A

V

= ± 12 V

CC

Gain = 10

= 500 Ω

1

200

100

0

Icc+ (Low)

Full Bias

R

L

Icc− (Low)

Icc− (SD)

0.1

Icc+ (SD)

0.01

100 k

1 M

10 M

100 M

3

5

7

9

11

13

15

0

5

10

15

20

f − Frequency − Hz

Output Voltage − Vp−p

Supply Voltage − +/−Vcc

Figure 38.

Figure 39.

Figure 40.

11

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

QUIESCENT CURRENT

vs

COMMON-MODE REJECTION RATIO

INPUT BIAS CURRENT

vs

TEMPERATURE

COMMON-MODE VOLTAGE

TEMPERATURE

25

90

13

Vcc = +/−12 V

Vcc = +/−15 V

Icc+ (Full)

Icc− (Full)

80

70

60

50

40

30

20

12

11

−40 Deg C

20

15

85 Deg C

Icc+ (Mid)

Iib−

10

9

Icc− (Mid)

25 Deg C

10

5

Icc+ (Low)

Icc− (Low)

8

Iib+

Icc− (SD)

7

Icc+ (SD)

20

6

0

−14 −10 −6

−2

2

6

10

14

−40 −20

0

20

40

60

80 100

−40 −20

0

40

60

80

100

Common−Mode Voltage − V

Temperature − Deg C

Temperature − Deg.C

Figure 41.

Figure 42.

Figure 43.

INPUT OFFSET VOLTAGE

2ND HARMONIC DISTORTION

vs

TEMPERATURE

FREQUENCY

5.5

−40

−50

−60

−70

−80

−90

−100

−40

−50

−60

−70

−80

Differential configuration

Low Bias

Differential configuration

Low Bias

Vio − Channel A

5

4.5

Full Bias

Mid Bias

4

3.5

3

Full Bias

Vio − Channel B

V

= ±5 V

CC

Gain = 10

V

= ±12 V

CC

Gain = 10

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−90

R

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

O

V

−100

100 k

−40 −20

0

20

40

60

80 100

1 M

10 M

100 M

100 k

1 M

10 M

100 M

Temperature − Deg C

f − Frequency − Hz

Figure 44.

Figure 45.

Figure 46.

2ND HARMONIC DISTORTION

vs

FREQUENCY

−45

−50

−55

−60

−65

−70

−75

−80

−45

−50

−55

−60

−65

−70

−75

−80

−40

−50

−60

−70

−80

Differential configuration

Low Bias

Differential configuration

Mid Bias

Low Bias

Mid Bias

Low Bias

Mid Bias

Full Bias

V

= ±12 V

CC

Gain = 10

V

= ±5 V

V

= ±12 V

CC

Gain = 10

CC

Gain = 5

Full Bias

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

R

V

= 200 Ω

= 1 kΩ

L

F

O

L

F

O

−90

Full Bias

1 M

= 2 V

PP

−100

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

100 k

10 M

100 M

f − Frequency − Hz

Figure 47.

Figure 48.

Figure 49.

12

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

2ND HARMONIC DISTORTION

vs

FREQUENCY

−40

−50

−60

−70

−80

−45

−50

−45

−50

−55

−60

−65

−70

−75

−80

−85

Differential configuration

Low Bias

Differential configuration

−55

−60

−65

−70

−75

−80

−85

Mid Bias

Low Bias

Mid Bias

Full Bias

Low Bias

V

= ±12 V

CC

Gain = 5

V

= ±5 V

CC

Gain = 5

V

= ±5 V

CC

Gain = 5

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

O

Full Bias

1 M

−90

Full Bias

−100

100 k

1 M

10 M

100 M

1 M

10 M

100 M

100 k

10 M

100 M

f − Frequency − Hz

Figure 50.

Figure 51.

Figure 52.

3RD HARMONIC DISTORTION

vs

FREQUENCY

−30

−40

−30

−40

−50

−60

−70

−80

−90

−100

−30

−40

−50

−60

Differential configuration

Low Bias

Differential configuration

Low Bias

V

= ±12 V

CC

Gain = 10

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−50

−60

Mid Bias

Low Bias

Full Bias

Mid Bias

−70

−80

−70

−80

Full Bias

V

= ±5 V

Mid Bias

CC

Gain = 10

V

= ±5 V

CC

Gain = 10

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−90

Differential configuration

O

−100

100 k

1 M

10 M

100 M

100 k

1 M

10 M

100 M

1 M

10 M

100 M

f − Frequency − Hz

Figure 53.

Figure 54.

Figure 55.

3RD HARMONIC DISTORTION

vs

FREQUENCY

−30

−40

−50

−60

−30

−40

−50

−60

−70

−80

−90

−100

−30

−40

−50

Differential configuration

Low Bias

Differential configuration

Low Bias

V

= ±5 V

CC

Gain = 5

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−60

−70

Mid Bias

Full Bias

Mid Bias

−70

−80

Full Bias

Mid Bias

V

= ±12 V

CC

Gain = 5

V

= ±12 V

−80

−90

CC

Gain = 10

Full Bias

R

V

= 200 Ω

= 1 kΩ

= 2 V

PP

L

F

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−90

Differential configuration

O

−100

100 k

−100

100 k

1 M

10 M

100 M

1 M

10 M

f − Frequency − Hz

100 M

1 M

10 M

100 M

f − Frequency − Hz

Figure 56.

Figure 57.

Figure 58.

13

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

3RD HARMONIC DISTORTION

2ND HARMONIC DISTORTION

vs

FREQUENCY

OUTPUT VOLTAGE

−30

−40

−50

−60

−70

−80

−90

−100

−75

−80

Differential configuration

Low Bias

Differential configuration

Low Bias

V

= ±12 V

CC

Gain = 5

−40

−50

R

V

= 50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−85

−90

Mid Bias

Full Bias

−60

−70

Mid Bias

Full Bias

Mid Bias

V

= ±12 V

CC

Gain = 5

V

= ±5 V

Full Bias

CC

Gain = 5

−80

−95

R

= 200 Ω

= 1 kΩ

L

R

V

50 Ω

= 1 kΩ

= 2 V

PP

L

F

O

−90

F

f = 1 MHz

Differential configuration

−100

100 k

1 M

10 M

100 M

0

5

10 15 20

25 30 35 40

1 M

10 M

100 M

f − Frequency − Hz

Output Voltage − Vpp

f − Frequency − Hz

Figure 59.

Figure 60.

Figure 61.

2ND HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

−75

−65

−70

−75

−80

−65

−70

Differential configuration

Low Bias

−80

−85

Mid Bias

Full Bias

Mid Bias

Full Bias

Mid Bias

−90

Full Bias

V

= ±12 V

V

= ±5 V

CC

Gain = 5

−75

−80

CC

Gain = 5

V

= ±5 V

CC

Gain = 5

R

= 50 Ω

= 1 kΩ

R

= 200 Ω

= 1 kΩ

L

−95

L

R

= 50 Ω

= 1 kΩ

L

F

f = 1 MHz

−100

0

5

10

0

5

10

15

20

25

30

0

2

4

6

8

10

Output Voltage − Vpp

Figure 62.

Figure 63.

Figure 64.

3RD HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

−70

−75

−65

−70

−75

−80

−85

−90

−95

−100

V

= ±12 V

CC

Gain = 5

Differential configuration

Low Bias

Differential configuration

Low Bias

−75

−80

R

= 50 Ω

= 1 kΩ

L

F

Low Bias

f = 1 MHz

−80

−85

Mid Bias

−85

Mid Bias

Full Bias

−90

V

= ±5 V

V

= ±12 V

CC

Gain = 5

CC

Gain = 5

Full Bias

R

= 200 Ω

= 1 kΩ

R

= 200 Ω

= 1 kΩ

L

Full Bias

−95

F

f = 1 MHz

Differential configuration

−100

0

2

4

6

8

10

0

5

10

15 20 25 30

35 40

0

5

10

15

20

25

30

Output Voltage − Vpp

Figure 65.

Figure 66.

Figure 67.

14

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

3RD HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

−65

Differential configuration

Low Bias

−70

−75

−80

−85

−90

−95

−100

Mid Bias

V

= ±5 V

CC

Gain = 5

Full Bias

R

= 50 Ω

= 1 kΩ

L

F

f = 1 MHz

0

2

4

6

8

10

Output Voltage − Vpp

Figure 68.

15

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION

The THS6182 contains two independent operational amplifiers. These amplifiers are current feedback topology

amplifiers made for high-speed operation. They have been specifically designed to deliver the full power

requirements of ADSL and therefore can deliver output currents of at least 400 mA at full output voltage.

The THS6182 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This

process provides excellent isolation and high slew rates that result in the device's excellent crosstalk and

extremely low distortion.

DEVICE PROTECTION FEATURE

The THS6182 has a built-in thermal protection feature. Should the internal junction temperature rise above

approximately 160°C, the device automatically shuts down. Such a condition could exist with improper heat

sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown

circuit automatically turns the device back on. This occurs at approximately 145°C, junction temperature. Note

that the THS6182 does not have short-circuit protection and care should be taken to minimize the output current

below the absolute maximum ratings.

THERMAL INFORMATION

The THS6182 is available in a thermally-enhanced DWP and RHF package, which is a member of the

PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is

mounted [see Figure 69(a) and Figure 69(b), for the DWP package example]. This arrangement results in the

lead frame being exposed as a thermal pad on the underside of the package [see Figure 69(c)]. Because this

thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing

a good thermal path away from the thermal pad. Note that the PowerPAD is electronically isolated from the

active circuitry and any pins. Thus, the PowerPAD can be connected to any potential voltage within the absolute

maximum voltage range. Ideally, connection of the PAD to the ground plane is preferred as the plane typically is

the largest copper plane on a PCB.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is

discussed in more detail in the PCB design considerations section of this document.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Thermal

Pad

Side View (a)

DIE

End View (b)

Bottom View (c)

A. The thermal pad is electrically isolated from all terminals in the package.

Figure 69. Views of Thermally Enhanced DWP Package

16

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES

As with all current feedback amplifiers, the bandwidth of the THS6182 is an inversely proportional function of the

value of the feedback resistor. The recommended resistors with a ±12-V power supply for the optimum frequency

response with a 25-Ω load system is 1 kΩ for a gain of 5. These should be used as a starting point and once

optimum values are found, 1% tolerance resistors should be used to maintain frequency response character-

istics.

Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain

resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback

resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the

bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback

amplifiers.

It is important to realize the effects of the feedback resistance on distortion. Increasing the resistance decreases

the loop gain and increases the distortion. It is also important to know that decreasing load impedance increases

total harmonic distortion (THD). Typically, the third order harmonic distortion increases more than the second

order harmonic distortion.

Finally, in a differential configuration as shown in Figure 1, it is important to note that there is a differential gain

and a common-mode gain which are different from each other. Differentially, the gain is at 1 + R_F/R_G. While

common-mode gain = 1 due to R_Gbeing connected directly between each amplifier and not to ground. This can

lead to potential problems as the stability of the amplifier is determined by R_F. Thus, R_Fmust be large enough to

ensure the common-mode stability, even though a large differential gain may be required.

OFFSET VOLTAGE

The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:

R

F

I

IB−

R

G

+

−

+

V

I

V

O

R

S

I

IB+

R

F

V

+ V

1 ) ǒ Ǔ " I

R

1 ) ǒ Ǔ " I

R

ǒ Ǔ ǒ Ǔ

OO

IO

IB)

S

IB–

F

R

G

Figure 70. Output Offset Voltage Model

NOISE CALCULATIONS

Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise

model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only

difference between the two is that the CFB amplifiers generally specify different current noise parameters for

each input while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in

Figure 71. This model includes all of the noise sources as follows:

•

e_n= Amplifier internal voltage noise (nV/√Hz)

IN+ = Noninverting current noise (pA/√Hz)

IN- = Inverting current noise (pA/√Hz)

e_RX= Thermal voltage noise associated with each resistor (e_RX= 4 kTR_x)

17

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

e

Rs

e

n

R

S

Noiseless

+

_

e

ni

e

no

IN+

IN−

e

Rf

R

F

e

Rg

R

G

Figure 71. Noise Model

The total equivalent input noise density (e_ni) is calculated by using the following equation:

₎ǒ_{IN ) R}Ǔ²₎ǒ_IN–ǒ_{R G}ǓǓ²_{) 4 kTR ) 4 kT}ǒ_{R G}Ǔ

2

Ǹ

ǒ Ǔ

e

+

e

ø R

n

s

ni

S

F

Where:

−23

k = Boltzmann’s constant = 1.380658 × 10

T = Temperature in degrees Kelvin (273 +°C)

R || R = Parallel resistance of R and R

F

G

F

G

To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e_ni) by the

overall amplifier gain (A_V).

R

F

_{+ e}ǒ_{1 )}Ǔ_{(Noninverting Case)}

e

+ e

A

no

ni

V

R

G

As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the

closed-loop gain is increased (by reducing R_G), the input noise is reduced considerably because of the parallel

resistance term.

DRIVING A CAPACITIVE LOAD

Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are

taken. The first is to realize that the THS6182 has been internally compensated to maximize its bandwidth and

slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the

output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for

capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of

the amplifier, as shown in Figure 72. A minimum value of 2 Ω should work well for most applications. For

example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance

loading and provides the proper line impedance matching at the source end.

18

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

1 kΩ

_

Input

2 Ω

Output

THS6182

+

C

LOAD

Figure 72. Driving a Capacitive Load

PCB DESIGN CONSIDERATIONS

Proper PCB design techniques in two areas are important to assure proper operation of the THS6182. These

areas are high-speed layout techniques and thermal-management techniques. Because the THS6182 is a

high-speed part, the following guidelines are recommended.

•

Ground plane - It is essential that a ground plane be used on the board to provide all components with a low

inductive ground connection. Although a ground connection directly to a terminal of the THS6012 is not

necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves

two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it

provides the path for heat removal. Note that the BiCom process is a SOI process and thus, the substrate is

isolated from the active circuitry.

•

Input stray capacitance - To minimize potential problems with amplifier oscillation, the capacitance at the

inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input

must be as short as possible, the ground plane should be removed under any etch runs connected to the

inverting input, and external components should be placed as close as possible to the inverting input. This is

especially true in the noninverting configuration.

Proper power supply decoupling - Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF

ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several

amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply

terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the

supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power terminal

and the ceramic capacitors.

•

For a differential configuration as shown in Figure 1, it is recommended that a 0.1-µF or 1-µF capacitor be

added across the power supplies (from V_CC+to V_CC-) as close as possible to the THS6182. This allows for

differential currents to flow properly, signficantly reducing even-order harmonic distortion. The 0.1-µF

capacitors to ground should also be used as previously stipulated.

Because of its power dissipation, proper thermal management of the THS6182 is required. Although there are

many ways to properly heatsink this device, the following steps illustrate one recommended approach for a

multilayer PCB with an internal ground plane utilizing the 20 pin DWP PowerPAD package.

1. Prepare the PCB with a top side etch pattern as shown in Figure 73. There should be etch for the leads as

well as etch for the thermal pad.

2. Place 18 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept

small so that solder wicking through the holes is not a problem during reflow.

3. It is recommended, but not required, to place six more holes under the package, but outside the thermal pad

area. These holes are 25 mils in diameter. They may be larger because they are not in the area to be

soldered so that wicking is not a problem.

4. Connect all 24 holes, the 18 within the thermal pad area and the 6 outside the pad area, to the internal

ground plane.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat

19

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

transfer during soldering operations. This makes the soldering of vias that have plane connections easier.

However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore,

the holes under the THS6182 package should make their connection to the internal ground plane with a

complete connection around the entire circumference of the plated through hole.

6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with

its five holes. The four larger holes outside the thermal pad area, but still under the package, should be

covered with solder mask.

7. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.

8. With these preparatory steps in place, the THS6182 DWP is simply placed in position and run through the

solder reflow operation as any standard surface-mount component. This results in a part that is properly

installed.

0.080

0.026

0.024

0.1025

0.476

0.120

0.085

0.178

0.450

0.0165

0.021

PowerPAD and via placement

pad area (0.085 x 0.120) with 15

vias (Via diameter = 0.013)

.039

0.026

Vias should go through the board connecting the top layer

PowerPad to any and all ground planes. (The larger the ground

plane, the larger the area to distribute the heat.) Solder resist should

be used on the bottom side ground plane in order to prevent wicking

of the solder through the vias during the reflow process.

All Units in Inches

Figure 73. 20-Pin DWP PowerPAD PCB Etch and Via Pattern

The RHF package is similar to the DWP package with respect to PCB mounting procedures. The recommended

PCB layout is as shown in Figure 74.

20

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

0.4953

0.1905

Pad size

24 x (0.3048 x 0.762) mm

0.3721

0.1905

0.4953

2.2987

0.3641

4.9022

3.302

5.9182

PowerPAD and Via layout

(Pad size 3.65 mm x 2.65 mm ,

0.682

1.143

9 Vias with diameter = 0.254 mm)

0.563

2.65

0.762

3.65

Vias should go through the board connecting the top layer PowerPAD to any and all

ground planes. The larger the ground plane, the more area to distribute the heat.

Solder resist should be used on the bottom side ground plane to prevent wicking of

the solder through the vias during the reflow process.

Figure 74. Suggested PCB Layout

The actual thermal performance achieved with the THS6182 in the 20-pin DWP PowerPAD package depends on

the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3

inches, then the expected thermal coefficient, Θ_JA, is about 21.5°C/W. (See the Package Dissipation Ratings

Table for all other package metrics.) For a given Θ_JA, the maximum power dissipation is calculated by the

following formula:

21

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

T

–T

MAX

A

P

+

ǒ Ǔ

D

q

JA

Where:

P

= Maximum power dissipation of THS6182 (watts)

= Absolute maximum operating junction temperature (125°C)

= Free-ambient air temperature (°C)

D

T

MAX

T

A

θ

= θ + θ

JA

JC CA

θ

= Thermal coefficient from junction to case. See the Package Dissipation Ratings table.

= Thermal coefficient from case to ambient determined by PCB layout and construction.

JC

CA

More complete details of the PowerPAD installation process and thermal management techniques can be found

in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found

at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered

through your local TI sales office. Refer to literature number SLMA002 when ordering.

GENERAL CONFIGURATIONS

A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly

to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6182,

like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors

directly from the output to the inverting input is not recommended. This is because, at high frequencies, a

capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when

using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily

implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an

RC-filter at the noninverting terminal of the operational-amplifier (see Figure 75).

R

G

R

F

V

R

−

+

O

F

1

ǒ

Ǔ

+

ǒ

1 )

Ǔ

V

O

V

1 ) sR1C1

I

G

V

I

R1

C1

1

f

+

–3dB

2pR1C1

Figure 75. Single-Pole Low-Pass Filter

If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is

because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of

their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize

distortion. An example is shown in Figure 76.

22

THS6182

www.ti.com

SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004

APPLICATION INFORMATION (continued)

C1

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

+

_

V

I

1

R1

R2

f

+

–3dB

2pRC

C2

R

F

R

G

=

1

R

F

2 −

)

(

R

G

Q

Figure 76. 2-Pole Low-Pass Sallen-Key Filter

EVALUATION BOARD

An evaluation board is available for the THS6182. This board has been configured for proper thermal

management of the THS6182. The circuitry has been designed for a typical ADSL application as shown

previously in this document. For more detailed information, refer to the THS6182EVM User's Guide (literature

number SLOU152). To order the evaluation board contact your local TI sales office or distributor.

23

THERMAL PAD MECHANICAL DATA

www.ti.com

DWP (R-PDSO-G20)

THERMAL INFORMATION

This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an

external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be

used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a

ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from

the integrated circuit (IC).

For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,

refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002

and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are

available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

20

11

Exposed Thermal Pad

2,54

2,08

1

10

3,30

2,31

Top View

NOTE: All linear dimensions are in millimeters

PPTD009

Exposed Thermal Pad Dimensions

PowerPAD is a trademark of Texas Instruments

PACKAGE OPTION ADDENDUM

www.ti.com

11-Feb-2005

PACKAGING INFORMATION

Orderable Device

THS6182D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

20

40

2500

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

THS6182DR

SOIC

D

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

THS6182DW

THS6182DWP

DW

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1YEAR/

Level-1-220C-UNLIM

SO

Power

PAD

DWP

25

None

CU NIPDAU Level-1-220C-UNLIM

THS6182DWPR

THS6182DWR

ACTIVE

SO

Power

PAD

DWP

DW

20

2000

None

CU NIPDAU Level-1-220C-UNLIM

SOIC

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1YEAR/

Level-1-220C-UNLIM

THS6182RHFR

THS6182RHFT

ACTIVE

QFN

RHF

24

3000

250

None

CU NIPDAU Level-2-220C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Products

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amplifier.ti.com

www.ti.com/audio

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dsp.ti.com

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www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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Logic

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logic.ti.com

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power.ti.com

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