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LZ2346

型号:

LZ2346

描述:

Twopower电源( + 5V和+ 12V )操作CCIR 1/3类型B / W CCD传感器面积为CCIR[ Twopower supply (+5 V and +12 V) operation CCIR 1/3 type B/W CCD Area Sensor for CCIR ]

品牌:

SHARP[ SHARP ELECTRIONIC COMPONENTS ]

页数:

8 页

PDF大小:

183 K

LZ2346  
supply  
V and +12 operation  
1/3 type B/W CCD Area Sensor for  
LZ2 3 4 6  
PIN CONNECTIONS  
DESCRIPTION  
LZ2346 is 1 /3-type (6.0 mm) solid-state image  
sensor that consists of PN phote-diodes and  
CCDS (charge-coupled devices) driven by only  
positive voltages. Having approximately 220000  
pixels (horizontal 384 vertical 582), the sensor  
provides a stable B/W image.  
TOP VIEW  
16-PIN S DIP  
16  
2
15 OFD  
G N D  
3
1 4  
1 3  
1 2  
1 1  
10  
FEATURES  
Number of pixels : 362 (H) X 582 (V)  
Pixel pitch : 13.6 (H) x 6.3 (V)  
Number of optical black pixels  
: Horizontal; front 2 and rear 20  
Low fixed pattern noise and lag  
0s  
4
5
H2  
B
7
No sticking and no image distortion  
Blooming suppression structure  
Built-in output amplifier  
9
Variable electronic shutter (1/50 to 1/10 000 s)  
Compatible with  
Package : 16-pin  
standard  
BLOCK DIAGRAM  
I
I
OFD  
GND  
Horizontal Shift Register  
0s  
OD RD  
by device  
SHARP In order  
any  
in  
using any SHARPS  
data  
any SHARPS device”  
PIN DESCRIPTION  
PIN NAME  
Reset transistor drain  
SYMBOL  
RD  
Output transistor drain  
Video  
0s  
Reset transistor gate clock  
Vertical shift register gate clock  
Horizontal shift register gate clock  
Transfer  
clock  
Overflow drain  
Test terminal  
Ground  
OFD  
GND  
ABSOLUTE MAXIMUM RATINGS  
(Ta  
PARAMETER  
transistor drain  
SYMBOL  
RATING  
O t o + 1 5  
O t o + 1 5  
O t o + 1 5  
–0.3 to +15  
–0.3 to  
UNIT  
v
v
v
v
v
v
v
v
V O D  
Reset transistor drain voltage  
Test terminal, T I  
Reset gate clock voltage  
Vertical shift register clock voltage  
Horizontal shift register clock voltage  
Transfer gate clock voltage  
Overflow drain voltage  
–0.3 to +15  
–0,3 to +15  
O to  
–40 to  
Tstg  
Topr  
Storage temperature  
–20 to + 7 0  
ambient temperature  
RECOMMENDED OPERATING CONDITIONS  
TYP.  
25.0  
12.5  
Voo  
MIN.  
12,0  
MAX.  
14.0  
NOTE  
SYMBOL  
Topr  
UNIT  
Operating ambient temperature  
Output transistor drain voltage  
Reset transistor drain voltage  
‘c  
v
v
Voo  
When DC is applied  
V
OFD  
12, 0  
v
1
3.0  
Overflow  
drain  
voltage  
When pulse is applied  
p-p level  
12,0  
12.5  
14.0  
v
2
Voo  
Test terminal,  
Ground voltage  
v
v
GND  
0.0  
v
TGL  
v
LOW level  
HIGH level  
LOW level  
HIGH level  
LOW level  
HIGH level  
LOW level  
HIGH level  
– 0.05  
12. 0  
0.05  
14,0  
0,05  
6.0  
Transfer gate clock  
v
12.5  
0.0  
v
v
0.05  
4.7  
Vertical  
register clock  
v
5.0  
-2L, V HI B-2BL  
HI  
0.05  
4 . 7  
v
0.05  
6.0  
Horizontal shift  
register clock  
5.0  
v
-10.5  
v
0 . 0  
Reset gate  
VRD – 6.0  
v
Vertical  
register clock frequency  
15. 63  
6, 75  
6. 75  
k H z  
M H z  
M H z  
ns  
Horizontal shift register clock frequency  
Reset gate clock frequency  
Horizontal shift register clock phase  
3
twl ,  
0.0  
10.0  
NOTES :  
1. When DC voltage is applied, shutter speed is  
1 /50 seconds.  
2. When pulse is applied, shutter spaed is less than 1/50 seconds.  
3
-
-
ELECTRICAL CHARACTERISTICS (Drive method : Field Accumulation)  
(Ta = Operating conditions : typical values for the recommended operating conditions, Color  
temperature of light source :3200 K /  
cut-off filter (CM-500, 1  
MIN.  
TYP.  
MAX.  
15  
SYMBOL  
PRNU  
UNIT  
NOTE  
2
3
Photo response non-uniformity  
Saturation signal  
vast  
Vdark  
DSNU  
R
450  
140  
5.0  
1.5  
15.0  
5.0  
1, 4  
1, 5  
6
Dark output voltage  
Dark signal non-uniformity  
Sensitivity  
200  
– 85  
7
SMR  
Al  
– 76  
1.0  
Smear ratio  
<
I
8
Image lag  
ABL  
1000  
9
Blooming suppression ratio  
2.5  
5.0  
Output  
drain current  
Ro  
400  
output impedance  
The standard output voltage is defined as 150  
by the  
dition where Vdmax and Vdmin are the maximum and  
minimum values of each segment’s voltage, respective y,  
that is the average output voltage over al pixels in the  
segment.  
average output voltage under uniform illumination.  
The standard exposure level is defined when the average  
output voltage is 150 under uniform illumination.  
NOTES :  
Ta :  
6. The average output voltage when a 1 COO  
light source  
attached with a 90% reflector is imaged by a lens of  
f50 mm.  
The sensor is adjusted to position a V/l O square at the  
The image area is divided mto 10X 10 segments.  
voltage is the average output voltage of all the  
pixels within the segment. PRNU is defined by (Vmax –  
2
center of image area  
V is the  
length of the  
image area. SMR is defined by the ratio of the output  
where Vmax and Vmin are the maximum and  
the minimum values of each segment’s voltage respec-  
tively, when the average output voltage Vo is 150 mV.  
The image area is divided into 10x 10 segments.  
voltage detected during the vertical blanking  
to the  
maximum of the pixel voltage in the V/l O square.  
The sensor is  
at the  
level  
3
ing to the standard condition preceding  
con-  
The saturation signal is defined as the minimum of each  
segment’s voltage which is the average output voltage of  
all the pixels within the segment, when the exposure level  
dition. Al is defined by the ratio between the output volt-  
age measured at the 1st field during the non-exposure  
period and the standard output voltage.  
The sensor is adjusted to position a V/l O square at the  
center of image area. ABL is the ratio between the  
at the standard condition and the exposure at a  
is  
as 10 times, compared to standard level.  
9
4
5
The average output voltage under a  
The image area is  
defined by  
into 10x 10 segments. OSNU is  
under the non-exposure con-  
where a  
is observed.  
PIXEL STRUCTURE  
OPTICAL  
OPTICAL BLACK  
(20 PIXELS)  
(2 PIXELS)  
(v)  
582  
X
362 (H)  
RESPONSE EXAMPLE  
SPECTRAL  
100  
80  
w
>
20  
0
1200  
1
800  
400  
TIMING DIAGRAM EXAMPLE  
VERTICAL TRANSFER TIMING  
3rd FIELD)  
19  
5
623  
625  
1
HD  
VD  
n
n
n
n
n
n
n
n
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n
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n
n
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n
n
n
u
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u
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n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
V4  
n
n
n
n
3
4
5
6
7
8
5 8 2  
2
0s  
I
II  
(2nd. 4th  
331  
311  
318  
HD  
VD  
n
n
n
n
n
n
n
n
n
n
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n
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,
u
u
u
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u
n
u
u
u
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u
u
u
u
u
u
u
u
u
u
n
u
u
u
V2  
V3  
u
n
n
n
n
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n
n
n
n
n
n
n
n
n
n
n
n
n
2
4
6
+
+
+
5 8 2  
0s  
TIMING  
HORIZONTAL TRANS FER  
I
0s  
0 6 (2 )  
.
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. . . . ...3 6 2  
READOUT TIMING  
(1S, 3rd FIELD)  
(2nd,  
180  
SYSTEM CONFIGURATION EXAMPLE  
mll  
181  
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