PART NUMBER:
± 2g Tri-axis Digital Accelerometer
Specifications
KXSD9-2050
Rev. 2
Jul-2009
Writing to a KXSD9 8-bit Register
Upon power up, the Master must write to the KXSD9’s control registers to set its operational mode.
Therefore, when writing to a control register on the I2C bus, as shown Sequence 1 on the following page,
the following protocol must be observed: After a start condition, SAD+W transmission, and the KXSD9
ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This
command is telling the KXSD9 to which 8-bit register the Master will be writing the data. Since this is I2C
mode, the MSB of the RA command should always be zero (0). The KXSD9 acknowledges the RA and the
Master transmits the data to be stored in the 8-bit register. The KXSD9 acknowledges that it has received
the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the
KXSD9 is now stored in the appropriate register. The KXSD9 automatically increments the received RA
commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave
ACK as shown in Sequence 2 on the following page.
Reading from a KXSD9 8-bit Register
When reading data from a KXSD9 8-bit register on the I2C bus, as shown in Sequence 3 on the next page,
the following protocol must be observed: The Master first transmits a start condition (S) and the
appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXSD9 acknowledges and the
Master transmits the 8-bit RA of the register it wants to read. The KXSD9 again acknowledges, and the
Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses
the KXSD9 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then
acknowledges and transmits the data from the requested register. The Master does not acknowledge
(NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that
the KXSD9 automatically increments through its sequential registers, allowing data reads from multiple
registers following a single SAD+R command as shown below in Sequence 4 on the following page.
If a receiver cannot transmit or receive another complete byte of data until it has performed some other
function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when
the receiver is ready for another byte and releases SCL. For instance, after the Master has requested to
read acceleration data from the KXSD9, the KXSD9 can hold SCL low to force the Master into a wait state
while it completes the A/D conversion. After the A/D conversion, the KXSD9 will release SCL and transmit
the acceleration data to the Master. Note that the KXSD9 will hold for A/D conversions only if the CLKhld
bit is set in CTRL_REGB.
Data Transfer Sequences
The following information clearly illustrates the variety of data transfers that can occur on the I2C bus and
how the Master and Slave interact during these transfers. Table 8 on the following page defines the I2C
terms used during the data transfers.
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