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LY6264UV

型号：

LY6264UV

描述：

8K ×8位低功耗CMOS SRAM[ 8K X 8 BIT LOW POWER CMOS SRAM ]

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

14 页

PDF大小：

212 K

下载PDF手册
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 2.0  
Rev. 2.1  
Rev. 2.2  
Rev. 2.3  
Rev. 2.4  
Description  
Initial Issue  
Revised Vcc Range 4.5~5.5V => 2.7~5.5V  
Revised ISB1  
Issue Date  
Jul.25.2004  
May.3.2005  
May.13.2005  
Aug.29.2005  
Feb.24.2006  
Jul.31.2006  
Adding PKG type : skinny P-DIP  
Revised VIH(min)=2.4V, VIL(max)=0.6V  
Revised VIH(min)=2.4V, VIL(max)=0.6V (VCC=2.7~3.6V)  
VIH(min)=2.4V, VIL(max)=0.8V (VCC=4.5~5.5V)  
Revised STSOP Package Outline Dimension  
Added SL grade  
Rev. 2.5  
Rev. 2.6  
Mar.26.2008  
Mar.30.2009  
℃
℃
Added ISB1/IDR values when TA = 25 and TA = 40  
FEATURES ORDERING INFORMATION  
Revised  
&
Lead free and green package available to Green package  
available  
ORDERING INFORMATION  
Added packing type in  
Revised ISB1(MAX)  
Revised VTERM to VT1 and VT2  
Revised Test Condition of ISB1/IDR  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
FEATURES  
GENERAL DESCRIPTION  
The LY6264 is a 65,536-bit low power CMOS static  
random access memory organized as 8,192 words  
by 8 bits. It is fabricated using very high  
performance, high reliability CMOS technology. Its  
standby current is stable within the range of  
operating temperature.  
„ Fast access time : 35/55/70ns  
„ Low power consumption:  
Operating current : 20/15/10mA (TYP.)  
Standby current : 1μA (TYP.)  
„ Single 2.7~5.5V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
The LY6264 is well designed for very low power  
system applications, and particularly well suited for  
battery back-up nonvolatile memory application.  
„ Tri-state output  
„ Data retention voltage : 1.5V (MIN.)  
„ Green package available  
„ Package : 28-pin 600 mil PDIP  
28-pin 330 mil SOP  
The LY6264 operates from a single power supply  
of 2.7~5.5V and all inputs and outputs are fully TTL  
compatible  
28-pin 8mm x 13.4mm STSOP  
28-pin 300 mil Skinny P-DIP  
PRODUCT FAMILY  
Product  
Family  
Operating  
Temperature  
0 ~ 70℃  
-20 ~ 80℃  
-40 ~ 85℃  
Power Dissipation  
Speed  
Vcc Range  
Standby(ISB1,TYP.)  
Operating(Icc,TYP.)  
20/15/10mA  
LY6264  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
35/55/70ns  
35/55/70ns  
35/55/70ns  
1µA  
1µA  
1µA  
LY6264(E)  
LY6264(I)  
20/15/10mA  
20/15/10mA  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
A0 - A12  
DESCRIPTION  
Address Inputs  
Vcc  
Vss  
DQ0 – DQ7 Data Inputs/Outputs  
CE#, CE2  
WE#  
OE#  
Chip Enable Inputs  
Write Enable Input  
Output Enable Input  
Power Supply  
8Kx8  
MEMORY ARRAY  
A0-A12  
DECODER  
VCC  
VSS  
Ground  
NC  
No Connection  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
CE2  
WE#  
OE#  
CONTROL  
CIRCUIT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
PIN CONFIGURATION  
NC  
A12  
A7  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Vcc  
WE#  
CE2  
A8  
3
OE#  
A11  
A9  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
Vss  
DQ2  
DQ1  
DQ0  
A0  
A6  
4
A5  
5
A9  
A8  
A4  
6
A11  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
CE2  
WE#  
Vcc  
NC  
A12  
A7  
A6  
A5  
A4  
A3  
A3  
7
LY6264  
A2  
8
A1  
9
A0  
10  
11  
12  
13  
14  
A1  
A2  
DQ0  
DQ1  
DQ2  
Vss  
STSOP  
Skinny P-DIP/P-DIP/SOP  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 6.5  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
H
CE2  
X
OE#  
X
WE#  
X
SUPPLY CURRENT  
ISB,ISB1  
MODE  
I/O OPERATION  
High-Z  
Standby  
X
L
X
X
High-Z  
ISB,ISB1  
L
H
H
H
Output Disable  
Read  
High-Z  
ICC,ICC1  
L
H
L
H
DOUT  
ICC,ICC1  
L
H
X
L
Write  
DIN  
ICC,ICC1  
Note: H = VIH, L = VIL, X = Don't care.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
2.4  
- 0.5  
- 0.5  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
Input High Voltage  
VCC  
3.3  
5.5  
VCC+0.5  
0.6  
V
V
V
V
*1  
VIH  
-
-
-
-
VCC=2.7~3.6V  
CC=4.5~5.5V  
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
*2  
Input Low Voltage  
VIL  
V
V
V
0.8  
1
Input Leakage Current  
Output Leakage  
Current  
ILI  
A
µ
ILO  
- 1  
-
1
A
µ
Output Disabled  
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
VOL IOL = 2mA  
Cycle time = Min.  
CE# = VIL and CE2 = VIH,  
I/O = 0mA  
Other pins at VIL or VIH  
Cycle time = 1 s  
2.4  
-
3.0  
-
-
V
V
0.4  
50  
20  
-35  
-55  
-70  
-
-
-
mA  
ICC  
15  
10  
45  
40  
mA  
mA  
I
Average Operating  
Power supply Current  
µ
≦
≧
CE# 0.2V and CE2 VCC-0.2V,,  
ICC1  
-
3
10  
mA  
II/O = 0mA  
other pins at 0.2V or VCC-0.2V  
CE# = VIH or CE2 = VIL  
Other pins at VIL or VIH  
LL  
ISB  
-
1
3
mA  
-
-
1
1
20  
30  
A
µ
A
µ
LLE/LLI  
Standby Power  
Supply Current  
CE# ≧VCC-0.2V  
SL*5  
℃
-
-
1
3
4
A
25  
µ
µ
≦
or CE2 0.2V  
ISB1  
SLE*5  
SLI*5  
Others at 0.2V or  
℃
1.5  
A
40  
VCC - 0.2V  
SL  
-
-
1
1
10  
20  
A
µ
A
µ
SLE/SLI  
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
5. This parameter is measured at VCC = 3.0V  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
tRC  
UNIT  
LY6264-35  
LY6264-55  
MIN. MAX.  
55  
LY6264-70  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
35  
-
-
-
10  
5
-
-
70  
-
-
-
10  
5
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
35  
35  
25  
-
-
-
-
10  
5
-
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
*
*
*
*
-
-
-
-
-
10  
15  
15  
-
20  
20  
-
-
-
10  
25  
25  
-
-
10  
(2) WRITE CYCLE  
PARAMETER  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
LY6264-35  
LY6264-55  
MIN. MAX.  
55  
LY6264-70  
MIN.  
35  
30  
30  
0
MAX.  
MIN.  
70  
60  
60  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
50  
50  
0
-
-
-
-
-
tWP  
tWR  
tDW  
tDH  
tOW  
25  
0
-
-
45  
0
-
-
55  
0
-
-
20  
0
-
-
25  
0
-
-
30  
0
-
-
*
5
-
5
-
5
-
tWHZ  
*
-
15  
-
20  
-
25  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
CE2  
WE#  
Dout  
Din  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
CE2  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high or CE2 must be low during all address transitions.  
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.  
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high  
impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data Retention  
SYMBOL  
VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V  
LL/LLE/LLI  
TEST CONDITION  
MIN.  
1.5  
-
TYP. MAX. UNIT  
-
5.5  
20  
V
0.5  
A
µ
SL  
V
CC = 1.5V  
℃
-
-
0.5  
1
2
3
A
A
25  
µ
CE# ≧ VCC - 0.2V  
or CE2 ≦ 0.2V  
Othersat 0.2V or VCC-0.2V  
SLE  
SLI  
SL  
Data Retention Current  
IDR  
℃
40  
µ
-
-
0.5  
0.5  
8
15  
A
µ
A
µ
SLE/SLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Low Vcc Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low Vcc Data Retention Waveform (2) (CE2 controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
CE2 ≦ 0.2V  
CE2  
VIL  
VIL  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
PACKAGE OUTLINE DIMENSION  
28 pin 600 mil PDIP Package Outline Dimension  
UNIT  
SYM.  
INCH.(BASE)  
MM(REF)  
A1  
A2  
B
B1  
c
0.010 (MIN) 0.254 (MIN)  
0.150±0.005 3.810±0.127  
0.020 (MAX) 0.508(MAX)  
0.055 (MAX) 1.397(MAX)  
0.012 (MAX) 0.304 (MAX)  
1.430 (MAX) 36.322 (MAX)  
D
E
0.6 (TYP)  
15.24 (TYP)  
E1  
e
eB  
L
0.52 (MAX)  
13.208 (MAX)  
0.100 (TYP) 2.540(TYP)  
0.625 (MAX) 15.87 (MAX)  
0.180(MAX) 4.572(MAX)  
S
Q1  
Θ
0.06 (MAX)  
0.08(MAX)  
15o(MAX)  
1.524 (MAX)  
2.032(MAX)  
15o(MAX)  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
28 pin 330 mil SOP Package Outline Dimension  
UNIT  
SYM.  
INCH(BASE)  
0.120 (MAX) 3.048 (MAX)  
0.002(MIN) 0.05(MIN)  
0.098±0.005 2.489±0.127  
0.016 (TYP) 0.406(TYP)  
0.010 (TYP) 0.254(TYP)  
0.728 (MAX) 18.491 (MAX)  
0.340 (MAX) 8.636 (MAX)  
0.465±0.012 11.811±0.305  
0.050 (TYP) 1.270(TYP)  
MM(REF)  
A
A1  
A2  
b
c
D
E
E1  
e
L
0.05 (MAX)  
1.270 (MAX)  
L1  
S
y
0.067±0.008 1.702 ±0.203  
0.047 (MAX) 1.194 (MAX)  
0.003(MAX) 0.076(MAX)  
o
o
o
o
Θ
～
～
10  
0
10  
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
28 pin 8x13.4mm STSOP Package Outline Dimension  
HD  
c
L
12° (2x)  
12° (2x)  
1
28  
14  
15  
"A"  
y
Seating Plane  
D
12° (2X)  
14  
15  
GAUGE PLANE  
0
SEATING PLANE  
12° (2X)  
L
1
28  
L1  
"A" DATAIL VIEW  
DIMENSIONS IN MILLIMETERS  
DIMENSIONS IN INCHES  
SYMBOLS  
MIN  
1.00  
0.05  
0.91  
0.17  
0.10  
13.20  
11.70  
7.90  
-
0.30  
0.675  
0.00  
0°  
NOM  
1.10  
-
MAX  
1.20  
0.15  
1.05  
0.27  
0.20  
13.60  
11.90  
8.10  
-
MIN  
NOM  
0.043  
-
MAX  
A
A1  
A2  
b
c
HD  
D
E
e
L
L1  
Y
0.040  
0.002  
0.036  
0.007  
0.004  
0.520  
0.461  
0.311  
-
0.012  
0.027  
0.000  
0°  
0.047  
0.006  
0.041  
0.011  
0.008  
0.535  
0.469  
0.319  
-
1.00  
0.22  
0.15  
13.40  
11.80  
8.00  
0.55  
0.50  
-
0.039  
0.009  
0.006  
0.528  
0.465  
0.315  
0.0216  
0.020  
-
0.70  
-
0.028  
-
-
3°  
0.076  
5°  
-
3°  
0.003  
5°  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
28 pin 300 mil PDIP Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
ORDERING INFORMATION  
LY6264 U V - WW XX Y Z  
Z : Packing Type  
Blank : Tube or Tray  
T : Tape Reel  
Y : Temperature Range  
Blank : (Commercial) 0°C ~ 70°C  
E : (Extended) -20°C ~ +80°C  
I : (Industrial) -40°C ~ +85°C  
XX : Power Type  
LL : Ultra Low Power  
SL : Special Ultra Low Power  
WW : Access Time(Speed)  
V : Lead Information  
L : Green Package  
U : Package Type  
P : 28-pin 600 mil P-DIP  
S : 28-pin 330 mil SOP  
R : 28-pin 8 mm x 13.4 mm STSOP  
D : 28-pin 300 mil P-DIP  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
®
LY6264  
8K X 8 BIT LOW POWER CMOS SRAM  
Rev. 2.6  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
13  
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