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5V7855SWFR

型号：

5V7855SWFR

描述：

EEPROM可编程的PLL死LVCMOS晶振[ EEPROM Programmable PLL Die for LVCMOS Crystal Oscillator ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

14 页

PDF大小：

1061 K

下载PDF手册
EEPROM Programmable PLL Die for  
LVCMOS Crystal Oscillator  
IDT5V7855  
DATA SHEET  
General Description  
Features  
The IDT5V7855 is a programmable PLL-based clock generator used  
for crystal oscillator modules. The device incorporates an on-chip  
crystal oscillator with a programmable capacitor tuning array to  
support direct connection with fundamental-mode crystals between  
16MHz – 50MHz. The capacitor tuning array offers a total of 9 bits of  
resolution and provides a step of 0.01pF.  
• Input: 16MHz – 50MHz fundamental mode crystal  
• Output frequency range: 1MHz – 170MHz in PLL mode,  
1MHz – 50MHz in non-PLL mode  
• On-chip EEPROM to store device configuration  
– 19-bit high-resolution fractional programmable multiplier  
– 3-bit prescaler  
– 7-bit output divider  
– 9-bit crystal oscillator tuning capacitor array  
– Selectable function power down or OE control pin  
The device incorporates on-chip non-volatile EEPROM cells which  
can store all the device settings and maintain them even when there  
is no power. The serial programming interface is implemented with  
dual-use pins for the clock and data. The CONT input can be  
programmed as either a power down input or an output enable input.  
Crystal oscillator modules using this device can be stocked as blank  
parts and custom frequencies programmed in package at the last  
stage before shipping. This enables fast-turn manufacture of custom  
and standard crystal oscillators without the need for expensive  
dedicated crystals.  
• In-package serial programming interface through dual-use pins  
• Full 2.5V and 3.3V operating supply  
• Maximum frequency shift across supply voltage: 1ppm  
• Available in die pack, lead-free RoHS compliant  
• ESD Human Body Model (HBM) and Machine Model (MM):  
– HBM: 2000V  
– MM: 200V  
The IDT PLL uses a patent-pending fractional multiplier technique to  
provide ultra-high resolution multiplication and division from input to  
output with low jitter. In addition, prescaler and post-  
• Small die size: 0.75mm x 0.75mm  
• Supports 20mm x 16mm package size  
• -40°C to 85°C ambient operating temperature  
divider circuits are included to enhance the granularity of clock  
scaling. The PLL may also be bypassed in order to operate the  
device as a non-PLL fundamental-mode crystal oscillator for  
applications that do not require frequency multiplication. The device  
is fabricated using advance technology and can support both 2.5V  
and 3.3V operation. The device is small enough to fit into  
small-footprint crystal oscillators. This is the industry’s smallest  
programmable die and can support crystal oscillator packages as  
small as 20mm x 16mm.  
Functional Block Diagram  
Pad Assignment  
VDD  
1
2
3
0
1
x2  
Output  
Divider  
xg  
OUT  
VDD  
÷2  
8
OUT  
OSC  
PFD  
VCO  
Pre-Scaler  
3-bit  
xd  
xd  
7-bit  
Fractional  
Multiplier  
xg  
Tuning  
Cap  
4
5
19-bit  
VSS  
CONT  
6
7
9-bit  
EEPROM  
IDT5V7855  
Pullup  
CONT  
0.75mm x 0.75mm Die  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
1
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Table 1. Pad Descriptions  
Number  
1, 2  
Name  
VDD  
Type  
Description  
Power  
Input  
Power supply pins. Both pads must be bonded.  
3, 4  
xd, xg  
Crystal oscillator interface. xg is the input. xd is the output.  
Programmable to function as power down or output enable. Serves as VPP and data  
input during programming mode.  
5
CONT  
Input  
Pullup  
Power supply ground. Only one pad should be bonded. Either pad can be used to  
accommodate optimal bond wire placement  
6, 7  
8
VSS  
Power  
I/O  
OUT  
Single-ended clock output. Serves as clock input during programming mode.  
NOTE: Pullup refers to internal input resistor.  
Table 2. Pad Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
51  
Maximum  
Units  
kΩ  
Ω
RPULLUP  
Input Pullup Resistor  
VDD = 3.3V  
25  
ROUT  
Output Impedance  
VDD = 2.5V  
37  
Ω
IDT5V7855-DPK REVISION A MARCH 11, 2010  
2
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Functional Description  
The output frequency of the IDT5V7855 is determined by the crystal  
frequency and the three programmable divider/multiplier registers:  
Prescaler (P), Fractional Multiplier (M), and Output Divider (D). The  
prescaler (P) is a 3-bit integer register while the output divider (D) is  
a 7-bit integer register. The fractional multiplier (M) is a 19-bit register  
and has the feature of a fractional component in addition to the  
integer value. This allows the IDT5V7855 to be programmed to a  
wide variety of output frequencies from a single input crystal  
frequency.  
Table 3A. Prescaler Table  
Crystal Range  
(MHz)  
Prescaler  
(P)  
Phase Detector Frequency  
(MHz)  
16 – 50  
16 – 50  
1
2
3
4
5
6
7
16 – 50  
8 – 25  
16 – 50  
5.3333 – 16.6667  
5.3125 – 12.5  
5.3125 – 10  
21.25 – 50  
26.5625 – 50  
31.875 – 50  
37.1875 – 50  
5.3125 – 8.3333  
5.3125 – 7.1429  
Figure 1. Simplified Block Diagram  
Fractional Multiplier (M)  
The actual values which may be programmed into the various  
registers depend on the specified operational ranges of some of the  
PLL components such as the VCO and crystal oscillator. As shown  
in tables 5 and 6A, these ranges are:  
The Fractional Multiplier (M) is a 19-bit register. The operational  
range of the fractional multiplier is 3.4 to approximately 32 (actually  
31.99993896). The decimal multiplier value obtained from the 19-bit  
fractional multiplier register can be determined as:  
VCO Range: 170MHz to 340MHz  
XTAL Oscillator Range: 16MHz to 50MHz  
MBIN  
MDEC = ----------------  
16384  
The minimum value permitted for the feedback register is a function  
of the minimum VCO frequency and the maximum phase detector  
reference frequency. The maximum phase detector reference  
frequency is set by the maximum crystal frequency (50MHz) divided  
by the minimum prescaler divider (1) and is therefore 50MHz. The  
feedback fractional multiplier register operational range can be  
determined as:  
MDEC is the fractional multiplier (decimal) value  
MBIN is the value programmed in the 19-bit register  
The fractional portion of the fractional multiplier allows a  
programming frequency resolution to 61/MDEC ppm. Note that higher  
MDEC values will produce lower ppm error.  
M Min: 170MHz ÷ 50MHz = 3.4  
M Max: 31.9993896 ≈ 32  
The maximum value that can be programmed into the fractional  
multiplier (all 19 bits “1”) is approximately 32 (actual value is  
31.99993896).  
Examples:  
For a fractional multiplier register MBIN of  
1010101000000000000 binary  
Given the VCO range and the feedback divider range, the minimum  
phase detector frequency can be determined from the minimum VCO  
frequency and the maximum feedback divider as:  
348160  
16384  
MDEC = ------------------- = 21.2500  
Phase Detector Min: 170MHz ÷ 32 = 5.3125MHz  
Phase Detector Max: 50MHz  
The ppm resolution (single LSB bit change in the MBIN) for this setting  
is:  
The maximum value is set by the specified maximum crystal  
frequency.  
61ppm  
21.25  
------------------ = 2.9ppm  
For a fractional multiplier register MBIN of  
0010101010000000000 binary  
Prescaler (P)  
87040  
The Prescaler (P) divides down the input crystal frequency prior to  
the internal phase detector. The prescaler register is a 3-bit register  
so the possible values which may be programmed are 1 through 7.  
MDEC = ---------------- = 5. 312 5  
16384  
The ppm resolution (single LSB bit change in the MBIN) for this setting  
is:  
The specified input crystal frequency range is: 16MHz to 50MHz and  
the phase detector range is: 5.3125MHz to 50MHz. So the possible  
settings and ranges are:  
61ppm  
------------------ = 11.5ppm  
5.3125  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
3
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Output Divider (D)  
The Output Divider register is a 7-bit register so the possible values  
which may be programmed are 1 through 127. Combining the  
information from the three registers, including the final output divider  
and the crystal frequency, the output frequency may be derived.  
Using table 3B, identify the crystal frequency from the given ranges  
and select the associated prescaler (P) value. The phase detector  
frequency is then calculated as:  
FXTAL  
----------------  
=
FPHASE – DET  
The actual frequency produced from a given crystal frequency may  
be determined as:  
P
Table 3B. Crystal Range Table  
MDEC  
P x(D x 2)  
FOUT = (FXTAL) x --------------------------  
Crystal Range  
(MHz)  
Prescaler (P)  
Phase Detector  
Frequency (MHz)  
FOUT  
is the output frequency  
16 – 50  
16 – 50  
1
2
3
4
5
6
16 – 50  
8 – 25  
FXTAL is the Crystal Frequency  
P
D
is the Prescaler Value  
is the Output Divider Value  
16 – 50  
5.3333 – 16.6667  
5.3125 – 12.5  
5.3125 – 10  
5.3125 – 8.3333  
MDEC is the Fractional Divider (decimal) Value  
21.25 – 50  
26.5625 – 50  
31.875 – 50  
Fine Frequency Adjustment  
The IDT5V7855 also has a fine frequency adjustment capability  
utilizing adjustable tuning capacitors in the crystal oscillator. These  
capacitors are set through a tuning capacitor register which is a 9-bit  
register and the resolution of the tuning capacitance is approximately  
0.01pF per bit. The frequency ppm tuning performance can be found  
by:  
Identify the range(s) that match the desired output frequency and  
select the associated Output Divider (D) value. The VCO frequency  
is then calculated as:  
FVCO = (FOUT x D x 2)  
C1  
2
1
1
6
FREQ(ppm) = -------x ----------------------------------------------------------------- –  
x10 ppm  
---------------------  
Table 3C. FVCO Table  
C0 + CL +CSTEP x TREG  
C0 + CL  
Output Frequency Range  
(MHz) FOUT  
VCO  
C1  
C0  
CL  
is the Crystal Motional Capacitance  
is the Crystal Shunt Capacitance  
Output Divider Frequency  
(D)  
(MHz)  
is the Inherent (parasitic) Load Capacitance  
85.0000 – 170.0000  
42.5000 – 85.0000  
28.3333 – 56.6667  
21.2500 – 42.5000  
17.0000 – 34.0000  
14.1667 – 28.3333  
• • •  
1
170 – 340  
170 – 340  
170 – 340  
170 – 340  
170 – 340  
170 – 340  
• • •  
CSTEP is the Tuning Capacitance Resolution 0.01pF  
TREG is the Tuning Capacitor Register Value from 0 to 511  
2
3
4
Determining the Appropriate Register Settings  
A typical use for this type of device is generating virtually any  
frequency between 1MHz to 170MHz from a single crystal frequency  
value. The steps required to accomplish this are:  
5
6
• • •  
125  
126  
127  
1. Determine the crystal frequency.  
0.6800 – 1.3600 (NOTE)  
0.6746 – 1.3492 (NOTE)  
0.6693 – 1.3386 (NOTE)  
170 – 340  
170 – 340  
170 – 340  
2. Determine the desired output frequency.  
3. Determine the proper prescaler value using the crystal  
frequency and the associated phase detector frequency.  
4. Determine the proper output divider using the desired  
output frequency to optimize the internal VCO frequency.  
NOTE: The specified minimum output frequency is 1MHz. While  
output frequencies less than 1MHz are possible, specified device  
performance is not guaranteed.  
5. Determine the appropriate fractional multiplier value using  
the phase detector frequency and the VCO frequency.  
6. Determine the MBIN value by multiplying the MDEC value  
by 16384.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
4
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
The fractional multiplier is determined from the phase detector  
frequency and the VCO frequency using the following equations.  
3. The fractional multiplier is calculated as the VCO frequency  
divided by the phase detector frequency. So, for the  
possible combinations identified, the resulting fractional  
multiplier could be one of nine possibilities.  
Calculate the fractional multiplier decimal value:  
FVCO  
MDEC = -----------------------------------  
FPHASE – DET  
Table 3D. Fractional Multiplier Table  
P = 1  
FPHASE_DET  
(48MHz)  
P = 2  
FPHASE_DET  
(24MHz)  
P = 3  
FPHASE_DET  
(16MHz)  
Calculate the fractional multiplier register binary value:  
M
BIN = MDEC x 16384  
200MHz  
200MHz  
200MHz  
16MHz  
12.5  
D = 4  
FVCO  
200MHz  
MDEC = ---------------------- MDEC= ---------------------- MDEC = ----------------------  
48MHz  
4.16666  
250MHz  
24MHz  
8.33333  
250MHz  
=
Example 1:  
The crystal frequency is 27MHz and the desired output frequency is  
166.66667MHz.  
250MHz  
16MHz  
15.625  
D = 5  
FVCO  
250MHz  
MDEC = ---------------------- MDEC= ---------------------- MDEC = ----------------------  
48MHz  
5.20833  
300MHz  
24MHz  
=
1. With a crystal frequency of 27MHz, the appropriate  
prescaler value is 1 and the associated phase detector  
frequency would be: 27MHz ÷ 1 = 27MHz.  
10.41666  
300MHz  
24MHz  
12.5  
300MHz  
16MHz  
18.75  
D = 6  
FVCO  
300MHz  
MDEC = ---------------------- MDEC = ---------------------- MDEC= ----------------------  
48MHz  
6.5  
=
2. For an output frequency of 166.6667MHz, the output  
divider which can be used with a VCO frequency in the proper  
170MHz to 340MHz range is 1, and the resulting  
VCO frequency is: 166.6667MHz x 1 x 2 = 333.33MHz.  
4. With the different MDEC values to choose from, how does  
one select the ‘best’ value? In general, selecting a fractional  
value which reduces the ppm error is the first selection  
criteria. This applies to MDEC values which have the fewest  
non-zero decimal places or MDEC values which have large  
integer values. This criteria would eliminate the  
3. The fractional multiplier is calculated as the VCO frequency  
divided by the phase detector frequency or  
333.33MHz ÷ 27MHz = 12.345679.  
4. The MBIN is found by 12.345679 x 16384 = 202271.6 and is  
rounded to 202272.  
MDEC = 4.16666, 5.208333, 8.33333, and 10.4166666  
options. After the ppm error selection is made and if there are  
still other options, generally the higher VCO frequency will  
provide better performance. In this example, the higher VCO  
frequency corresponds with D = 6 and the associated P and  
MDEC values of 1 and 6.25, 2 and 12.5, or 3 and 18.75. Lastly,  
the higher phase detector frequency generally provides better  
performance. So for this example, the condition of P = 1,  
MDEC = 6.25, and D = 6 would be the preferred choice.  
5. Due to the rounding, the actual MDEC value will be 12.3457  
and the actual output frequency will be:  
MDEC  
12.3457  
1x1 x 2  
FOUT = FXTAL x -------------------------- = 27MHz x ---------------------  
P x(D x 2)  
FOUT = 166.66699MHz  
(NOTE: This is an error of only 1.94ppm.)  
5. The MBIN is found by: 6.25 x 16384 = 102400. (No rounding is  
necessary.)  
Example 2:  
The starting crystal frequency is 48MHz and the desired output  
frequency is 25MHz.  
6. Verifying the values  
MDEC  
1. With a starting crystal frequency of 48MHz, the appropriate  
prescaler value can be either 1, 2 or 3 and the associated  
phase detector frequency would be either:  
48MHz ÷ 1 = 484MHz,  
12.5  
2 x6 x 2  
FOUT = FXTAL x -------------------------- = 48MHz x ---------------------  
P x(D x 2)  
48MHz ÷ 2 = 24MHz or,  
48MHz ÷ 3 = 16MHz.  
2. For an output frequency of 25MHz, the output dividers  
which can be used with a VCO frequency in the proper  
170MHz to 340MHz range are: 4, 5, or 6, and the resulting  
VCO frequencies is: 200MHz, 250MHz, or 300MHz.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
5
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Programming Instructions  
The IDT5V7855 registers, along with some control functions, are  
written and the EEPROM burned through a serial write using the  
CONT and OUT pins. During the programming the CONT pin  
functions as a Data input while the OUT pin functions as a Clock  
input. The data registers are not addressed individually but are all  
written sequentially with the most significant bit first. All registers  
must be written when programming the device. The order of registers  
/ control bits and the number of bits per register are:  
9 bits  
19 bits  
3 bits  
3 bits  
1 bit  
Tuning Capacitor Register T[8:0]  
Fractional Multiplier Register M[18:0]  
Prescaler Register P[2:0]  
Factory Test Mode Register F[2:0]  
PLL Bypass Mode (0 = crystal oscillator connected directly to output divider, 1 = PLL used)  
Power Down Control (0 = CONT acts as an output enable, 1 = CONT acts as power down)  
Output Enable Type (0 = synchronous output enable, 1 = asynchronous output enable)  
Output Divider Register D[6:0]  
1 bit  
1 bit  
7 bits  
Table 3E. Register Table  
Register  
Name  
Tuning  
Capacitor  
Fractional  
Multiplier  
Prescaler  
(P)  
Factory Test  
Mode  
PLL  
Mode  
Power Down OutputEnable  
Output  
Divider  
Control  
Control  
# of Bits  
Symbol  
9-bit  
19-bit  
3-bit  
3-bit  
1-bit  
1-bit  
1-bit  
7-bit  
T[8:0]  
M[18:0]  
P[2:0]  
F[2:0]  
D[6:0]  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
6
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
The procedure to program the registers and control bits without writing to the EEPROM is as follows:  
1.  
2.  
3.  
4.  
Set CONT and OUT to 0.0 volts with no power applied.  
Apply power, wait for 1ms.  
Apply four clock pulses on OUT to enter serial programming mode (see timing diagram below).  
Enter serial data (bit order as described above) via the CONT pin, with a positive pulse on OUT pin for each data bit.  
NOTE: CONT must only change while OUT is LOW to write the data properly.  
5.  
To activate the registers and exit serial programming mode, while OUT is held LOW, set CONT HIGH.  
After 1µs with CONT still HIGH, set OUT HIGH. After 1µs with OUT still HIGH, set CONT LOW.  
6.  
7.  
Remove the programming voltage from OUT pin.  
Enable the output by setting CONT HIGH.  
Figure 2. Timing Diagram  
3F. Timing/Voltage Requirements Table  
Symbol  
Parameter  
Minimum  
Maximum  
Units  
ms  
µs  
ts  
td  
Enter Serial Data Mode  
Data & Clock Timing  
Supply Voltage  
1
1
VDD  
2.2  
3.6  
V
IDT5V7855-DPK REVISION A MARCH 11, 2010  
7
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
The procedure to program the registers and control bits and write the data to the EEPROM is as follows:  
1.  
2.  
3.  
4.  
5.  
Set CONT and OUT to 0.0 volts with no power applied.  
Apply power, wait for 1ms.  
Apply four clock pulses to OUT to enter serial programming mode (see timing diagram below).  
Wait 1ms.  
Apply EEPROM programming pulse (12V) on CONT to erase EEPROM.  
[WARNING: Do not apply High Voltage Programming pulse prior to entering serial mode.]  
6.  
7.  
Wait 1ms.  
Enter serial data (bit order as described above) via the CONT pin, with a positive pulse on OUT pin for each data bit.  
NOTE: CONT must only change while OUT is LOW to write the data properly.  
8.  
Complete the serial write with a Stop Bit set to 0.  
9.  
Wait 1ms  
10.  
11.  
While OUT is held LOW, apply EEPROM programming pulse (12V) to CONT to store the data in EEPROM.  
Remove power from the device.  
Figure 3. Timing Diagram  
3G. Timing/Voltage Requirements Table  
Symbol  
ts  
Parameter  
Test Conditions  
Minimum  
Maximum  
Units  
ms  
µs  
Enter Serial Data Mode  
Data & Clock Timing  
1
1
td  
tp  
Programming EEPROM Timing  
Rise/Fall Time of VPP  
Supply Voltage; NOTE  
Programming EEPROM Voltage  
100  
110  
5
ms  
ms  
V
tR / tF  
VDD  
VPP  
10% - 90%  
2.2  
3.6  
12.5  
11.5  
V
NOTE: The supply voltage on VDD must be able to sink at least 2mA when VPP is applied to CONT to ensure transient currents are safely  
absorbed. Alternatively, a 1kΩ resistor may be connected between VDD and GND during programming.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
8
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs/Outputs, VI / VO; NOTE  
Storage Temperature, TSTG  
4.6V  
-0.5V to VDD + 0.5V  
-65°C to 150°C  
NOTE: 12.5V can be applied to the CONT pin during serial programming mode only after applying four clock pulses to the OUT pin.  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, VDD = 2.3V to 3.6V, TA = -40°C to 85°C  
Symbol Parameter  
VDD Power Supply Voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
V
2.3  
3.0  
3.6  
6
No Load  
No Load  
PWRDN  
f
OUT = 50MHz, Non-PLL mode  
fOUT = 170MHz, PLL mode  
Power-Down Mode  
mA  
mA  
µA  
IDD  
Power Supply Current  
15  
40  
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.7V to 3.6V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
VOUT = ≥ VOH (min.)  
VOUT = ≤ VOH (max.)  
Minimum  
Typical  
Maximum  
Units  
VIH  
VIL  
IIN  
Input High Voltage  
Input Low Voltage  
2
VDD + 0.3  
V
V
-0.3  
0.8  
5
CONT  
VIN = max.;  
Input Current  
µA  
V
OUT  
VIN = 0V or VIN = VDD  
15  
IOH = -100µA  
IOH = -4mA  
IOL = 100µA  
IOL = 4mA  
VDD – 0.2  
2.2  
Output  
High Voltage  
VOH  
VDD = min. VI = VIH or VIL  
0.2  
0.4  
Output  
Low Voltage  
VOL  
VDD = min. VI = VIH or VIL  
V
IDT5V7855-DPK REVISION A MARCH 11, 2010  
9
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 2.3V to 2.7V, TA = -40°C to 85°C  
Symbol  
VIH  
Parameter  
Test Conditions  
VOUT = ≥ VOH (min.)  
VOUT = ≤ VOH (max.)  
VIN = max.;  
Minimum  
1.7  
Typical  
Maximum  
Units  
Input High Voltage  
Input Low Voltage  
VDD + 0.3  
V
V
VIL  
-0.3  
0.7  
5
Input  
Curren  
t
CONT  
OUT  
IIN  
µA  
VIN = 0V or VIN = VDD  
15  
IOH  
-100µA  
=
2.1  
Output  
High  
VDD = min.;  
VOH  
V
Voltag IOH = -1mA  
VI = VIH or VIL  
2
e
IOH = -2mA  
1.7  
IOH  
-100µA  
=
0.2  
Output  
Low  
VDD = min.;  
VOL  
V
Voltag IOH = -1mA  
VI = VIH or VIL  
0.4  
0.7  
e
IOH = -2mA  
AC Electrical Characteristics  
Table 6. AC Characteristics, VDD = 2.3V to 3.6V, TA = -40°C to 85°C  
Symbol Parameter  
fVCO VCO Frequency  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
MHz  
MHz  
MHz  
170  
1
340  
170  
50  
PLL Mode  
fOUT  
Output Frequency  
Non-PLL Mode  
1
Measured over 50,000 cycles;  
fOUT > 40MHz  
PLL Mode  
30  
9
ps  
ps  
ps  
ps  
ps  
ps  
Period Jitter, RMS;  
NOTE 1, 2  
tjit(per)  
Measured over 50,000 cycles;  
fOUT > 16MHz  
Non-PLL Mode  
PLL Mode  
Measured over 50,000 cycles;  
230  
90  
f
OUT > 40MHz  
Peak-to-Peak Jitter;  
NOTE 1, 2  
tp-p  
Measured over 50,000 cycles;  
fOUT > 16MHz  
Non-PLL Mode  
PLL Mode  
Measured over 50,000 cycles;  
fOUT > 40MHz  
130  
75  
Cycle-to-Cycle Jitter;  
NOTE 1, 2  
tjit(cc)  
Measured over 50,000 cycles;  
fOUT > 16MHz  
Non-PLL Mode  
tR / tF  
odc  
Output Rise/Fall Time; NOTE 2  
Output Duty Cycle; NOTE 2  
Oscillation Startup Time  
fOUT > 40MHz, 20% to 80%  
100  
48  
700  
52  
ps  
%
PLL  
Bypass  
45  
55  
%
tOSC  
10  
ms  
NOTE 1: Measured on Wavecrest SIA3000.  
NOTE 2: Output terminated with 50Ω to VDD/2.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
10  
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Parameter Measurement Information  
1.65V 0.15V  
1.25V 0.15V  
SCOPE  
SCOPE  
V
DD  
V
DD  
Qx  
Qx  
LVCMOS  
LVCMOS  
GND  
GND  
1.65V 0.15V  
-1.25V 0.15V  
3.3V Output Load AC Test Circuit  
2.5V Output Load AC Test Circuit  
VOH  
VREF  
OUT  
VOL  
➤
➤
tcycle n  
tcycle n+1  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
➤
➤
tjit(cc) = tcycle n – tcycle n+1  
|
|
1000 Cycles  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
Cycle-to-Cycle Jitter  
Period Jitter  
VDD  
2
80%  
80%  
OUT  
tPW  
tPERIOD  
20%  
20%  
OUT  
tR  
tF  
tPW  
x 100%  
odc =  
tPERIOD  
Output Duty Cycle/Pulse Width/Period  
Output Rise/Fall Time  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
11  
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Pad Information  
Table 7. Bond Pad Coordinates  
Pad  
Name  
Pad Size (µm)  
Coordinates  
X(µm)  
-266  
-266  
-266  
-266  
-266  
161  
Y(µm)  
266  
1
2
3
4
5
6
7
8
VDD  
VDD  
xd  
75 x 75  
75 x 75  
75 x 75  
75 x 75  
75 x 75  
75 x 75  
75 x 75  
75 x 75  
161  
56  
xg  
-161  
-266  
-266  
-266  
219  
CONT  
VSS  
VSS  
OUT  
266  
191  
NOTE: Pad locations specify the center of the pad relative to the center of the die.  
NOTE The substrate of the die should be connected to VSS  
.
NOTE: Not all of the VSS pads need to be bonded, but all of the VDD pads need to be bonded.  
Ordering Information  
Table 8. Ordering Information  
Part/Order Number  
5V7855-DPK  
5V7855SWFR  
Package  
Die  
Sawn Wafer  
Shipping Packaging  
Waffle  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
Film Frame  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the  
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal  
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without  
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support  
devices or critical medical instruments.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
12  
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
Revision History Sheet  
Rev  
Table  
Page  
Description of Change  
Date  
7
Deleted procedure 5. Complete the serial write with a Stop Bit set to 0.  
Updated Figure 2. Timing Diagram.  
A
2/20/08  
3/11/10  
A
T8  
12  
Ordering Information Table - added Sawn Wafer package.  
IDT5V7855-DPK REVISION A MARCH 11, 2010  
13  
©2010 Integrated Device Technology, Inc.  
IDT5V7855 Data Sheet  
EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
San Jose, California 95138  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT  
product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2010. All rights reserved.  
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 		5V7855-DPK EEPROM可编程的PLL死LVCMOS晶振[ EEPROM Programmable PLL Die for LVCMOS Crystal Oscillator ] 14 页

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