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LY62W5128I

型号：

LY62W5128I

描述：

512K ×8位低功耗CMOS SRAM[ 512K X 8 BIT LOW POWER CMOS SRAM ]

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

11 页

PDF大小：

166 K

下载PDF手册
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
REVISION HISTORY  
Revision  
Rev. 1.a  
Description  
Initial Issue  
Issue Date  
Jul.15.2009  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
FEATURES  
GENERAL DESCRIPTION  
The LY62W5128 is a 4,194,304-bit low power  
CMOS static random access memory organized as  
524,288 words by 8 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
„ Fast access time : 55ns  
„ Low power consumption:  
Operating current : 30mA (TYP.)  
Standby current : 4μA (TYP.)  
„ Single 2.7V ~ 5.5V power supply  
„ All outputs TTL compatible  
„ Fully static operation  
The LY62W5128 is well designed for very low power  
system applications, and particularly well suited for  
battery back-up nonvolatile memory application.  
„ Tri-state output  
„ Data retention voltage : 1.5V (MIN.)  
„ Green package available  
„ Package : 32-pin 400 mil TSOP-II  
The LY62W5128 operates from a single power  
supply of 2.7V ~ 5.5V and all inputs and outputs are  
fully TTL compatible  
PRODUCT FAMILY  
Product  
Family  
Operating  
Temperature  
Power Dissipation  
Speed  
Vcc Range  
Standby(ISB1TYP.) Operating(Icc,TYP.)  
0 ~ 70℃  
-20 ~ 80℃  
-40 ~ 85℃  
LY62W5128  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
55ns  
55ns  
55ns  
4µA  
4µA  
4µA  
30mA  
30mA  
30mA  
LY62W5128(E)  
LY62W5128(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0 - A18  
Vcc  
Vss  
DQ0 – DQ7 Data Inputs/Outputs  
CE#  
WE#  
OE#  
VCC  
VSS  
Chip Enable Inputs  
Write Enable Input  
Output Enable Input  
Power Supply  
512Kx8  
MEMORY ARRAY  
A0-A18  
DECODER  
Ground  
NC  
No Connection  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
WE#  
OE#  
CONTROL  
CIRCUIT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
PIN CONFIGURATION  
A18  
A16  
A14  
A12  
A7  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VCC  
A15  
A17  
WE#  
A13  
A8  
3
4
5
A6  
6
A5  
7
A9  
A4  
8
A11  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A3  
9
A2  
10  
11  
12  
13  
14  
15  
16  
A1  
A0  
DQ0  
DQ1  
DQ2  
VSS  
TSOP-II  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 6.5  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
H
OE#  
X
WE#  
X
SUPPLY CURRENT  
ISB1  
MODE  
I/O OPERATION  
High-Z  
Standby  
Output Disable  
Read  
L
H
H
High-Z  
ICC,ICC1  
L
L
H
DOUT  
ICC,ICC1  
Write  
L
X
L
DIN  
ICC,ICC1  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
0.7*Vcc  
- 0.2  
- 1  
TYP. *3 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
3.0  
5.5  
VCC+0.3  
0.6  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*1  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
2.4  
-
-
-
-
V
V
VOL  
IOL = 2mA  
0.4  
Cycle time = Min.  
30  
60  
ICC  
CE# = 0.2V, II/O = 0mA  
other pins at 0.2V or VCC - 0.2V  
-
mA  
Average Operating  
Power supply Current  
Cycle time = 1 s  
µ
ICC1  
-
-
4
4
10  
mA  
CE# = 0.2V, II/O = 0mA  
other pins at 0.2V or VCC - 0.2V  
Standby Power  
Supply Current  
≦
CE# ≧VCC - 0.2V or CE2 0.2V  
Others at 0.2V or VCC - 0.2V  
ISB1  
50 *4  
A
µ
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
2. Over/Undershoot specifications are characterized, not 100% tested.  
3. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25  
4. 25 A for special request  
µ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
UNIT  
SYM.  
LY62W5128-55  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
tRC  
tAA  
55  
-
-
-
10  
5
-
-
10  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
55  
55  
30  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
*
*
-
*
*
20  
20  
-
(2) WRITE CYCLE  
PARAMETER  
UNIT  
SYM.  
LY62W5128-55  
MIN.  
55  
50  
50  
0
45  
0
25  
0
MAX.  
Write Cycle Time  
tWC  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
tDH  
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
tOW  
*
5
-
tWHZ  
*
20  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tAS  
tWP  
tWR  
WE#  
Dout  
Din  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data Retention  
SYMBOL TEST CONDITION  
VDR CE# ≧ VCC - 0.2V  
VCC = 1.5V  
MIN.  
1.5  
TYP.  
-
MAX.  
5.5  
UNIT  
V
Data Retention Current  
IDR  
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V  
Other pins at 0.2V or VCC-0.2V  
-
2
30  
A
µ
Chip Disable to Data  
Retention Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
Recovery Time  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
PACKAGE OUTLINE DIMENSION  
Ⅱ
32-pin 400mil TSOP-  
Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
ORDERING INFORMATION  
LY62W5128 U V - WW XX Y Z  
Z : Packing Type  
Blank : Tube or Tray  
T : Tape Reel  
Y : Temperature Range  
Blank : (Commercial) 0°C ~ 70°C  
E : (Extended) -20°C ~ +80°C  
I : (Industrial) -40°C ~ +85°C  
XX : Power Type  
LL : Ultra Low Power  
WW : Access Time(Speed)  
V : Lead Information  
L : Green Package  
U : Package Type  
W : 32-pin 400 mil TSOP-II  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY62W5128  
512K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.a  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
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