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82567 GbE Physical Layer Transceiver (PHY)

Datasheet

Product Features

 Reduced power consumption during normal

 Extended configuration load sequence

operation and power down modes

 Automatic resolution of FDX/HDX mismatch in

 IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications

(802.3, 802.3u, and 802.3ab) conformance

10/100 forced configurations

 Dual interconnect between MAC and PHY:

— LCI for 10/100 Mb/s operation control traffic

— GLCI for 1000 Mb/s operation

 Three LED outputs

 Multiple voltage regulation modes:

— External voltage regulation

 Supports up to 9 kB jumbo frames (full

duplex)

 Supports carrier extension (half duplex)

 Auto-negotiation with support for next page

 Smart speed operation, for automatic speed

— Fully integrated linear regulator (nominal

1.05 V, programmable)

— Discrete linear voltage regulator (nominal

1.8 V-1.9 V)

reduction on faulty cable plants

 Automatic MDI crossover capable

 PMA loopback capable (No echo cancel)

 Advanced power management:

— Low power link up

— Auto Connect Battery Saver - link

disconnect

 Advanced cable diagnostics:

— TDR

 Supported ICH Integrated MAC Features:

— Linksec (ICH10 only)

— Manageability: vPro Compatible

— Performance:

•RSS Support

•Checksum offload

— Channel frequency response

Order Number: 321792-001

Revision 2.4

April 2009

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel

or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS.

Please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any Intel® pre-release product, including any

evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you

indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event

that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different

processor families. See http://www.intel.com/products/processor_number for details.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

The 82567 GbE Physical Layer Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

®

Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a HT Technology enabled

chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/

products/ht/Hyperthreading_more.htm for additional information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

ii

Datasheet—82567

Contents

1.0 Introduction..............................................................................................................5

1.1

1.2

1.3

Scope................................................................................................................6

Reference Documents..........................................................................................6

Product Codes.....................................................................................................6

2.0 Signal Descriptions....................................................................................................7

2.1

2.2

2.3

2.4

2.5

Signal Type Definitions.........................................................................................7

GLCI Interface Pins..............................................................................................7

LCI Interface Pins................................................................................................8

Miscellaneous Pins...............................................................................................8

PHY Pins ............................................................................................................9

2.5.1 LED Pins .................................................................................................9

2.5.2 Analog Pins .............................................................................................9

2.5.3 Testability Pins.........................................................................................9

Power Supply Pins............................................................................................. 10

2.6

3.0 Features.................................................................................................................. 11

3.1

3.2

Feature Matrix and Product Information................................................................ 11

Power Saving Features....................................................................................... 12

3.2.1 Intel^®Auto Connect Battery Saver (ACBS) ................................................ 12

3.2.2 Link Speed Battery Saver ........................................................................ 12

3.2.3 System Idle Power Saver (SIPS) .............................................................. 13

3.2.4 Low Power Link Up (LPLU)....................................................................... 13

3.2.5 LAN Disable........................................................................................... 14

4.0 Voltage, Temperature, and Timing Specifications .................................................... 16

4.1

4.2

4.3

4.4

4.5

Recommended Operating Conditions.................................................................... 16

DC and AC Characteristics .................................................................................. 16

LED Electrical Specification ................................................................................. 16

Crystal Specifications......................................................................................... 17

Oscillator Specifications...................................................................................... 19

4.5.1 Oscillator High Voltage Configuration ........................................................ 19

Power Consumption........................................................................................... 20

Power Delivery.................................................................................................. 23

4.7.1 The 1.8 V-1.9 V Rail ............................................................................... 23

4.7.2 The 1.05 V Rail ...................................................................................... 23

4.7.3 Voltage Regulator Schematics.................................................................. 23

4.7.4 Voltage Regulator Power Supply Specifications........................................... 24

4.7.5 PNP Specifications .................................................................................. 25

4.7.6 Power Sequencing.................................................................................. 25

Timing Parameters ............................................................................................ 26

4.8.1 Timing Requirements.............................................................................. 26

4.8.2 Timing Guarantees ................................................................................. 26

4.6

4.7

4.8

5.0 Package and Pinout Information ............................................................................. 27

5.1

5.2

5.3

5.4

Package Information.......................................................................................... 27

Thermal........................................................................................................... 27

Internal Pull-Up Resistors................................................................................... 28

Visual Pin Assignments....................................................................................... 29

iii

82567—Datasheet

Revision History

Date

Revision Description

Oct 2006

0.1

Initial release (Intel secret)

January 2007

0.25

Corrected pin numbers and made minor text corrections (Intel Confidential)

Corrected GLAN TX pin numbers; added RSET & DIS_REG1_0 to the signal descriptions; corrected

LAN_DISABLE# (active high) to LAN_DISABLE_N (active low); in the Visual Pin Assignment

Diagram, pin 37, “LAN Enable” was corrected to “LAN_Disable_N”; removed VHV references.

February 2007

0.26

April 2007

May 2007

0.50

0.51

Minor text updates.

Updated power consumption target values.

Added Low-Power feature information, Recommended Operating Conditions, DC and AC

Characteristics, Preliminary LED/TEST/JTAG I/F DC Specifications, Crystal Specification, Voltage

RegulatorPower Supply Specification, PnP Transistor Specification, and Power Sequencing

information.

August 2007

0.75

0.76

1.5

September

2007

Changed IEEE 802.3ab designation to conformance

Updated features list; updated Reference Documents; added SKU information; Updated power rail

information (1.8 V-1.9 V, 1.05 V); clarified oscillator placement information; updated power target

information; corrected Slope and Operation Range characteristics for 1.8-1.9 V rail; added pointer

to reference schematics for regulator information.

November 2007

December 2007

1.51

1.6

Deleted “programmable” from 1.8 V-1.9 V power rail listing in the Features list.

Corrected 1.05 V power rail tolerance to +7% / -5% (1.0 V min, 1.12 V max)

Added XOR test file information; updated SKU and Features table; added information regarding

using LAN_PHY_PWR_CTRL ; updated Recommended Operating Conditions; updated DC and AC

characteristics; updated crystal/oscillator specifications; updated the measured power

consumption values; updated reference schematic link information; updated the 1.8 V-1.9 V rail

February 2008

1.7

operational range value; updated the 1.05 V rail operational range value; corrected P Min value

tot

in PNP specification;

Updated Reference Documents list; updated Testability Pins table; updated SKU table; updated

Power Consumption tables 7-10; updated power delivery drawing; added Ambient Operating

Temperature table.

March 2008

2.0

March 2008

April 2008

2.1

2.2

Updated SKU table; Combined Tables 5 and 6 to create new Table 5.

Updated Table 2.4 (added pull-up type designation to LAN_DISABLE_N); updated Table 12 (added

LAN_DISABLE_N information)

Updated WoL information; added System Idle Power Saver information; updated crystal

tolerances; updated LED pin table; updated pinout illustration; updated package tolerance values.

July 2008

April 2009

2.3

2.4

Updated SKU table; added SPI FLASH Programming Guide and 82567 Specification Update to

Reference Documents; added note regarding ACBS operation; added WoL power information;

added Solution Power information to Power Consumption table; clarified crystal Drive Level

specification.

Note: The revision numbering system changed with the first November 2007 release. At that time, the collateral for this device

began synchronizing with platform collateral revision numbering. There were no releases between versions 0.76 and 1.5.

iv

Datasheet—82567

1.0

Introduction

The 82567 is a single port GbE Physical Layer Transceiver (PHY) that connects to its

Media Access Controller (MAC) through a dedicated interconnect. The 82567 is based

on Intel's GbE PHY technology, and supports operation at data rates of 10/100/1000

Mb/s. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for

10BASE-T, 100BASE-TX, and 1000BASE-T applications (802.3, 802.3u, and 802.3ab).

The 82567 operates with the ICH9/9M/10 chipset that incorporates and integrates the

MAC, which is referred to as the ICH9/9M/10 LAN.

The 82567 is packaged in a small footprint QFN package. The package size is 8 mm x 8

mm with a pin-to-pin spacing of 0.5 mm, making it attractive for small form-factor

platforms.

The 82567 interfaces with its MAC through two interfaces: Gigabit LAN Connect

Interface (GLCI) and LAN Connect Interface (LCI). The GLCI is a high-speed proprietary

serial interface. The LCI is a low-speed proprietary parallel bus. The 82567 operates

using both interfaces; the GLCI for 1000 Mb/s traffic and LCI for all other traffic types.

Figure 1 identifies the major components of the 82567 architecture.

LCI

GLCI

LCI

GLCI

PLL

Crystal

Multiplexer

LEDs

Testability

MDIO

Status & Control

Power

Supply

Power

PHY

82567

MDI

Figure 1.

82567 Block Diagram

5

82567—Datasheet

1.1

1.2

Scope

This document contains datasheet specifications for the 82567, including signal

descriptions, DC and AC parameters, packaging data, and pinout information.

Reference Documents

This document assumes that the designer is acquainted with high-speed design and

board layout techniques. The following documents provide application information:

• IEEE Standard 802.3, 2002 Edition. Incorporates various IEEE Standards previously

published separately. Institute of Electrical and Electronic Engineers (IEEE).

• I/O Control Hub 9 NVM Map and Programming Information. Intel Corporation.

• I/O Control Hub 9M NVM Map and Programming Information. Intel Corporation.

• I/O Control Hub 10 NVM Map and Programming Information. Intel Corporation.

• ICH9 External Design Specification (EDS), Intel Corporation.

• ICH10 External Design Specification (EDS), Intel Corporation.

• I/O Controller Hub 8/9/10 and 82566/82567/82562V Software Developer’s Manual.

Intel Corporation.

• Information Technology - Telecommunication & Information Exchange Between

Systems - LAN/MAN - Specific Requirements - Part 3: Carrier Sense Multiple Access

with Collision Detection (CSMA/CD) Access Method and Physical Layer.

• Intel^®ICH7, ICH8, ICH9 and ICH10 – SPI Family Flash Programming Guide

Application Note. Intel Corporation. Contact your Intel representative to obtain this

document.

• Intel^®82567 Specification Update, Intel Corporation.

1.3

Product Codes

Table 1 lists the product ordering codes for the 82567.

Product Ordering Codes¹

Table 1.

Note:

For more information regarding the differences between the versions, please contact

your Intel field representative.

Part Number

Product Name

Description

Intel® 82567 Gigabit Platform Gigabit LAN for high-end Corporate and

LAN Connect Device Workstation designs

XX82567LM

Intel® 82567 Gigabit Platform Gigabit LAN for mainstream Corporate and

XX82567LF

XX82567V

LAN Connect Device

high-end desktop designs

Intel® 82567 Gigabit Platform

LAN Connect Device

Gigabit LAN for consumer designs

1. For more information regarding the differences, please contact your Intel field representative.

6

Datasheet—82567

2.0

Signal Descriptions

2.1

Signal Type Definitions

The signals are defined as follows in the table below:

Type

Description

In (I)

Out (O)

T/s

Standard input-only signal.

Totem pole output is a standard active driver.

Tri-state is a bi-directional, tri-state input/output pin.

Sustained tri-state is an active low tri-state signal owned and driven by one

and only one agent at a time. The agent that drives an s/t/s pin low must

drive it high for at least one clock before letting it float. A new agent cannot

start driving an s/t/s signal any sooner than one clock after the previous

owner tri-states it.

S/st/s

O/d

A-in

A-out

B

Open drain enables multiple devices to share as a wire-OR.

Analog input signal.

Analog output signal.

Input bias.

P

Power

PU

Pull-up.

PD

Pull-down.

2.2

GLCI Interface Pins

Signal Name

GLAN_RXP

55

Type

A-in

Description

GLCI Serial Data Input

GLAN_RXN

56

This is the differential input for GLCI (MAC to PHY).

GLAN_TXN

GLAN_TXP

53

52

GLCI Serial Data Output

This is the differential output for GLCI (PHY to MAC).

A-out

Crystal Oscillator

An external 25 MHz crystal can be connected to these pins to

generate a 25 MHz reference clock. A 25 MHz reference clock

can also be generated from an external 1.4 V oscillator

connected to the XTAL1 input pin.

XTAL2

XTAL1

9

10

A-out

A-in

7

82567—Datasheet

2.3

LCI Interface Pins

Signal Name

Type

Description

LCI/GLCI Clock

The clock is driven by the 82567 according to the operation

mode:

In 1000 Mb/s mode, JKCLK frequency is 62.5 MHz.

In 100 Mb/s mode, JKCLK frequency is 50 MHz.

In 10 Mb/s mode and no link, JKCLK frequency is 5 MHz.

In power down mode, JKCLK frequency is 0 MHz.

JKCLK

45

O

Reset/SYNC

This pin is driven by the MAC and has two functions:

Reset. When this pin is asserted beyond one LCI clock, the

82567 refers to this signal as a reset signal. However, to ensure

that the 82567 resets, the reset should remain active for at least

1ms. This functionality is also used to bring the 82567 out of a

power-down state.

JRSTSYNC

50

I

SYNC. When this pin is activated synchronously for one LCI clock

only, it is used for synchronization between the MAC and the

82567 on LCI word boundaries.

LCI Transmit Data

JTXD2

JTXD1

JTXD0

44

43

42

These pins are used for receiving real time control and

management data transmitted by the ICH9 LAN. These pins are

also used to move out of band control from the MAC to the

82567. The pins should be fully synchronous to JKCLK.

I

LCI Receive Data

JRXD2

JRXD1

JRXD0

49

48

47

These pins are used for transmitting real time control and

management data received by the ICH9 LAN. These pins are also

used to move out of band control from the 82567 to the MAC.

O

2.4

Miscellaneous Pins

Signal Name

Type

Description

IEEE_TEST_P

IEEE_TEST_N

12

13

A-out

Positive side of the high speed differential debug port for the 82567.

When this pin is set, the 82567 consumes minimum power and is

disabled.

LAN_DISABLE_N 37

I/PU

RSET

15

51

This pin should be connected through 4.99 kohm, +-1%, to ground.

Do not connect.

RESERVED_NC

8

Datasheet—82567

2.5

PHY Pins

2.5.1

LED Pins

Signal Name

LED0

Type

Description

LED0

4

2

1

O

This signal is used for the programmable LED. It is programmed

®

through the Intel ICH9/ICH10 NVM word 18h.

LED1

LED2

O

This signal is used for the programmable LED. It is programmed

®

through the Intel ICH9/ICH10 NVM word 17h.

LED2

This signal is used for the programmable LED. It is programmed

®

through the Intel ICH9/ICH10 NVM word 18h.

Note: Reference the following Application Notes for details regarding the programming of the LEDs and the

various modes.

•

I/O Control Hub 9 NVM Map and Programming Information Application Notes

I/O Control Hub 9M NVM Map and Programming Information Application Notes

I/O Control Hub 10 NVM Map and Programming Information Application Notes

2.5.2

Analog Pins

Signal Name

Pins

Type

Description

Media Dependent Interface [0]

In MDI configuration, MDI_PLUS[0]+/- is used for the transmit pair

and in MDI-X configuration MDI_MINUS[0]+/- is used for the

receive pair.

MDI_PLUS[0]

MDI_MINUS[0]

27

26

A

Media Dependent Interface [1]

MDI_PLUS[1]

MDI_MINUS[1]

23

22

In MDI configuration, MDI_PLUS[1]+/- is used for the receive pair

and in MDI-X configuration MDI_MINUS[1]+/- is used for the

transmit pair.

A

MDI_PLUS[2]

MDI_MINUS[2]

MDI_PLUS[3]

MDI_MINUS[3]

21

20

17

16

Media Dependent Interface [2:3]

For 1000BASE-T MDI configuration, MDI_PLUS[2:3]+/- is used for

the receive pair and in MDI-X configuration MDI_MINUS[2:3]+/- is

used for the transmit pair.

2.5.3

Testability Pins

Signal Name

Type

Description

JTAG_TCK

JTAG_TDI

JTAG_TDO

40

7

I

JTAG Clock Input

JTAG TDI Input

JTAG TDO Output

I/PU

T/s

6

9

82567—Datasheet

JTAG_TRST

JTAG_TMS

35

39

I

JTAG Reset

I/PU

JTAG TMS Input

Test Mode Enable

TEST_EN

36

T/s

This signal enables test mode capabilities. It should be strapped

to GND for normal operation.

Note:

The 82567 uses the JTAG interface to support XOR files for manufacturing test. BSDL is

not supported.

2.6

Power Supply Pins

Signal Name

Type

Description

3

28

46

3.3 VDC Supply

This is connected to the 82567.

VCC3_3

P

5

8

33

38

1.05 V DC Supply

This is connected to the 82567.

VCC1_05

11

14

18

19

24

25

30

41

32

54

1.8 V-1.9 V DC Supply

This is connected to the 82567. 82567 supports both 1.8 V and

1.9 V for this DC supply.

VCC1_8

P

1.05 V Control

CTRL10

CTRL18

31

29

Out

This is the voltage control signal for the external PNP transistor

that generates the 1.05 V supply.

1.8 V-1.9 V Control

This is the voltage control signal for the external PNP transistor.

The default voltage generated from the external PNP is 1.9 V.

When set to 3.3 V, configured to use external regulator for 1.05

V supply. When set to 0, the internal regulator will be used for

1.05 V supply. A 1 kOhm pull up or 1 kOhm pull down resistor is

required, depending on the desired configuration.

DIS_REG1_0

34

A

10

Datasheet—82567

3.0

Features

3.1

Feature Matrix and Product Information

The following matrix shows the features available with the 82567:

Extended

Power

Performance

Advanced Features***

82567 Sku Platform/Features Information

Platform

Code Name

Device ID

Product Name

Embedded

Intel® 82567V-3 Gigabit Network

Connection

ICH8M + 82567V

1501

X

High End

Desktop/

Workstation

Intel® 82567LM-4 Gigabit Network

Connection

ICH9/9R + 82567LM

10E5

X

Intel® 82567LM Gigabit Network

Connection

ICH9m+82567LM

10F5

10BF

10CB

10CC

10CD

10CE

10DE

10DF

X

Mobile

Intel® 82567LF Gigabit Network

Connection

ICH9m+82567LF

ICH9m+82567V

Intel® 82567V Gigabit Network Connection

Intel® 82567LM-2 Gigabit Network

Connection

Intel® 82567LF-2 Gigabit Network

Connection

Intel® 82567V-2 Gigabit Network

Connection

Intel® 82567LM-3 Gigabit Network

Connection

ICH10/10R+82567LM

ICH10/10R+82567LF

ICH10/10R+82567V

ICH10D/10DO+82567LM

ICH10D/10DO+82567LF

X

Desktop

X

Intel® 82567LF-3 Gigabit Network

Connection

* Note: Teaming is supported on Corporate SKU's with no-AMT

** Basic manageability includes ASF & DASH support. For firmware and hardware requirements, please refer to Intel® chipset documentation.

*** For Platform features, other Intel® component skus may be required. Please refer to the relevant Intel® component (chipset/CPU) documentation for sku requirements.

Production information is in the 82567 Specification Update available from Intel on the

Intel Business Link. Contact your Intel representative for more information.

11

82567—Datasheet

3.2

Power Saving Features

This section provides information about the low power configurations for the 82567.

3.2.1

Intel^®Auto Connect Battery Saver (ACBS)

Intel Auto Connect Battery Saver for the 82567 is a hardware-only feature that

automatically reduces the PHY to a lower power state when the power cable is

disconnected. When the power cable is reconnected, it will renegotiate the line speed

following IEEE specs for autonegotiation. By default, autonegotiation starts at 1GHz,

then 100 Mb full duplex/half duplex, then 10 Mb full duplex/half duplex.

Note:

Intel Auto Connect Battery Saver for the 82567 is only supported if autonegotiation is

enabled. If link speed is forced and the network cable is disconnected, the 82567 will

not enter ACBS, resulting in higher power consumption than specified in section 4.6.

82567 ACBS works in both S0 and Sx states. Unlike the 82566 External ACBS

implementation, 82567 ACBS requires no BIOS, software, or external on-board

hardware, limiting BOM cost and making implementation easier. When the 82567 PHY

is in ACBS mode, the LAN drivers stay loaded and the PHY consumes 37 mW (Solution

power is 63 mW). The crystal and LCI/GLCI interface clock still run, but all unneeded

internal clocks are gated. Since 82567 ACBS has no driver control, the feature is always

enabled, allowing power savings by default. The table below compares 82566 External

ACBS implementation and 82567 ACBS implementation:

82566 ACBS

82567 ACBS

Needs on board hardware

(energy detect circuit, power

FET Switch) (BOM Cost

~$0.2)

HW

No external BOM ($0)

No Driver control. Feature

always enabled. Enabling/

Disabling ACBS is not possible

from the driver.

Driver controls entry into

ACBS. Enabling/Disabling

ACBS possible from driver.

Driver

Implementation

(HW/SW/FW)

Minor changes needed for

LAN_PHY_PWR_CTRL (ICH

output) configuration.

BIOS

FW

No BIOS changes needed

NVM Soft Straps and GbE

NVM needs to be set up.

NVM does not need to be set

up.

Supported in both AC and DC

modes.

AC/DC modes

Sx support

Supported only in DC mode

Cannot enter ACBS mode in

Sx states.

Can enter ACBS mode in both

S0 and Sx states

3.3/1.8/1.05 V are all turned

off in IVRd/IVRi

3.3/1.8-1.9/1.05 V rails are all

left on

LAN Power Rails

configurations

PHY Power

Consumption

37 mW PHY power (63 mW

solution power)

~7mW

3.2.2

Link Speed Battery Saver

Link Speed Battery Saver is a power saving feature that negotiates to the lowest speed

possible when a Mobile system operates in DC mode to save power. When in AC mode,

where performance is more important than power, it negotiates to the highest speed

12

Datasheet—82567

possible. The Windows NDIS drivers (Windows XP and later), monitor the AC-to-DC

transition on the system to make the PHY negotiate to the lowest connection speed

supported by the link partner (usually 10 Mb) when the user unplugs the power cable

(switches from AC to DC power). When the AC cable is plugged in, the speed will

negotiate back to the fastest LAN speed. This feature can be enabled/disabled directly

from DMiX or through the Advanced Settings of the Window's driver.

When transferring packets at 1000/100 Mbps speed, if there is an AC-to-DC transition,

the speed will renegotiate to the lower speed. Any packet that was in process will be

retransmitted by the protocol layer. If the link partner is hard-set to only advertise a

certain speed, then the driver will negotiate to the advertised speed. Since the feature

is driver based, it is available in S0 state only.

Link Speed Battery Saver handles duplex mismatches/errors on link seamlessly by re-

initiating auto negotiation while changing speed. Link Speed Battery Saver also

supports Spanning Tree Protocol.

Note:

The packets would get re-transmitted for any protocol other than TCP as well.

3.2.3

System Idle Power Saver (SIPS)

System Idle Power Saver (SIPS) is a software-based power saving feature that is

enabled only with Microsoft* Windows* Vista*. This feature is only supported in the S0

state and can be enabled/disabled in the Advanced Tab of the Windows driver or

through DMiX. The power savings from this feature is dependent on the link speed of

the device. Please refer to Section 4.6 Tables 6-9 for the power dissipated in each link

state.

SIPS is designed to save power in mobile systems by negotiating to the lowest possible

link speed when both the network is idle and the monitor is turned off due to inactivity.

The SIPS feature is activated based on both of the following conditions.

• The Windows* Vista* NDIS driver receives notification from the Operating System

(OS) when the monitor is turned “OFF” due to non-activity.

• The LAN driver monitors the current network activity and determines that the

network is idle.

Then, with both the monitor “OFF” and the network idle, the LAN negotiates to the

lowest possible link speed supported by both the PHY and the link partner (typically 10

Mb). If the link partner is hard-set to only advertise a certain speed, then the LAN will

negotiate to the advertised speed. This link speed will be maintained until the LAN

driver receives notification from the OS that the monitor is turned “ON,” thus exiting

SIPS and re-negotiating to the highest possible link speed supported by both the PHY

and the link partner. If SIPS is exited when transferring packets, any packet that was

being transferred will be re-transmitted by the protocol layer after re-negotiation to the

higher link speed.

3.2.4

Low Power Link Up (LPLU)

Low Power Link Up is a firmware/hardware based feature that allows the designer to

make the PHY negotiate to the lowest connection speed first and then to the next

higher speed and so on. This setting allows users to save power when power is more

important than performance.

When speed negotiation starts, the PHY tries to negotiate for a 10 Mb/s link,

independent of speed advertisement. If link establishment fails, the PHY tries to

negotiate with different speeds. It enables all speeds up to the lowest speed supported

by the partner. For example, if the 82567 advertises 10 Mb/s only and the link partner

supports 1000/100 Mbps only , a 100Mbps link is established.

13

82567—Datasheet

LPLU is controlled through the LPLU bit in the PHY Power Management register. The

MAC sets and clears the bit according to hardware/software settings. The 82567 auto-

negotiates with the updated LPLU setting on the following auto-negotiation operation.

The 82567 does not automatically auto-negotiate after a change in the LPLU value.

LPLU is not dependent on whether the system is in AC or DC mode . In S0 state, Link

Speed Battery Saver overrides the LPLU funtionality.

LPLU is enabled for Non-D0a states by GbE NVM image word 17h (bit 10)

• 0b = Low Power Link Up is disabled.

• 1b = Low Power Link Up is enabled in all non-D0a states.

LPLU power consumption depends on what speed it negotiates at. This datasheet

includes all of the power numbers for the 82567 in the various speeds; see section 4.6,

Tables 1-4.

3.2.5

LAN Disable

82567 has a LAN_DISABLE_N input pin that can be used by the BIOS to disable the

PHY. The addition of this feature simplifies the PHY disable feature from the BIOS

relative to the LAN Disable sequence used in 82566.

LAN_DISABLE_N is an active low input and when asserted, it loses all functionality

other than the ability to power up again. Asserting LAN_DISABLE_N causes:

• GLCI enters electrical idle

• JKCLK is stopped to the MAC

• 25MHz clock remains active

• 82567 tri-states its output buffers

• WOL is not supported

On de-assertion:

• PHY sends JKCLK to MAC; MAC asserts JRSTSYNC

• PHY goes through usual initialization process.

Important Note:

Be sure to check for the latest LAN Disable and LAN_PHY_PWR_CTRL design guidelines.

The information in the Specification Updates listed below supercedes the general LAN

disable recommendations below.

Depending on which I/O Control Hub you are connecting, the information can be found

in the errata section of the following documents:

• I/O Controller Hub 9 (ICH9) Family Specification Update

• I/O Controller Hub 10 (ICH10) Family Specification Update

3.2.5.1

General LAN Disable Recommendations

LAN_DISABLE_N needs to be connected to the GPIO12/LAN_PHY_PWR_CTRL output of

ICH9, ICH9M, or ICH10. The GPIO12 needs to configured using ICH soft straps as

LAN_PHY_PWR_CTRL (bit [20] of STRP0 register - LAN_PHY_PWR_CTRL/GPIO12

Select (LAN_PHY_PWR_GPIO12_SEL) set to “1.” This can be done with the Intel FIT

tool by setting LAN_PHY_PWR_CTRL in ICH STRP0 to native mode (“1”). Please refer

to ICH9 EDS Section 22.2.5.1 for more details.

14

Datasheet—82567

In addition, LAN_PHY_PWR_CTRL can also be used to turn the 3.3 V power off to the

82567 when the PHY is disabled. This will also turn the PHY off when in Sx state and

WOL is disabled from the OS (through driver settings) for systems that have ME

disabled. This capability is called PHY Power Down and can be enabled/disabled through

GbE NVM Word 0x13.9.

The figure below shows the power delivery for 82567 and ICH LAN along with the

recommended connection for LAN_PHY_PWR_CTRL to LAN_DISABLE_N pin of 82567.

Note:

LAN_PHY_PWR_CTRL cannot be used to gate the 3.3V power rail to the ICH LAN.

Please refer to 82567 Specification Update for more information on

LAN_PHY_PWR_CTRL connection.

Figure 2.

Recommended Platform Power Delivery for 82567.

15

82567—Datasheet

4.0

Voltage, Temperature, and Timing Specifications

4.1

Recommended Operating Conditions

Table 2.

Recommended Operating Conditions

Symbol

Parameter

Min

Max

Unit

VCCP

Periphery Voltage Range

Core/Analog Voltage Range

Core Digital Voltage Range

3.0

3.6

2.015

1.12

V

VCC1p8

VCC1p0

1.71

0.98

4.2

DC and AC Characteristics

Table 3.

DC and AC Characteristics

Symbol

Parameter

Specificatiom

Typical

Units

Minimum

Maximum

High-threshold for

3.3 V supply

V1a

V2a

V1b

V2b

V1c

V2c

2.2

2.3

2.2

0.7

0.6

1.2

1.15

2.4

V

Low-threshold for 3.3

V supply

2.1

0.65

0.55

1.15

1.1

2.5

0.75

0.65

1.25

1.2

High-threshold for

1.05 V supply

Low-threshold for

1.05 V supply

High-threshold for

1.8-1.9 V supply

Low-threshold for

1.8-1.9 V supply

4.3

LED Electrical Specification

Table 4.

LED Electrical Specification

Symbol

Condition

Min

Nom

3.3

Max

Units

VDDO

-

3.0

3.6

1.0

V

-0.65

il

VDDO

+ 0.4

V

-

2.0

V

ih

Input Leakage

I @V =0.4 V

0 < V < VDDO

in

10

A

mA

pF

SR=11

-

12

ol

I

@V =VDDO - 0.4 V

oh

C

5

in

16

Datasheet—82567

4.4

Crystal Specifications

Following are the recommended crystal specifications for operation with the 82567.

Parameter Name

Symbol

Recommended Value

Max/Min Range

Conditions

Frequency

Vibration mode

Cut

f

25.000 MHz

Fundamental

AT

-

@25 °C

o

-

Operating/Calibration

Mode

Parallel

-

1

Frequency Tolerance

Temperature Tolerance

Operating Temperature

f/f @25°C

±30 ppm

Note

@25 °C

o

1

f/f

Note

-

o

T

-20 to +70 °C

Note ¹

-

opr

Non Operating

Temperature

T

-40 to +90 °C

-

opr

Equivalent Series

Resistance (ESR)

R

40 

50 

@25 MHz

s

1

Load Capacitance

Shunt Capacitance

C

18 pF (max 24 pF)

6 pF

Note

-

load

1

C

Note

o

Pullability from Nominal

Load Capacitance

f/C

15 ppm/pF max

-

load

Max Drive Level

Insulation Resistance

Aging

D

300 W

Note 4

-

L

IR

500 M min

@ 100 VDC

-

f/f

±5 ppm per year

o

Differential Board

Capacitance

2

C

2 pF

Note

D

3

Board Capacitance

External Capacitors

Board Resistance

C

4 pF

27 pF

0.1 

Note

-

s

1

C , C

Note

1

2

R

1 

s

1. When not using values within 1% of the recommended values, the following procedures must be used:

1. On the board with the crystal and the 82567, measure the clock at the output of the receive and transmit

lines.

2. Change C and C to meet with the 25 MHz requirement.

1

2

3. Ensure the demand on the 25 MHz clock has a deviation of less than 30 ppm (for example, 25 MHz + 750

Hz).

4. If the measured frequency is higher then 25.00075 MHz, replace capacitors C and C with larger

1

2

capacitors.

5. If the measured frequency is lower then 24.99925 MHz, replace capacitors C and C with smaller

1

2

capacitors.

2. Differential board capacitance is the capacitance between Ser_CLK_PLUS and Ser_CLK_MINUS.

3. Board capacitance is the differential capacitance between the input and output. This parasitic capacitance

must be less than or equal to the specification. This value can change up to 10%. The procedures listed in

footnote “1” must be followed to comply with the ppm specification.

4. Crystal must meet or exceed the specified drive level (D ). A crystal with a specified drive level of less than

L

300 W does not meet this requirement.

17

82567—Datasheet

To the 82567

XTAL1

XTAL2

Keep lines identical

Crystal

Keep lines identical

C1

C2

Figure 3.

Crystal Connectivity to the 82567

The current from the 82567 does not change regardless of generating the 1.05 V using

the on-die transistor or an external pass transistor. The total current demand remains

constant, but the power dissipated by the 82567 package changes. The 1.05 V power is

either on-die or at the external pass transistor.

18

Datasheet—82567

4.5

Oscillator Specifications

Table 5.

Oscillator Specifications and Timing Requirements

Symbol/

Parameter

Parameter Name

Frequency

Conditions

Min

Typ

25.0

Max

Unit

f

@25 °C]

MHz

V

Swing

V

3

3.3

3.6

P-P

Frequency Tolerance

Temperature Stability

Operating Temperature

f/f

-20 to +70

±30

ppm

o

0 C to 70 C

-20 to +70 °C

T

opr

±5 ppm

per year

Aging

f/f

ppm

pF

o

Coupling capacitor

Calibration mode

C

12

15

18

coupling

Parallel

Oscillator Load

Capacitance

18

pF

Shunt Capacitance

Series Resistance, Rs

Drive Level

6

pF



50

300

W

M

ns

Insulation Resistance

@ 100 VDC

500

13

T

XTAL_IN High Time

XTAL_IN Low Time

XTAL_IN Rise

20

H_XTAL_IN

L_XTAL_IN

R_XTAL_IN

F_XTAL_IN

13

10%-90%

5

XTAL_IN Fall

XTAL_IN Total

Jitter

1

T

200

ps

J_XTAL_IN

1 Broadband peak-peak=200pS, Broadband rms=3pS, 12 kHzto 20 MHz rms= 1ps

4.5.1

Oscillator High Voltage Configuration

This configuration involves capacitor C1, which forms a capacitor divider with Cstray of

about 20 pF. This attenuates the input clock amplitude and adjusts the clock oscillator

load capacitance.

19

82567—Datasheet

Vin = VDD * (C1/(C1 + Cstray))

Vin = 3.3 * (C1/(C1 + Cstray))

This enables load clock oscillators of 15 pF to be used. If the value of Cstray is unknown,

C1 should be adjusted by tuning the input clock amplitude to approximately 1.2-1.8

Vptp. If Cstray equals 20 pF, then C1 is 15 pF ±10%. A low capacitance, high impedance

probe (C < 1 pF, R > 500 K_) should be used for testing. Probing the parameters can

affect the measurement of the clock amplitude and cause errors in the adjustment. A

test should also be done after the probe has been removed for circuit operation. If jitter

performance is poor, a lower jitter clock oscillator can be implemented.

Note:

C_strayshown in the figure below is not an actual discrete capacitor, but a representation

of the board capacitance and is not to be placed in the actual design.

Measure the Vptp at the XTAL1 pin to ensure that it is never over 1.8 V. Overvoltage

could lead to a silicon reliability concern.

Keep C1 close to the XTAL1 pin of the 82567. This will help make the value of Cstray

less dependent on the PCB (Total Cstray is a combination of Cstray of PCB and Cstray of

silicon).

4.6

Power Consumption

The following table lists the measured values for the 82567’s power. The numbers apply

to the 82567 power dissipation with External Voltage Regulators (EVRs). Power is

reduced according to link speed and link activity.

20

Datasheet—82567

Table 6.

State

Power Consumption–82567 with external Voltage regulator, 1.9V (VCC1P8)

3.3 V

Current

[mA]

1.9 V

Current

[mA]

1.05 V

Current

[mA]

82567

Power

[mW]

Solution

Power

[mW]

Mode

1000Mbps Active, 90°c [Ta]

1000Mbps Idle, 90°c [Ta]

1000Mbps Active

1000Mbps Idle

22

25

4

256

254

72

115

110

112

106

18

6

680

675

673

667

238

221

141

37

1297

1280

1261

380

S0 - Max

100Mbps Active

100Mbps Idle

72

380

10Mbps Active

106

64

383

S0 - Typ

10Mbps Idle

4

6

244

Cable Disconnect (ACBS)

3

12

4

63

Cable Disconnect (82567V only,

no ACBS)

3

23

7

61

109

LAN Disable

3

4

3

6

64

6

3

6

3

24

141

24

40

244

40

10Mbps Idle with WOL

WOL disabled in driver

WOL disabled in BIOS

SX

6

24

40

WOL disabled in BIOS w/FET

switch‡

0

Note: The total solution power is the total amount of power from the 3.3V supply required for the 82567 to

operate. In its mathematical form:

solution power = (82567 current) * 3.3 V. The 3.3 V is assumed since this is the normal voltage rail provided to the

LAN solution.

Refer to Fig. 2 for details of the implementation of V3.3WOL gated by a FET switch controlled by an OR

of WOL_EN and SLP_M#

‡

21

82567—Datasheet

Table 7.

Power Consumption–82567 with internal Voltage regulator, 1.9V (VCC1P8)

3.3 V

Current

[mA]

1.9 V

Current

[mA]

82567

Power

[mW]

Solution

Power

[mW]

State

Mode

1000Mbps Active, 90°c [Ta]

1000Mbps Idle, 90°c [Ta]

1000Mbps Active

1000Mbps Idle

22

25

4

377

370

372

365

88

789

776

779

766

250

228

135

40

1317

1294

1300

1277

373

S0 - Max

100Mbps Active

100Mbps Idle

88

373

10Mbps Active

113

64

386

S0 - Typ

10Mbps Idle

4

224

Cable Disconnect (ACBS)

3

16

63

Cable Disconnect (82567V only,

no ACBS)

3

30

67

109

LAN Disable

3

4

3

9

64

9

27

135

27

40

224

40

10Mbps Idle with WOL

WOL disabled in driver

WOL disabled in BIOS

SX

9

27

40

WOL disabled in BIOS w/FET

switch‡

0

Note: The total solution power is the total amount of power from the 3.3V supply required for the 82567 to

operate. In its mathematical form:

solution power = (82567 current) * 3.3 V. The 3.3 V is assumed since this is the normal voltage rail provided to the

LAN solution.

Refer to Fig. 2 for details of the implementation of V3.3WOL gated by a FET switch controlled by an OR

of WOL_EN and SLP_M#

‡

22

Datasheet—82567

Table 8.

State

Power Consumption–82567 with external Voltage regulator; 1.8 V (VCC1P8)

3.3 V

Current

[mA]

1.8 V

Current

[mA]

1.05 V

Current

[mA]

82567

Power

[mW]

Solution

Power

[mW]

Mode

1000Mbps Active, 90°c [Ta]

1000Mbps Idle, 90°c [Ta]

1000Mbps Active

1000Mbps Idle

22

25

4

253

251

71

115

110

112

106

18

6

643

638

636

630

228

205

133

36

1287

1270

1250

376

S0 - Max

100Mbps Active

100Mbps Idle

71

376

10Mbps Active

103

63

373

S0 - Typ

10Mbps Idle

4

6

241

Cable Disconnect (ACBS)

3

12

4

63

Cable Disconnect (82567V only,

no ACBS)

3

23

7

59

109

LAN Disable

3

4

3

6

63

6

3

6

3

24

133

24

40

241

40

10Mbps Idle with WOL

WOL disabled in driver

WOL disabled in BIOS

SX

6

24

40

WOL disabled in BIOS w/FET

switch‡

0

Note: The total solution power is the total amount of power from the 3.3V supply required for the 82567 to

operate. In its mathematical form:

solution power = (82567 current) * 3.3 V. The 3.3 V is assumed since this is the normal voltage rail provided to the

LAN solution.

Refer to Fig. 2 for details of the implementation of V3.3WOL gated by a FET switch controlled by an OR

of WOL_EN and SLP_M#

‡

23

82567—Datasheet

Table 9.

Power Consumption–82567 with internal Voltage regulator, 1.8 V (VCC1P8)

3.3 V

Current

[mA]

1.8 V

Current

[mA]

82567

Power

[mW]

Solution

Power

[mW]

State

Mode

1000Mbps Active, 90 °C [Ta]

1000Mbps Idle, 90 °C [Ta]

1000Mbps Active

1000Mbps Idle

22

25

4

374

368

369

362

86

746

735

737

724

237

239

217

127

35

1307

1287

1290

1267

366

S0 - Max

100Mbps Active

100Mbps Idle

87

370

10Mbps Active

113

63

386

S0 - Typ

10Mbps Idle

4

221

Cable Disconnect (ACBS)

3

14

56

Cable Disconnect (82567V only,

no ACBS)

3

30

64

109

LAN Disable

3

4

3

9

63

9

26

127

26

40

221

40

10Mbps Idle with WOL

WOL disabled in driver

WOL disabled in BIOS

SX

9

26

40

WOL disabled in BIOS w/FET

switch‡

0

Note: The total solution power is the total amount of power from the 3.3V supply required for the 82567 to

operate. In its mathematical form:

solution power = (82567 current) * 3.3 V. The 3.3 V is assumed since this is the normal voltage rail provided to the

LAN solution.

Refer to Fig. 2 for details of the implementation of V3.3WOL gated by a FET switch controlled by an OR

of WOL_EN and SLP_M#

‡

4.7

Power Delivery

The 82567 operates from two or three external power rails:

• A 3.3 V power rail for internal power regulation and for periphery.

• A 1.8 V-1.9 V power rail for analog functions. (See the 82567 Specification Update

for more information.)

• An optional 1.05 V power rail. Onboard transistor saved/unused when the on-die

LVR is used.

4.7.1

The 1.8 V-1.9 V Rail

The power delivery system supports a load of 300 mA.

The 1.8 V-1.9 V rail is tunable and can be supplied in one of three ways:

• A discrete Switched Voltage Regulator (SVR) solution.

• An external power supply that is not dependent on support from 82567. For

example, the platform designer might choose to route a platform-available 1.8 V-

1.9 V supply to the 82567.

• A discrete LVR solution where the base current of PnP power transistor is driven by

the 82567, while the power transistor is placed externally. 1.9 V is the default

value.

24

Datasheet—82567

4.7.2

The 1.05 V Rail

The 1.05 V power delivery system supports a load of 300 mA.

The 1.05 V rail can be supplied in one of three ways:

• An external power supply that is not dependent on support from the 82567. For

example, the platform designer might choose to route a platform-available 1.05 V

supply to the 82567.

• A fully integrated on-die LVR solution.

• A discrete LVR solution, where the base current of PNP power transistor is driven by

the 82567, while the power transistor is placed externally.

• A discrete Switched Voltage Regulator (SVR) solution.

4.7.3

Voltage Regulator Schematics

Schematics for 82567 power delivery using integrated and discrete LVRs are included in

the reference schematics (titled 82567_Gigabit_Ethernet_PHY_Reference_Schematics)

4.7.4

Voltage Regulator Power Supply Specifications

3.3 V Rail

4.7.4.1

Title

Rise Time

Description

Time from 10% to 90% mark

Min

Max

100

Units

ms

1

3

Monotonicity

Slope

Voltage dip allowed in ramp

0

mV

V/s

Ramp rate at any given time between 10% and 90%

28800

Operational

Range

Voltage range for normal operating conditions

3.6

V

Ripple

Maximum voltage ripple @ BW = 50MHz

Maximum voltage allowed

70

4

mV

V

Overshoot

Capacitance

Minimum capacitance

25

uF

4.7.4.2

1.8 V-1.9 V Rail

Title

Description

Min

Max

Units

Rise Time

Monotonicity

Slope

Time from 10% to 90% mark

Voltage dip allowed in ramp

1

100

0

ms

mV

V/s

Ramp rate at any given time between 10% and 90%

Voltage range for normal operating condtions

1440

Operational

Range

1.71

2.015

V

Ripple

Maximum voltage ripple @ BW = 50MHz

Maximum voltage allowed

50

mV

V

Overshoot

2.7

Output

Capacitance

Capacitance range when using PNP circuit

20

40

uF

25

82567—Datasheet

Title

Description

Min

Max

Units

Input

Capacitance range when using PNP circuit

20

5

uF

Capacitance

Capacitance ESR

Ictrl

Equivalent series resistance of output capacitance

Maximum output current rating rating to CTRL18

100

10

m

mA

Note: Do not use tantalum capacitors.

4.7.4.3

1.05 Rail

Title

Description

Min

Max

Units

Rise Time

Monotonicity

Slope

Time from 10% to 90% mark

Voltage dip allowed in ramp

1

100

0

ms

mV

V/s

Ramp rate at any given time between 10% and 90%

Voltage range for normal operating conditions

800

Operational

Range

0.98

1.12

V

Ripple

Maximum voltage ripple @ BW = 50MHz

Maximum voltage allowed

30

mV

V

Overshoot

1.5

Output

Capacitance

Capacitance range when using PNP circuit

20

40

uF

Input

Capacitance

20

5

Capacitance ESR

Ictrl

Equivalent series resistance of output capacitance

Maximum output current rating rating to CTRL10

100

10

mW

mA

4.7.5

PNP Specifications

Title

Description

Min

Max

Units

VCBO

20

V

A

VCEO

20

1

IC(max)

IC(peak)

1.2

Minimum total dissipated power @ 25°C ambient

temperature

Ptot

1.5

W

hFE

hfe

Cc

DC current gain @ Vce=-10V, Ic=500mA

AC current gain @ Ic=50mA VCE=-10V, f=20MH

Collector capacitance @ VCB=-5V, f=1MHz

85

2.5

50

pF

fT

Transition frequency @ Ic=10mA, VCE=-5V, f=100MHz 40

BCP69

MHz

Recommended

Transistor

Note: Maximum current of 1.8 V-1.9 V is less then 270mA, Maximum current of 1.05 V is less then 139mA.

1.8 V-1.9 V and 1.05 V PnP used is BCP69 (see BCP69 spec).

26

Datasheet—82567

4.7.6

Power Sequencing

For proper and safe operation, the power supplies must follow the following rule:

VDDO (3.3 V) > AVDD (1.8 V or 1.9 V) > DVDD (1.05 V)

This means that VDDO must start ramping before AVDD and DVDD, but DVDD may

reach its nominal operating range before AVDD and VDDO.

Basically, the higher voltages must be greater than or equal to the lower voltages. This

is necessary to avoid low impedance paths through clamping diodes and to eliminate

back-powering.

The same requirements apply to the power-down sequence.

LAN_RST# must be low throughout the time that the power supplies are ramping. This

will guarantee that the MAC and PHY reset cleanly. While LAN_RST# is low, PHYRST#

will also be asserted to reset the PHY.

27

82567—Datasheet

4.8

Timing Parameters

Timing Requirements

4.8.1

The 82567 requires the following start-up and power state transitions.

Table 10.

Timing Requirements

Parameter

Description

Min

1 ms

Max

Notes

Minimum duration of

JRSTSYNC pulse

T

Per LCI specification

JRST_min

Completion of dock/undock

configuration following cable

connection

Tc2dud

Tr2init

0.5 sec

Completion of PHY

configuration following a reset

complete indication

0.5 sec

4.8.2

Timing Guarantees

The 82567 guarantees the following start-up and power state transition related timing

parameters.

Table 11.

Timing Guarantees

Parameter

Description

Min

Max

Notes

PHY configuration

should be delayed

until PHY completes

its reset

Reset de-assertion to PHY

reset complete

T

10 ms

PHY_Reset

XTAL frequency stable after

platform power ramp up

T

5 ms

1 s

3 s

XTAL

POR

Internal POR trigger after XTAL

stable

JKCLK output stable after

internal POR

JKCLK

Maximum time to transition to

valid TX specifications after

leaving an electrical idle

condition

Required by GLCI

2.0 specification

T

200 ns

TX_IDLE-TO-DIFF-DATA

RX_IDLE-TO-DIFF-DATA

Maximum time to be ready to

accept data after leaving an

electrical idle condition

Required by GLCI

2.0 specification

200 ns

1.3 s

Cable connect to start of auto

negotiation

Per 802.3

specification

T

1.2 s

c2an

28

Datasheet—82567

5.0

Package and Pinout Information

The physical characteristics of the 82567 are described in this section. The pin number

to signal mapping is indicated in Section 5.4.

5.1

Package Information

The package used for the 82567 is an 56-pin QFN package. The Epad size is option

number 4.

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Figure 4.

82567 Mechanical Drawing

5.2

Thermal

The thermal resistance from junction to case, JC, is 6.1 C/Watt. The thermal resistance

from junction to ambient, JA, is as follows:

Air Flow (m/s)

Maximum T

_ja(°C/Watt)

J

0

1

2

3

127.1

122.1

119.3

117.5

26.0

23.7

22.4

21.6

Note:

No heat sink required.

29

82567—Datasheet

Operating Ambient Temperature

Minimum

Maximum

0 °C

85 °C

5.3

Internal Pull-Up Resistors

Table 12 lists the internal pull-up resistors and their functionality in different device

states. Each internal pull-up resistor has a nominal value of 5 k, ranging from 2.7 k

to 8.6 k

Table 12.

Internal Pull-Up Resistors

Signal Name (Pin

Location)

1

Default State

Power-Down State

LED0 (4)

LED1 (2)

Not connected

Connected

LED2 (1)

Connected

JTAG_TCK (40)

JTAG_TDI (7)

Connected

JTAG_TDO (6)

Not connected

Connected

Not Connected

Connected

JTAG_TMS (39)

JTXD[2:0] (42, 43, 44)

JRXD[2:0] (47, 48, 49)

LAN_DISABLE_N (37)

Not Connected

Connected

Not Connected

Connected

1. This column describes the state of the internal pull-up resistors in device power-

down mode when the internal voltage regulators are shut down.

30

Datasheet—82567

5.4

Visual Pin Assignments

Pin 57-VSS_EPad

Pin 1

42

JTXD0

1

2

LED2

41 VCC1_8

LED1

40

JTAG_TCK

VCC3_3

3

39 JTAG_TMS

4

LED0

VCC1_05

38

VCC1_05

5

37 LAN_ENABLE

6

JTAG_TDO

JTAG_TDI

36

TEST_EN

7

82567

35 JTAG_TRST

8

VCC1_05

XTAL2

34

33

32

31

30

29

DIS_REG1_0

9

10

XTAL1

VCC1_05

VCC1_8

CTRL10

VCC1_8

CTRL18

VCC1_8 11

IEEE_TEST_P 12

13

14

IEEE_TEST_N

VCC1_8

Note:

VCC1_8 range is 1.71 V to 2.015 V

VCC1_05 range is 0.98 V to 1.12 V

82567 Pinout (Top View, Pins Down)

Figure 5.

31

82567—Datasheet

Table 13.

Pin Mapping

Pin Name

LED2

Pin Name

CTRL18

1

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

2

LED1

VCC1_8

3

VCC3_3

CTRL10

4

LED0

VCC1_8

5

VCC1_05

JTAG_TDO

JTAG_TDI

VCC1_05

XTAL2

VCC1_05

REG_DIS1_0

JTAG_TRST

TEST_EN

LAN_DISABLE_N

VCC1_05

JTAG_TMS

JTAG_TCK

VCC1_8

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

XTAL1

VCC1_8

IEEE_TEST_P

IEEE_TEST_N

VCC1_8

JTXD0

RSET

JTXD1

MDI_MINUS[3]

MDI_PLUS[3]

VCC1_8

JTXD2

JKCLK

VCC3_3

VCC1_8

JRXD0

MDI_MINUS[2]

MDI_PLUS[2]

MDI_MINUS[1]

MDI_PLUS[1]

VCC1_8

JRXD1

JRXD2

JRSTSYNC

RESERVED_NC

GLAN_TXP

GLAN_TXN

VCC1_8

MDI_MINUS[0]

MDI_PLUS[0]

VCC3_3

GLAN_RXP

GLAN_RXN

32

Datasheet—82567

33

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