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5M570ZF256C5N

型号：

5M570ZF256C5N

描述：

MAX V CPLD开发板[ MAX V CPLD Development Board ]

品牌：

ALTERA[ ALTERA CORPORATION ]

页数：

24 页

PDF大小：

1003 K

下载PDF手册
MAX V CPLD Development Board Reference Manual  
MAX V CPLD Development Board  
Reference Manual  
101 Innovation Drive  
San Jose, CA 95134  
www.altera.com  
MNL-01061-1.0  
Subscribe  
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.  
& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective  
holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance  
with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or  
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera  
customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or  
services.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Contents  
Chapter 1. Overview  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1  
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1  
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2  
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2  
Chapter 2. Board Components  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1  
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2  
Featured Device: MAX V CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3  
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4  
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5  
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5  
CPLD Configuration over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5  
CPLD Configuration using External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6  
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6  
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7  
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7  
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8  
GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8  
PC Speaker Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10  
DC Motor Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11  
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13  
User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13  
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13  
Off-Chip EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14  
2
I C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14  
SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15  
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16  
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16  
Additional Information  
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1  
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1  
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
iv  
Contents  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
1. Overview  
Introduction  
This document describes the hardware features of the MAX® V CPLD development  
board, including the detailed pin-out and component reference information required  
to create custom CPLD designs that interface with all components of the board.  
General Description  
The MAX V CPLD development board provides a hardware platform for developing  
and prototyping low-cost, low-power CPLD designs, as well as to demonstrate the  
features of the MAX V CPLD device.  
To facilitate the development of MAX V CPLD designs, the board provides connectors  
to interface to external functions or devices.  
f For more information on the MAX V CPLD device family, refer to the MAX V Device  
Handbook.  
Board Component Blocks  
The board features the following major component blocks:  
■
MAX V CPLD 5M570ZF256C5N in a 256-pin FineLine BGA (FBGA) package  
■
■
■
■
■
■
570 logic elements (LEs)  
440 equivalent macrocells  
8,192-bits user flash memory (UFM)  
4 global clocks  
159 user I/Os  
1.8-V core power  
■
■
MAX II EPM240M100C4N CPLD in the 100-pin Micro FBGA (MBGA) package  
On-Board configuration circuitry  
■
Embedded USB-BlasterTM for use with the Quartus® II Programmer  
On-Board connectors  
■
■
■
■
■
Type-B USB connector (as power source and communication port)  
Two general purpose I/O (GPIO) 2×20-pin 0.1-inch expansion headers  
One 4-pin PC speaker header  
Two 2×3-pin DC motor headers  
■
On-Board clocking circuitry  
10-MHz single-ended external oscillator  
■
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
1–2  
Chapter 1: Overview  
Development Board Block Diagram  
■
General user I/O  
LEDs and display  
■
■
■
■
Two CPLD user LEDs  
One USB status LED  
One power status LED  
■
Push-Button switches  
■
Two user-defined push-button switches  
One capacitor sense push-button switch  
■
■
Mechanical  
4.1” × 3.1” board  
■
Development Board Block Diagram  
Figure 1–1 shows the block diagram of the MAX V CPLD development board.  
Figure 1–1. MAX V CPLD Development Board Block Diagram  
Push-Button  
User LEDs  
GPIO  
Header 2  
Switches  
EPM240M100  
Embedded  
USB-Blaster  
USB  
2.0  
10 MHz Oscillator  
JTAG Chain  
Capacitor  
x1  
x8  
Sense  
Push-Button  
Switch  
SPI x4  
EEPROM  
EEPROM  
PC Speaker  
Header  
I2C x2  
EP5M570ZF256N  
x36  
GPIO  
Header 1  
x9  
x9  
DC Motor  
Header 2  
DC Motor  
Header 1  
Handling the Board  
When handling the board, it is important to observe the following static discharge  
precaution:  
c
Without proper anti-static handling, the board can be damaged. Therefore, use  
anti-static handling precautions when touching the board.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
2. Board Components  
Introduction  
This chapter introduces the major components on the MAX V CPLD development  
board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief  
description of all component features of the board.  
1
A complete set of schematics, a physical layout database, and GERBER files for the  
development board reside in the MAX V CPLD development kit documents directory.  
f For information about powering up the board and installing the demonstration  
software, refer to the MAX V CPLD Development Kit User Guide.  
This chapter consists of the following sections:  
■
■
■
■
■
■
■
■
■
“Board Overview”  
“Featured Device: MAX V CPLD” on page 2–3  
“Configuration, Status, and Setup Elements” on page 2–5  
“Clock Circuitry” on page 2–7  
“Connectors” on page 2–8  
“General User Input/Output” on page 2–13  
“Off-Chip EEPROM” on page 2–14  
“Power Supply” on page 2–16  
“Statement of China-RoHS Compliance” on page 2–16  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–2  
Chapter 2: Board Components  
Board Overview  
Board Overview  
This section provides an overview of the MAX V CPLD development board,  
including an annotated board image and component descriptions. Figure 2–1  
provides an overview of the development board features.  
Figure 2–1. Overview of the MAX V CPLD Development Board Features  
Footprint for  
I2C EEPROM  
(U6)  
10-MHz Single-Ended  
External Oscillator  
(J1)  
Motor Control  
Header 1  
(J5)  
Power LED  
(D1)  
USB Type-B  
Connector (J4)  
USB LED  
(D3)  
GPIO Headers  
(J6, J7)  
MAX II CPLD  
EPM240M100C4N  
(For embedded  
USB-Blaster) (U4)  
Power  
Regulator  
(U7)  
VAR_VCCIO  
Voltage Output  
Selection Jumper  
(U7)  
Footprint for  
SPI EEPROM  
(U8)  
User  
Push-Button  
Switches (S1, S2)  
Motor Control  
Header 2  
(J10)  
User  
LEDs  
(D7, D8)  
Speaker  
Header  
(J9)  
MAX V  
CPLD  
(U5)  
Capacitor  
Sense Button  
(CPB1)  
Table 2–1 describes the components and lists their corresponding board references.  
Table 2–1. MAX V CPLD Development Board Components (Part 1 of 2)  
Board Reference  
Type  
Description  
Featured Device  
U5  
CPLD  
MAX V 5M570ZF256C5N, 256-pin FBGA.  
Configuration, Status, and Setup Elements  
Connects the USB cable to the computer to enable embedded  
USB-Blaster JTAG. The connector also supplies power to the board  
through a USB cable when the cable is connected to a PC USB slot at  
the other end.  
J4  
USB Type-B connector  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–3  
Featured Device: MAX V CPLD  
Table 2–1. MAX V CPLD Development Board Components (Part 2 of 2)  
Board Reference  
Type  
Description  
A FTDI USB 2.0 PHY device to configure the CPLD over embedded  
USB-Blaster.  
U3  
USB 2.0 PHY  
CPLD  
U4  
MAX II CPLD EPM240M100.  
Footprint (at the bottom of the board) to mount a JTAG header. The  
header allows direct-access to devices in the JTAG connection.  
J13, J14  
JTAG header  
D1  
D3  
Power LED  
USB LED  
Illuminates when 5-V USB power is present.  
Illuminates to indicate USB-JTAG activity.  
Clock Circuitry  
J1  
X1  
Y1  
10-MHz oscillator  
6-MHz oscillator  
24-MHz oscillator  
10-MHz single-ended input clock for the MAX V CPLD.  
6-MHz input clock for the FTDI USB 2.0 PHY device.  
24-MHz input clock for the MAX II CPLD EPM240M100.  
Connectors  
J6, J7  
GPIO headers  
Two general-purpose 2x40-pin 0.1-inch expansion headers.  
A 4-pin PC speaker header which connects to the MAX V CPLD I/O  
bank 2.  
J9  
PC speaker header  
DC motor headers  
J5, J10  
Two motor headers which connects to the MAX V CPLD I/O bank 2.  
General User Input/Output  
D7, D8  
S1, S2  
CPB1  
User LEDs  
Two user LEDs. Illuminates when driven low.  
User push-button switches  
Capacitor sense button  
Two user push-button switches. Driven low when pressed.  
One capacitive touch-sense user-defined button.  
Off-Chip EEPROM  
U6  
U8  
I2C EEPROM  
SPI EEPROM  
Footprint to install an I2C serial EEPROM  
Footprint to install a SPI EEPROM.  
Featured Device: MAX V CPLD  
The MAX V CPLD development board features the MAX V CPLD 5M570ZF256C5N  
device (U5) in a 256-pin FBGA package.  
Table 2–2 describes the features of the MAX V CPLD 5M570ZF256C5N device.  
Table 2–2. MAX V CPLD 5M570ZF256C5N Device Features  
Equivalent LEs  
User Flash Memory (bits)  
User I/Os  
Global Clocks  
Package Type  
570  
8192  
159  
4
256-pin FBGA  
f For more information about MAX V CPLD device family, refer to the MAX V Device  
Handbook.  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–4  
Chapter 2: Board Components  
Featured Device: MAX V CPLD  
Table 2–3 lists the MAX V CPLD device component reference and manufacturing  
information.  
Table 2–3. MAX V CPLD Device Component Reference and Manufacturing Information  
Manufacturing  
Part Number  
Manufacturer  
Website  
Board Reference  
Description  
Manufacturer  
MAX V CPLD, 256-pin FBGA  
package, 570 LEs, lead-free.  
U5  
Altera Corporation  
5M570ZF256C5N  
www.altera.com  
I/O Resources  
The 5M570ZF256C5N device support two I/O banks and each of these banks support  
all the LVTTL, LVCMOS, LVDS, and RSDS standards.  
Figure 2–2 illustrates the bank organization for the 5M570ZF256C5N device in a  
256-pin FBGA package.  
Figure 2–2. 5M570ZF256C5N Device I/O Bank Diagram (Note 1)  
I/O Bank 1  
I/O Bank 2  
5M570ZF256C5N  
Note to Figure 2–2:  
(1) This figure is a top view of the silicon die and is a graphical representation only. Refer to the pin list and the Quartus II  
software for exact pin locations.  
Table 2–4 lists the MAX V CPLD device pin count and usage by function on the  
development board.  
Table 2–4. MAX V CPLD Device I/O Pin Count and Usage (Part 1 of 2)  
Function  
40-pin GPIO Header A  
40-pin GPIO Header B  
PC Speaker Header  
DC Motor Headers  
I/O Standard  
I/O Count  
Special Pins  
3.3-V CMOS  
36  
36  
8
—
—
—
—
1.2-V to 3.3-V  
18  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–5  
Configuration, Status, and Setup Elements  
Table 2–4. MAX V CPLD Device I/O Pin Count and Usage (Part 2 of 2)  
Function  
Push-Buttons  
I/O Standard  
I/O Count  
Special Pins  
2
2
2
4
1
Push-button 2: Dev_CLRn  
User LEDs  
I2C EEPROM  
SPI EEPROM  
Clock  
—
—
—
—
3.3-V CMOS  
109/159  
Device I/O Total:  
Configuration, Status, and Setup Elements  
This section describes the board's configuration, status, and setup elements.  
Configuration  
The MAX V CPLD development board supports the following device configuration  
methods:  
■
■
Embedded USB-Blaster is the default method for configuring the CPLD at any  
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.  
External USB-Blaster for configuring the CPLD using a JTAG connector. To use this  
optional method to configure the CPLD, you have to mount the JTAG connector or  
header to the back of the board.  
CPLD Configuration over Embedded USB-Blaster  
The USB-Blaster is implemented using a USB Type-B connector (J4), a FTDI USB 2.0  
PHY device (U3), and an Altera MAX II CPLD EPM240M100 (U4). This allows the  
configuration of the MAX V CPLD using a USB cable which connects between the  
USB port on the board (J4) and a USB port of a PC running the Quartus II software.  
The JTAG chain is normally mastered by the embedded USB-Blaster found in the  
MAX II CPLD EPM240M100.  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–6  
Chapter 2: Board Components  
Configuration, Status, and Setup Elements  
Figure 2–3 illustrates an exmaple of the JTAG chain connection.  
Figure 2–3. JTAG Chain  
(Connector not mounted)  
JTAG  
2 x 5 Header  
TDI TDO  
TMS TCK  
Embedded USB-Blaster  
USB  
PHY  
MAX V CPLD  
5M570ZF256C5N  
TCK TMS  
TDI TDO  
MAX II  
EPM240M100  
GPIO (TCK)  
GPIO (TMS)  
GPIO (TDO)  
GPIO (TDI)  
TMS TCK  
TDI TDO  
TDO TDI  
TMS TCK  
JTAG  
2 x 5 Header  
(Connector not mounted)  
The primary configuration mode for the MAX V CPLD is via JTAG using the MAX II  
configuration controller design (embedded USB-Blaster). The board also includes a  
JTAG connector which interfaces directly to the MAX V CPLD as the alternate source  
for configuration.  
CPLD Configuration using External USB-Blaster  
The JTAG programming header (J13) provides another method for configuring the  
CPLD using an external USB-Blaster device with the Quartus II Programmer running  
on a PC. The external USB-Blaster connects to the board through the JTAG connector.  
Figure 2–3 illustrates the JTAG chain.  
Status Elements  
This section describes the status elements. The development board includes two  
status LEDs which connects to the MAX V CPLD.  
Table 2–5 lists the LED board references, names, and functional descriptions.  
Table 2–5. Board-Specific LEDs  
Board Reference  
LED Name  
Description  
D1  
Power  
Blue LED. Illuminates when power is active.  
Green LED. Illuminates when the embedded USB-Blaster is in use. Driven by the  
MAX II CPLD EPM240M100.  
D3  
USB  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–7  
Clock Circuitry  
Table 2–6 lists the board-specific LEDs component references and manufacturing  
information.  
Table 2–6. Board-Specific LEDs Component References and Manufacturing Information  
Board Reference  
Description  
Blue LED  
Green LEDs  
Manufacturer  
Lite-On  
Lumex Inc.  
Manufacturer Part Number  
LTST-C170TBKT  
Manufacturer Website  
www.liteon.com  
D1  
D3  
SML-LXT0805GW-TR  
www.lumex.com  
Setup Elements  
The development board does not have any setup elements.  
1
To power-up the board, ensure that the VAR_VCCIOjumper is set to 3.3 V before  
plugging the USB cable into the USB Type-B connector (J4).  
Clock Circuitry  
The development board includes a single-ended clock input on a 4-pin through-hole  
socket. To replace the clock input with a different frequency oscillator, unplug the  
current oscillator from the board and plug the desired oscillator into the 4-pin socket.  
Figure 2–4 shows the MAX V CPLD development board clock input.  
Figure 2–4. MAX V CPLD Development Board Clock Input  
10 MHz  
Single-Ended  
Clock  
5M570ZF256C5N  
The development board also includes a 6-MHz crystal oscillator which provides the  
input clock for the USB 2.0 PHY device.  
Table 2–16 lists the oscillator component reference and the manufacturing  
information.  
Table 2–7. Oscillator Component Reference and Manufacturing Information  
Board  
Manufacturer  
Part Number  
Description  
Manufacturer  
Manufacturer Website  
www.abracon.com  
www.ctscorp.com  
www.abracon.com  
Reference  
10-MHz oscillator, 3.3 V,  
CMOS, 12.7 mm × 12.7 mm,  
1/2-SZ, 30 ppm.  
J1  
X1  
Y1  
Abracon Corporation ACHL-10.000MHZ-EK  
6-MHz crystal oscillator, 20pF  
SMD.  
CTS Corporation  
ATS060SM-T  
24-MHz oscillator, 3.3 V,  
CMOS SMD 3.2 mm × 2.5 mm, Abracon Corporation  
50 ppm.  
ASE-24.000MHZ-ET  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–8  
Chapter 2: Board Components  
Connectors  
Connectors  
This section describes the connectors available on the development board.  
GPIO Headers  
There are two general-purpose 2×20-pin 0.1-inch expansion headers to allow the  
addition of daughtercards for supplementary board features and functions.  
Table 2–15 lists the GPIO header A schematic signal names and their corresponding  
MAX V CPLD device pin numbers.  
Table 2–8. GPIO Header A Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
GPIO connector A pin  
I/O Standard  
J6.1  
J6.2  
AGPIO_1  
AGPIO_2  
AGPIO_3  
AGPIO_4  
AGPIO_5  
AGPIO_6  
AGPIO_7  
AGPIO_8  
AGPIO_9  
AGPIO_10  
5VIN_CONN  
GND  
P2  
M4  
L4  
N3  
N2  
N1  
M3  
M2  
M1  
L3  
—
—
L1  
L2  
K2  
K3  
J3  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
Power  
J6.3  
J6.4  
J6.5  
3.3-V  
J6.6  
J6.7  
J6.8  
J6.9  
J6.10  
J6.11  
J6.12  
J6.13  
J6.14  
J6.15  
J6.16  
J6.17  
J6.18  
J6.19  
J6.20  
J6.21  
J6.22  
J6.23  
J6.24  
J6.25  
J6.26  
J6.27  
J6.28  
J6.29  
J6.30  
5-V  
—
Ground  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
Power  
AGPIO_11  
AGPIO_12  
AGPIO_13  
AGPIO_14  
AGPIO_15  
AGPIO_16  
AGPIO_17  
AGPIO_18  
AGPIO_19  
AGPIO_20  
AGPIO_21  
AGPIO_22  
AGPIO_23  
AGPIO_24  
AGPIO_25  
AGPIO_26  
3.3VIN_CONN  
GND  
K1  
J1  
J2  
3.3-V  
H2  
H3  
G3  
H1  
G1  
G2  
F2  
F3  
—
—
Ground  
—
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–9  
Connectors  
Table 2–8. GPIO Header A Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Board Reference  
Description  
GPIO connector A pin  
I/O Standard  
Pin Number  
J6.31  
J6.32  
J6.33  
J6.34  
J6.35  
J6.36  
J6.37  
J6.38  
J6.39  
J6.40  
AGPIO_27  
AGPIO_28  
AGPIO_29  
AGPIO_30  
AGPIO_31  
AGPIO_32  
AGPIO_33  
AGPIO_34  
AGPIO_35  
AGPIO_36  
E3  
F1  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
GPIO connector A pin  
E1  
E2  
D2  
D3  
C3  
D1  
E4  
C2  
3.3-V  
Table 2–15 lists the GPIO header B schematic signal names and their corresponding  
MAX V CPLD device pin numbers.  
Table 2–9. GPIO Header B Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
GPIO connector B pin  
I/O Standard  
J7.1  
J7.2  
BGPIO_P_1_R  
BGPIO_N_1_R  
BGPIO_P_2_R  
BGPIO_N_2_R  
BGPIO_P_3_R  
BGPIO_N_3_R  
BGPIO_7  
D15  
C14  
D16  
C15  
E15  
D13  
B14  
C12  
E16  
E14  
—
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
Power  
J7.3  
J7.4  
J7.5  
J7.6  
J7.7  
J7.8  
BGPIO_8  
J7.9  
BGPIO_9  
J7.10  
J7.11  
J7.12  
J7.13  
J7.14  
J7.15  
J7.16  
J7.17  
J7.18  
J7.19  
J7.20  
J7.21  
J7.22  
J7.23  
BGPIO_10  
5VIN_CONN  
GND  
Variable VCCIO  
voltage  
Ground  
—
(1.2-V to 3.3-V)  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
BGPIO_11  
BGPIO_12  
BGPIO_13  
BGPIO_14  
BGPIO_15  
BGPIO_16  
BGPIO_17  
BGPIO_18  
BGPIO_19  
BGPIO_20  
BGPIO_21  
F13  
F16  
F15  
F14  
G16  
G15  
G14  
H16  
H15  
H14  
J16  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–10  
Chapter 2: Board Components  
Connectors  
Table 2–9. GPIO Header B Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
GPIO connector B pin  
I/O Standard  
J7.24  
J7.25  
J7.26  
J7.27  
J7.28  
J7.29  
J7.30  
J7.31  
J7.32  
J7.33  
J7.34  
J7.35  
J7.36  
J7.37  
J7.38  
J7.39  
J7.40  
BGPIO_22  
BGPIO_23  
BGPIO_24  
BGPIO_25  
BGPIO_26  
3.3VIN_CONN  
GND  
J15  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
Power  
J14  
K16  
K15  
K14  
—
Variable VCCIO  
voltage  
(1.2-V to 3.3-V)  
3.3-V  
—
Ground  
—
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
GPIO connector B pin  
BGPIO_27  
BGPIO_28  
BGPIO_29  
BGPIO_30  
BGPIO_31  
BGPIO_32  
BGPIO_33  
BGPIO_34  
BGPIO_35  
BGPIO_36  
L16  
L15  
L14  
M16  
M15  
M14  
L13  
M13  
N14  
N13  
Variable VCCIO  
voltage  
(1.2-V to 3.3-V)  
Table 2–16 lists the GPIO headers component reference and the manufacturing  
information.  
Table 2–10. GPIO Headers Component Reference and Manufacturing Information  
Manufacturer  
Part Number  
Board Reference  
Description  
GPIO headers  
Manufacturer  
Manufacturer Website  
J6, J7  
JMSCONN Technology  
217040SE  
www.jmsconn.com  
PC Speaker Header  
The development board includes one PC speaker header which connects to the MAX  
V CPLD I/O bank 2. The speaker header also supports a compatible standard  
four-pin motherboard speaker.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–11  
Connectors  
Table 2–15 lists the speaker header schematic signal names and their corresponding  
MAX V CPLD device pin numbers.  
Table 2–11. Speaker Header Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
I/O Standard  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Speaker header I/O pin  
Power  
MAX_SPK_0  
MAX_SPK_1  
MAX_SPK_2  
MAX_SPK_3  
MAX_SPK_4  
MAX_SPK_5  
MAX_SPK_6  
MAX_SPK_7  
VAR_VCCIO  
GND  
N15  
N16  
P15  
P14  
H12  
J12  
A8  
Variable VCCIO  
voltage  
J9.1  
(1.2-V to 3.3-V)  
A7  
J9.4  
J9.3  
—
Ground  
—
—
Table 2–16 lists the speaker header component reference and the manufacturing  
information.  
Table 2–12. Speaker Header Component Reference and Manufacturing Information  
Manufacturer  
Part Number  
Board Reference  
Description  
Manufacturer  
Manufacturer Website  
www.samtec.com  
0.025 inches (0.64 mm) square  
post header  
J9  
Samtec  
TSW-104-07-G-S  
20503  
4-pin, 2-wire motherboard  
speaker (1)  
Pc Parts  
Collection  
—
www.pcpartscollection.com  
Note to Table 2–12:  
(1) This component is a compatible unit which can be used on the development board. The MAX V CPLD development kit does not include this  
component.  
DC Motor Headers  
The development board includes two DC motor headers which are driven by six  
open-drain I/Os from the MAX V CPLD. The headers can directly drive micro DC  
motor and also provides two channels for DC motor encoder to measure the motor’s  
rotation speed.  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–12  
Chapter 2: Board Components  
Connectors  
Table 2–15 lists the motor headers schematic signal names and their corresponding  
MAX V CPLD device pin numbers.  
Table 2–13. Motor Headers Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
I/O Standard  
Motor header 1 I/O pin  
Motor header 1 I/O pin  
Motor header 1 I/O pin  
Motor header 1 I/O pin  
Motor header 1 I/O pin  
Motor header 1 I/O pin  
Motor header 1 feedback signal A  
Motor header 1 feedback signal B  
Motor header 1 control signal  
Power  
MAX_MOTOR_1_0  
MAX_MOTOR_1_1  
MAX_MOTOR_1_2  
MAX_MOTOR_1_3  
MAX_MOTOR_1_4  
MAX_MOTOR_1_5  
MOTOR_1_FB_A  
MOTOR_1_FB_B  
MOTOR_1_FB_CTRL  
VAR_VCCIO  
B1  
B3  
A2  
J5.3  
A6  
A4  
A5  
J5.2  
J5.4  
J5.6  
J5.1  
J5.5  
C7  
C6  
C5  
Variable VCCIO  
voltage  
—
(1.2-V to 3.3-V)  
Ground  
GND  
—
Motor header 2 I/O pin  
Motor header 2 I/O pin  
Motor header 2 I/O pin  
Motor header 2 I/O pin  
Motor header 2 I/O pin  
Motor header 2 I/O pin  
Motor header 2 feedback signal A  
Motor header 2 feedback signal B  
Motor header 2 control signal  
Power  
MAX_MOTOR_2_0  
MAX_MOTOR_2_1  
MAX_MOTOR_2_2  
MAX_MOTOR_2_3  
MAX_MOTOR_2_4  
MAX_MOTOR_2_5  
MOTOR_2_FB_A  
MOTOR_2_FB_B  
MOTOR_2_FB_CTRL  
VA_VCCIO  
A10  
A15  
A11  
A13  
A12  
B16  
D12  
B12  
E13  
—
J10.3  
J10.2  
J10.4  
J10.6  
J10.1  
J10.5  
Variable VCCIO  
voltage  
(1.2-V to 3.3-V)  
Ground  
GND  
—
Table 2–16 lists the motor headers component reference and the manufacturing  
information.  
Table 2–14. Motor Headers Component Reference and Manufacturing Information  
Manufacturer  
Part Number  
Board Reference  
Description  
Manufacturer  
Manufacturer Website  
www.samtec.com  
J10  
—
Surface mount terminal strip  
Samtec  
TSM-103-01-L-DV-TR  
DC motor (30:1 Micro Metal  
Gearmotor) (1)  
Cytron  
Technologies  
MO-SPG-10-30K  
www.cytron.com.my  
DC motor encoder (encoder for  
Pololu wheel 42×19 mm) (1)  
—
Pololu  
SN-EN-PW4219  
www.cytron.com.my  
Note to Table 2–14:  
(1) This component is a compatible unit which can be used on the development board. The MAX V CPLD development kit does not include this  
component.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–13  
General User Input/Output  
General User Input/Output  
This section describes the user I/O interface to the CPLD, including the push-buttons  
and status LEDs.  
User-Defined Push-Button Switches  
The development board includes two user-defined push-button switches. Board  
references S1 (USER_PB1) and S2 (USER_PB0) are push-button switches that allow you to  
interact with the MAX V CPLD device. There is no board-specific function for these  
user-defined push-button switches.  
Table 2–15 lists the user-defined push-button switch schematic signal names and their  
corresponding MAX V CPLD device pin numbers.  
Table 2–15. User-Defined Push-Button Switch Schematic Signal Names and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
I/O Standard  
S2  
User-defined push-button switch.  
When the switch is pressed and held  
down, the device pin is set to logic 0;  
when the switch is released, the  
device pin is set to logic 1.  
USER_PB0  
M9  
3.3-V  
S1  
USER_PB1  
R3  
Table 2–16 lists the user-defined push-button switch component reference and the  
manufacturing information.  
Table 2–16. User-Defined Push-Button Switch Component Reference and Manufacturing Information  
Manufacturer  
Board Reference  
Description  
Manufacturer  
Manufacturer Website  
Part Number  
S1, S2  
Push-button switches Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw  
User-Defined LEDs  
The development board includes two general purpose LEDs. Board references D7  
USER_LED1) and D8 (USER_LED0) are user-defined LEDs which allow status and  
(
debugging signals to be driven to the LEDs from the CPLD designs loaded into the  
MAX V CPLD device. There is no board-specific function for these LEDs.  
Table 2–17 lists the user-defined LED schematic signal names and their corresponding  
MAX V CPLD pin numbers.  
Table 2–17. User-Defined LED Schematic Signal Names and Functions  
Schematic  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
User-defined LEDs.  
Driving a logic 0 on the I/O port  
illuminates the LED. Driving a logic 1  
on the I/O port turns off the LED.  
I/O Standard  
Signal Name  
D8  
USER_LED0  
USER_LED1  
P4  
3.3-V  
D7  
R1  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–14  
Chapter 2: Board Components  
Off-Chip EEPROM  
Table 2–18 lists the user-defined LED component reference and the manufacturing  
information.  
Table 2–18. User-Defined LED Component Reference and Manufacturing Information  
Board Reference  
Device Description  
Manufacturer  
Manufacturer Part Number Manufacturer Website  
SML-LX1206GC-TR www.lumex.com  
D7, D8  
Green LEDs  
Lumex, Inc.  
Off-Chip EEPROM  
This section describes the board's EEPROM interface support and also their signal  
names, types, and connectivity relative to the MAX V CPLD device. The board  
include footprints for you to mount the following EEPROM device:  
■
I2C EEPROM  
SPI EEPROM  
■
1
The MAX V CPLD development board only provide the EEPROM device footprints.  
However, the board test system EEPROM function is developed based on the  
EEPROM components described in this section.  
I2C EEPROM  
Board reference U6 is a footprint to mount an I2C EEPROM device onto the  
development board.  
Table 2–19 lists the I2C EEPROM device pin assignments, signal names, and functions.  
The signal names and types are relative to the MAX V CPLD device in terms of I/O  
setting and direction.  
Table 2–19. I2C EEPROM Pin Assignments, Schematic Signal Names, and Functions  
Board  
Reference  
MAX V CPLD Device  
Pin Number  
Description  
Schematic Signal I/O Standard  
Name  
Clock to synchronize the data transfer to and  
from the device.  
U6.1  
U6.2  
I2C_PROM_SCL  
T13  
R13  
Bidirectional serial data pin to transfer  
addresses and data into and out of the  
device.  
I2C_PROM_SDA  
Write-protect pin.  
3.3-V  
■ Tied to Vss: Normal operation (read or  
write to the entire memory of 000-3FF).  
U6.5  
I2C_PROM_WP  
—
■ Tied to Vcc: Write operation disabled (the  
entire memory is write-protected). Read  
operation is not affected.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Chapter 2: Board Components  
2–15  
Off-Chip EEPROM  
Table 2–20 lists the I2C EEPROM component reference and manufacturing  
information.  
Table 2–20. I2C EEPROM Component Reference and Manufacturing Information  
Board  
Reference  
Manufacturing  
Part Number  
Manufacturer  
Website  
Description  
Manufacturer  
8-Kbit EEPROM, 256 × 8-bit  
memory (1)  
U6  
Microchip  
24LC08BT-I/OT  
www.microchip.com  
Note to Table 2–20:  
(1) This component is a compatible unit which can be used on the development board. The MAX V CPLD development kit does not include this  
component.  
SPI EEPROM  
Board reference U8 is a footprint to mount a SPI EEPROM device onto the  
development board.  
Table 2–21 lists the SPI EEPROM pin assignments, signal names, and functions. The  
signal names and types are relative to the MAX V CPLD device in terms of I/O setting  
and direction.  
Table 2–21. SPI EEPROM Pin Assignments, Schematic Signal Names, and Functions  
Schematic Signal  
Name  
MAX V CPLD Device  
Pin Number  
Board Reference  
Description  
SPI chip select signal  
I/O Standard  
U8.1  
U8.2  
U8.5  
U8.6  
SPI_CSn  
SPI_MISO  
SPI_MOSI  
SPI_SCK  
R14  
T15  
P13  
R16  
SPI data in signal (master-in-slave-out)  
SPI data out signal (master-out-slave-in)  
SPI clock signal  
3.3-V  
Table 2–22 lists the SPI EEPROM component reference and manufacturing  
information.  
Table 2–22. SPI EEPROM Component Reference and Manufacturing Information  
Manufacturing  
Part Number  
Manufacturer  
Website  
Board Reference  
Description  
Manufacturer  
U8  
256-Kbit serial EEPROM (1)  
Microchip  
25LC256-I/ST  
www.microchip.com  
Note to Table 2–22:  
(1) This component is a compatible unit which can be used on the development board. The MAX V CPLD development kit does not include this  
component.  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
2–16  
Chapter 2: Board Components  
Power Supply  
Power Supply  
The development board is powered up through a USB cable. The blue LED  
illuminates when the board is powered up. Alternatively, you can also power-up the  
board by connecting three 1.5-V batteries in series (to obtain 4.5 V) through connectors  
BATT+and BATT-  
.
1
Once you plug the USB cable into the board’s USB connector and connect the other  
end of the cable to a PC USB slot, the board disconnects the battery supply and switch  
over to obtain power supply from the USB cable.  
Table 2–23 lists the power rails.  
Table 2–23. Power Rails  
Rail  
1
Schematic Signal Name  
Voltage (V)  
1.8  
Device Pin  
VCCINT  
VCCIO  
Description  
CPLD core voltage  
1.8_VCCINT  
VAR_VCCIO  
3.3V  
2
1.2 – 3.3  
3.3  
CPLD I/O bank 2 variable voltage  
Power for I/O bank 1 and EEPROM  
Power-up USB peripheral  
3
VCCIO  
4
5V  
5.0  
5V_USB  
Table 2–24 lists the power rail component reference and manufacturing information.  
Table 2–24. Power Supply Rail Component Reference and Manufacturing Information  
Manufacturing  
Part Number  
Manufacturer  
Website  
Board Reference  
Description  
Manufacturer  
400 mA, 2.25 MHz synchronous  
step-down DC/DC converter  
U7  
Linear Technology  
LTC3670  
www.linear.com  
Statement of China-RoHS Compliance  
Table 2–25 lists hazardous substances included with the kit.  
Table 2–25. Table of Hazardous Substances’ Name and Concentration Notes (1), (2)  
Hexavalent  
Chromium  
(Cr6+)  
Polybrominated  
diphenyl Ethers  
(PBDE)  
Lead  
(Pb)  
Cadmium  
(Cd)  
Mercury Polybrominated  
Part Name  
(Hg)  
biphenyls (PBB)  
MAX V CPLD development board  
Type A-B USB cable  
X*  
0
0
0
0
0
0
0
0
0
0
0
Notes to Table 2–25:  
(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the  
SJ/T11363-2006 standard.  
(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant  
threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
Additional Information  
This chapter provides additional information about the document and Altera.  
Document Revision History  
The following table shows the revision history for this document.  
Date  
Version  
1.0  
Changes  
January 2011  
Initial release.  
How to Contact Altera  
To locate the most up-to-date information about Altera products, refer to the  
following table.  
Contact (1)  
Technical support  
Contact Method  
Website  
Website  
Email  
Address  
www.altera.com/support  
www.altera.com/training  
custrain@altera.com  
Technical training  
Product literature  
Website  
Email  
www.altera.com/literature  
nacomp@altera.com  
Non-technical support (General)  
(Software Licensing)  
Note to Table:  
Email  
authorization@altera.com  
(1) You can also contact your local Altera sales office or sales representative.  
January 2011 Altera Corporation  
MAX V CPLD Development Board Reference Manual  
Info–2  
Additional InformationAdditional Information  
Typographic Conventions  
Typographic Conventions  
The following table shows the typographic conventions this document uses.  
Visual Cue  
Meaning  
Indicate command names, dialog box titles, dialog box options, and other GUI  
labels. For example, Save As dialog box. For GUI elements, capitalization matches  
the GUI.  
Bold Type with Initial Capital  
Letters  
Indicates directory names, project names, disk drive names, file names, file name  
extensions, software utility names, and GUI labels. For example, \qdesigns  
directory, D: drive, and chiptrip.gdf file.  
bold type  
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.  
Indicates variables. For example, n + 1.  
italic type  
Variable names are enclosed in angle brackets (< >). For example, <file name> and  
<project name>.pof file.  
Indicate keyboard keys and menu names. For example, the Delete key and the  
Options menu.  
Initial Capital Letters  
“Subheading Title”  
Quotation marks indicate references to sections within a document and titles of  
Quartus II Help topics. For example, “Typographic Conventions.”  
Indicates signal, port, register, bit, block, and primitive names. For example, data1  
,
tdi, and input. The suffix  
Indicates command line commands and anything that must be typed exactly as it  
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf  
ndenotes an active-low signal. For example, resetn.  
Courier type  
.
Also indicates sections of an actual file, such as a Report File, references to parts of  
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for  
example, TRI).  
r
An angled arrow instructs you to press the Enter key.  
1., 2., 3., and  
Numbered steps indicate a list of items when the sequence of the items is important,  
such as the steps listed in a procedure.  
a., b., c., and so on  
■
■
■
Bullets indicate a list of items when the sequence of the items is not important.  
The hand points to information that requires special attention.  
1
A question mark directs you to a software help system with related information.  
The feet direct you to another document or website with related information.  
f
c
A caution calls attention to a condition or possible situation that can damage or  
destroy the product or your work.  
A warning calls attention to a condition or possible situation that can cause you  
injury.  
w
The envelope links to the Email Subscription Management Center page of the Altera  
website, where you can sign up to receive update notifications for Altera documents.  
MAX V CPLD Development Board Reference Manual  
January 2011 Altera Corporation  
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