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IZ0066

型号:

IZ0066

描述:

点阵LCD控制器及驱动器[ DOT MATRIX LCD CONTROLLER & DRIVER ]

品牌:

INTEGRAL[ INTEGRAL CORP. ]

页数:

9 页

PDF大小:

171 K

DOT MATRIX LCD CONTROLLER & DRIVER  
IZ0066  
FEATURES  
FUNCTION  
Internal Memory  
Character type dot matrix LCD driver & controller  
Internal driver: 16 common and 40 segment signal output  
Display character format: 5 x 7 dots + cursor,  
5 x 10 dots + cursor  
-
-
-
Character Generator ROM: 8320 bits  
Character Generator RAM: 512 bit  
Display Data RAM: 80 x 8 bits for 80 digits  
Internal automatic reset circuit at power ON  
Internal oscillation circuit  
Easy interface with a 4-bit or 8-bit MPU  
Display character pattern:  
Power Supply Voltage: +5V ± 10%  
LCD Driving Voltage for display: 0 ~ -5V(V5)  
Duty factor selection (selected by programs)  
1/8 duty: 5 x 7 dots format 1 line,  
5 x 7 dots format: 192 kinds, 5 x 10 dots format: 32 kinds  
The special character pattern can be programmable by  
Character Generator RAM directly  
A customer character pattern can be programmable by mask  
option  
1/11 duty: 5 x 10 dots format 1 line  
1/16 duty: 5 x 7 dots format 2 line  
Wide range of instruction function:  
Bare chip available  
Display clear, Cursor home, Display ON/OFF, Display shift  
Cursor ON/OFF, Display character blink, Cursor shift  
Pin-to-Pin replacement for KS0066, HD44780, SED1278  
DESCRIPTION  
The IZ0066 is a dot matrix liquid crystal display controller & driver LSI that displays alphanumerics, characters and symbols.  
It drives dot matrix LCD under microcomputer control. All functions needed for dot matrix LCD drive are internally provided  
on one chip.  
ODERING INFORMATION  
Type  
CGROM  
IZ0066 - 00  
IZ0066 - 01  
IZ0066 - XX  
English  
English  
Numberal  
Numberal  
Japanese  
Cyrillic  
Custom font (XX – ROM code)  
ABSOLUTE MAXIMUM RATINGS  
Characteristic  
Symbol  
Value  
- 0.3 ~ 7.0  
Unit  
Power Supply Voltage  
Driver Supply Voltage  
Input Voltage  
VDD  
V1 ~ V5  
VI  
V
V
VDD - 13.5 ~ VDD + 0.3  
-0.3 ~VDD + 0.3  
- 20 ~ + 75  
V
Operating Temperature  
Storage Temperature  
Ta  
oC  
oC  
Tstg  
- 55 ~ + 125  
Notes: Must keep the relation of VDD V1 V2 V3 V4 V5  
1
1
DOT MATRIX LCD CONTROLLER & DRIVER  
BLOCK DIAGRAM  
IZ0066  
V 1  
Pow er  
supply  
for  
LCD  
D rive  
Parallel/Serial  
D ata conversion  
Circuit  
V 2  
V 3  
V 4  
V 5  
5
5
Busy  
Flag  
Cursor  
Blink  
Control  
Circuit  
Character  
G enerator  
RA M  
Character  
G enerator  
RO M  
512 bits  
8320 bits  
D B  
D B  
0
~D B  
~D B  
3
7
4
4
4
8
8
SEG 1  
to  
SEG 40  
40  
8
D ata  
Register  
I/O  
Buffer  
Segm ent  
Sign al  
D river  
40 - bit  
Shift  
R egister  
40 - bit  
40 Latch  
C ircuit  
40  
8
7
R/W  
RS  
D isplay  
D ata R A M  
80 x 8 bits  
E
7
8
D
Instruction  
Register  
Instruction  
D ecoder  
8
7
7
7
A ddress  
Counter  
COM  
to  
COM 16  
1
16 - bit  
Shift  
Register  
Com m on  
Signal  
D river  
16  
16  
7
O SC1  
O SC2  
CLK 1  
Tim ing  
G eneration  
Circuit  
CLK 2  
M
V
V
D D  
SS  
2
2
DOT MATRIX LCD CONTROLLER & DRIVER  
IZ0066  
ELECTRICAL CHARACTERISTICS  
(Ta = 25oC, VDD = +5V, VSS = 0V unless otherwise specified)  
Characteristic  
Symbol  
Test Condition  
Applicable  
Terminals  
Min  
Typ  
Max  
Unit  
Operating Voltage  
VDD  
IDD  
4.5  
5.5  
0.6  
V
Internal oscillation or external  
0.35  
Operating Current (*1)  
clock  
fOSC = 270KHz  
E, DB0 ~ DB7, R/W,  
RS  
2.2  
VDD  
HIGH Input Voltage  
VIH  
V
V
OSC1  
VDD-1.0  
-0.3  
VDD  
0.6  
LOW Input Voltage  
VIL  
E, DB0 ~ DB7, R/W,  
RS  
OSC1  
DB0 ~ DB7  
-0.2  
2.4  
1.0  
HIGH Output Voltage  
LOW Output Voltage  
VOH  
IOH = -0.205 mA  
V
V
V
CLK1, CLK2, M, D  
DB0 ~ DB7  
0.9VDD  
IOH = -40µA  
IOL = 1.2mA  
IOL = 40µA  
VOL  
0.4  
0.1VDD  
1.0  
CLK1, CLK2, M, D  
COM1 ~ COM16  
SEG1 ~ SEG40  
E
VCOM  
VSEG  
ILKG  
IIL  
IO = ± 0.1mA  
Driver Voltage Descending  
1.0  
Input Leakage Current  
Input LOW Current  
VIN =0V ~ VDD  
-1  
1
µA  
µA  
VCC = 5V (test pull up R)  
RS, R/W,  
DB7  
DB0 ~  
-50  
-125  
-250  
Frequency(*1)  
fEC  
125  
46  
250  
50  
350  
55  
KHz  
%
External  
Clock  
Duty  
DUTY  
tR  
OSC1  
Rise time  
Fall time  
0.2  
0.2  
350  
255  
µs  
tF  
µs  
Internal Clock Frequency(*1)  
fOSC1  
Rf = 91KΩ ± 2%  
190  
245  
270  
250  
KHz  
OSC1, OSC2  
V1 ~ V5  
Ceramic Resonator Oscillation  
Frequency (*1)  
fOSC2  
VDD – V5  
1/5 bias  
1/4 bias  
4.6  
3.0  
10.0  
10.0  
LCD Driving Voltage (*2)  
VLCD1  
VLCD2  
V
Notes: *1). Oscillation circuit  
Resistor circuit  
External clock circuit  
OSC1  
OSC1  
OSC2  
OSC2  
Rf  
Rf:91k  
open  
Frequency input  
+2%  
*2). Input the voltage listed in table below to V1 ~ V5  
Duty  
1/8, 1/11  
1/16  
1/5  
Bias  
1/4  
Power supply  
V1  
V2  
V3  
V4  
V5  
VDD – VLCD/4  
VDD – VLCD/2  
VDD – VLCD/2  
VDD – 3VLCD/4  
VDD – VLCD  
VDD – VLCD/5  
VDD – 2VLCD/5  
VDD – 3VLCD/5  
VDD – 4VLCD/5  
VDD – VLCD  
*VLCD is the LCD driving voltage, refer to the initial set of the instruction code.  
3
3
DOT MATRIX LCD CONTROLLER & DRIVER  
IZ0066  
AC CHARACTERISTICS (VDD = 5V, VSS = 0V, Ta = 25oC)  
(1) Write mode (Writing data from MPU to IZ0066)  
Characteristic  
E Cycle Time  
Symbol  
Test pin  
Min  
Typ  
Max  
Unit  
tC  
tR  
E
E
500  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
E Rise Time  
25  
25  
E Fall Time  
tF  
E
E Pulse Width (High, Low)  
R/W and RS Set-up Time  
R/W and RS Hold Time  
Data Set-up Time  
Data Hold Time  
tW  
E
220  
40  
tSU1  
tH1  
tSU2  
tH2  
R/W, RS  
R/W, RS  
DB0 ~ DB7  
DB0 ~ DB7  
10  
60  
10  
V
V
IH 1  
IL 1  
V
IH 1  
IL 1  
RS  
V
t
SU 1  
t
H 1  
R/W  
V
IL 1  
V
IL 1  
t
H 1  
t
W
V
IL 1  
E
t
R
t
SU 2  
t
H 2  
V
V
IH 1  
IL 1  
V
IH 1  
D B  
0 7  
~ D B  
Valid D ata  
V
IL 1  
t
C
(2) Read mode (Reading data from IZ0066 to MPU)  
Characteristic  
E Cycle Time  
Symbol  
Test pin  
Min  
Typ  
Max  
Unit  
tC  
tR  
E
E
500  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
E Rise Time  
25  
25  
E Fall Time  
tF  
E
E Pulse Width (High, Low)  
R/W and RS Set-up Time  
R/W and RS Hold Time  
Data Output Delay Time  
Data Hold Time  
tW  
tSU1  
tH1  
tD  
E
220  
40  
R/W, RS  
R/W, RS  
DB0 ~ DB7  
DB0 ~ DB7  
10  
120  
tH2  
20  
4
4
DOT MATRIX LCD CONTROLLER & DRIVER  
IZ0066  
V
V
IH 1  
IL 1  
V
IH 1  
IL 1  
RS  
V
t
SU  
t
H
R/W  
V
IL 1  
t
W
t
H
t
F
V
IH 1  
V
IL 1  
V
IL 1  
V
IL 1  
E
t
R
t
D
t
D H  
V
V
IH 1  
IL 1  
V
V
IH 1  
D B  
~ D B  
0 7  
Valid D ata  
IL 1  
t
C
(3) Interface mode with IZ0065  
Characteristic  
Symbol  
Test pin  
Min  
Typ  
Max  
Unit  
Clock Pulse Width High  
Clock Pulse Width Low  
Data Set-up Time  
Data Hold Time  
tWCKH  
tWCKL  
tSU  
CLK  
CLK  
D
800  
800  
300  
300  
500  
ns  
ns  
ns  
ns  
ns  
ns  
tDH  
D
Clock Set-up Time  
M Delay Time  
tCSU  
tDM  
CLK  
M
-1000  
1000  
0.9VD D  
0.9V D D  
CLK 1  
CLK 2  
t
W CK H  
t
W CK H  
t
CSU  
0.9VD D  
0.9V D D  
0.1V D D  
0.1V D D  
0.1V D D  
t
W CK 1  
t
CSU  
0.9VD D  
0.1VD D  
0.9V D D  
0.1V D D  
D
M
t
SU  
t
D M  
0.9V D D  
t
D M  
5
5
DOT MATRIX LCD CONTROLLER & DRIVER  
TERMINAL DESCRIPTION  
IZ0066  
Pin  
INPUT/OUTPUT  
Name  
DESCRIPTION  
INTERFACE  
Power  
VDD  
VSS  
Operating Voltage  
For logical circuit (+5V ± 10%)  
0V(GND)  
Power  
Supply  
V1 – V5  
Negative Supply Voltage  
Segment output  
Common output  
Oscillator  
Bias voltage level for LCD driving  
Segment signal output for LCD driving  
Common signal output for LCD driving  
SEG1– SEG40  
COM1– COM16  
OSC1  
Output  
Output  
Input  
LCD  
LCD  
Both pin connected to Rf resistor or ceramic  
resonator for internal oscillator circuit. In case of  
external frequency use only, the frequency is input  
to OSC1 terminal.  
Resistor or  
Ceramic  
Resonator  
OSC2  
CLK1  
Output  
Output  
Data latch clock  
Data shift clock  
Clock output terminal for the serially transferred  
data to be latched to the driver.  
CLK2  
M
Clock output terminal used when D terminal data  
output shifts the inside of the driver.  
IZ0065  
Alternated signal for LCD  
driver output  
The alternating signal to convert LCD drive  
waveform to AC.  
D
Display data interface  
Character pattern data, which is corresponding to  
each common signal, is supplied to driver serially.  
High  
Low  
Selection  
Non selection  
E
Input  
Enable  
Start anable signal to read or write the data  
MPU  
R/W  
Read/Write  
R/W signal input is used to select the read/write  
mode  
High  
Low  
Read mode  
Write mode  
RS  
Register select  
Register selection input  
High  
Low  
Data register  
and write)  
(for read  
Instruction register (for  
write), Busy flag, address  
counter (for read)  
DB0 – DB7  
Input/Output  
Data interface  
Used for data transfer between the MPU and  
IZ0066. These terminals are for data bus with  
bidirectional three-state.  
Initial 4 bit (DB0-DB3) are not used during 4 bit  
operation (DB7 can be used as a busy flag)  
6
6
DOT MATRIX LCD CONTROLLER & DRIVER  
CONTROL and DISPLAY COMMANDS  
IZ0066  
Execution time  
(fOSC=250KHz)  
Command  
RS  
R/W  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
Remark  
DISPLAY  
CLEAR  
RETURN  
HOME  
L
L
L
L
L
L
L
L
L
H
1.64 ms  
1.64 ms  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
Cursor move to first digit  
*I/D: set cursor move  
direction  
ENTRY  
H
I/D  
SH  
40µs  
MODE SET  
I/D  
H
L
Increase  
Decrease  
*SH: Specifies shift of  
display  
SH  
H
Display is  
shifted  
L
Display is not  
shifted  
*Display  
D
DISPLAY  
ON/OFF  
L
L
L
L
L
L
H
D
C
B
40µs  
H
L
Display on  
Display off  
*Cursor  
C
H
L
Cursor on  
Cursor off  
*Blinking  
B
H
L
Blinking on  
Blinking off  
SHIFT  
L
L
L
L
L
L
L
L
L
H
S/C  
R/L  
X
X
X
X
40µs  
40µs  
SC  
H
L
Display shift  
Cursor move  
R/L  
H
L
Right shift  
Left shift  
SET  
FUNCTION  
H
DL  
N
F
DL  
H
L
8 bits interface  
4 bits interface  
N
F
H
L
2 line display  
1 line display  
H
L
5x10 dots  
5x7 dots  
SET CG  
RAM  
ADDRESS  
SET DD  
RAM  
L
L
L
L
L
H
CG RAM address  
(corresponds to  
CG RAM Data is sent and  
received after this setting  
40µs  
40µs  
cursor address)  
H
DD RAM Data is sent and  
received after this setting  
DD RAM address  
ADDRESS  
READ BUSY  
FLAG &  
ADDRESS  
L
H
BF  
0µs  
BF  
H
L
Busy  
Ready  
Address Counter used for  
Both DD &  
CG RAM address  
-Reads BF indication  
internal operating  
is being performed.  
-Reads address  
counter contents  
WRITE  
DATA  
READ DATA  
H
H
L
Write Data  
Read Data  
Write data DD or CG RAM  
46µs  
46µs  
H
Read data from DD or CG  
RAM  
Note: X – Don’t care.  
7
7
DOT MATRIX LCD CONTROLLER & DRIVER  
APPLICATION CIRCUIT  
IZ0066  
To M PU  
V
LC D (1/5 bias)  
When IZ0065 is externally connected to the IZ0066, you can increase the number of display digits up to 80 characters.  
8
8
DOT MATRIX LCD CONTROLLER & DRIVER  
PAD LAYOUT  
IZ0066  
(0 ,0 )  
IZ0066 PAD DIAG RAM  
C hip size : 4000 x4900  
Pad size : 120 x120  
Unit  
: µm  
The chip substrate is connected to VDD  
.
PAD LOCATION  
( Unit: µm)  
Pad  
No.  
Pad  
No.  
Pad Name  
X
Y
Pad  
No.  
Pad Name  
X
Y
Pad Name  
X
Y
1
2
3
4
5
6
7
8
SEG22  
SEG21  
SEG20  
SEG19  
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
SEG1  
GND  
-2221  
-2041  
-1804  
-1624  
-1444  
-1264  
-1084  
-904  
-724  
-544  
-364  
-184  
-4  
-1830 28  
-1830 29  
-1830 30  
-1830 31  
-1830 32  
-1830 33  
-1830 34  
-1830 35  
-1830 36  
-1830 37  
-1830 38  
-1830 39  
-1830 40  
-1830 41  
-1830 42  
-1830 43  
-1830 44  
-1830 45  
-1830 46  
-1830 47  
-1830 48  
-1830 49  
-1830 50  
-1830 51  
-1552 52  
-1372 53  
-1192 54  
V3  
V4  
V5  
CL1  
CL2  
VCC  
M
D
RS  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2299  
2188  
2008  
1812  
1632  
1436  
1256  
961  
-1012 55  
-832 56  
-862 57  
-472 58  
-292 59  
-112 60  
68 61  
COM9  
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
COM16  
SEG40  
SEG39  
SEG38  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
SEG25  
SEG24  
SEG23  
-530  
-710  
-941  
1830  
1830  
1830  
1830  
1830  
1830  
1830  
1830  
1830  
1830  
1404  
1224  
1044  
864  
-1121  
-1301  
-1481  
-1661  
-1841  
-2036  
-2216  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
-2298  
248 62  
428 63  
608 64  
788 65  
1090 66  
1270 67  
1830 68  
1830 69  
1830 70  
1830 71  
1830 72  
1830 73  
1830 74  
1830 75  
1830 76  
1830 77  
1830 78  
1830 79  
1830 80  
1830  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
R/W  
E
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
COM1  
COM2  
COM3  
COM4  
COM5  
COM6  
COM7  
COM8  
176  
35  
536  
716  
684  
504  
324  
144  
896  
1076  
1256  
1436  
1616  
1920  
2100  
2299  
2299  
2299  
-36  
-216  
-396  
-576  
-756  
-936  
-1116  
-1296  
781  
601  
421  
241  
61  
-119  
-299  
OSC1  
OSC2  
V1  
V2  
9
9
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