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9ZX21901BKLF

型号：

9ZX21901BKLF

描述：

19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

170 K

下载PDF手册
DATASHEET  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Description  
Features/Benefits  
The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for PCI-  
Express Gen3 or QPI applications.The part is backwards compatible  
to PCIe Gen1 and Gen2. A fixed external feedback maintains low  
drift for critical QPI applications. In bypass mode, the 9ZX21901  
can provide outputs up to 400MHz  
•
•
Fixed feedback path/ 0ps input-to-output delay  
9 Selectable SMBus addresses/ Multiple devices can  
share same SMBus segment  
•
•
•
8 dedicated OE# pins/ hardware control of outputs  
PLL or bypass mode/ PLL can dejitter incoming clock  
Selectable PLL BW/ minimizes jitter peaking in  
downstream PLL's  
Recommended Application  
19 output PCIe Gen3/QPI buffer with fixed feedback for Romley  
platforms  
•
Spread spectrum compatible/tracks spreading input clock  
for EMI reduction  
Output Features  
•
•
•
SMBus Interface/ unused outputs can be disabled  
100MHz & 133.33MHz PLL mode/ Legacy QPI support  
Undriven differential outputs in Power Down mode for  
maximum power savings  
•
19 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
•
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps  
Output-to-output skew: <65ps  
Input-to-output delay: Fixed at 0 ps  
Input-to-output delay variation: <50ps  
Phase jitter: PCIe Gen3 < 1ps rms  
Phase jitter: QPI 9.6GB/s < 0.2ps rms  
Functional Block Diagram  
8
OE(5_12)#  
DFB_OUT  
DIF_IN  
DIF_IN#  
Z-PLL  
DIF(18:0)  
(SS Compatible)  
DFB_IN  
DFB_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
Logic  
SMBDAT  
SMBCLK  
IREF  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
1
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
OE11#  
DIF_11#  
DIF_11  
OE10#  
DIF_10#  
DIF_10  
OE9#  
VDDA  
GNDA  
1
2
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
IREF 3  
100M_133M# 4  
HIBW_BYPM_LOBW# 5  
CKPWRGD_PD# 6  
GND 7  
DIF_9#  
DIF_9  
VDD  
VDDR 8  
DIF_IN 9  
9ZX21901B  
DIF_IN# 10  
GND  
SMB_A0_tri 11  
SMBDAT 12  
OE8#  
DIF_8#  
DIF_8  
OE7#  
SMBCLK 13  
SMB_A1_tri 14  
DFB_IN 15  
DIF_7#  
DIF_7  
OE6#  
DFB_IN# 16  
DFB_OUT# 17  
DFB_OUT 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin MLF  
Power Connections  
Pin Number  
PLL Operating Mode Readback Table  
HiBW_BypM_LoBW#  
Low (Low BW)  
Byte0, bit 7  
Byte 0, bit 6  
Description  
0
0
1
0
1
1
VDD  
GND  
Mid (Bypass)  
1
8
2
7
Analog PLL  
Analog Input  
High (High BW)  
21, 31, 45,  
58, 68  
Functionality at Power Up (PLL Mode)  
26, 44, 63  
DIF clocks  
DIF_IN  
(MHz)  
DIF  
100M_133M#  
(MHz)  
DIF_IN  
DIF_IN  
9ZX21901 SMBus Addressing  
1
0
100.00  
133.33  
Pin  
SMBus Address  
(Rd/Wrt bit = 0)  
D8  
SMB_A1_tri SMB_A0_tri  
0
0
M
1
0
M
1
0
M
1
PLL Operating Mode  
HiBW_BypM_LoBW#  
Low  
0
0
M
M
DA  
MODE  
DE  
C2  
C4  
PLL Lo BW  
Mid  
Bypass  
High  
PLL Hi BW  
M
1
1
C6  
CA  
CC  
CE  
NOTE: PLL is OFF in Bypass Mode  
Tri-level Input Thresholds  
Level  
Low  
Voltage  
<0.8V  
1
Mid  
High  
1.2<Vin<1.8V  
Vin > 2.2V  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
2
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Pin Description  
PIN #  
PIN NAME  
PIN TYPE  
PWR  
PWR  
DESCRIPTION  
1
2
VDDA  
3.3V power for the PLL core.  
Ground pin for the PLL core.  
GNDA  
IREF  
This pin establishes the reference for the differential current-mode output pairs.  
It requires a fixed precision resistor to ground. 475ohm is the standard value  
for 100ohm differential impedance. Other impedances require different values.  
See data sheet.  
3
OUT  
Input to select operating frequency  
1 = 100MHz, 0 = 133.33MHz  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
4
5
100M_133M#  
IN  
IN  
HIBW_BYPM_LOBW#  
Notifies device to sample latched inputs and start up on first high assertion, or  
exit Power Down Mode on subsequent assertions. Low enters Power Down  
Mode.  
6
CKPWRGD_PD#  
IN  
7
8
GND  
PWR  
PWR  
Ground pin.  
3.3V power for differential input clock (receiver). This VDD should be treated  
as an analog power rail and filtered appropriately.  
0.7 V Differential TRUE input  
VDDR  
9
10  
DIF_IN  
DIF_IN#  
IN  
IN  
0.7 V Differential Complementary Input  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SMB_A1 to decode 1 of 9 SMBus Addresses.  
11  
SMB_A0_tri  
IN  
12  
13  
SMBDAT  
SMBCLK  
I/O  
IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SMB_A0 to decode 1 of 9 SMBus Addresses.  
True half of differential feedback input, provides feedback signal to the PLL for  
synchronization with the input clock to elimate phase error.  
Complementary half of differential feedback input, provides feedback signal to  
the PLL for synchronization with input clock to elimate phase error.  
14  
15  
16  
SMB_A1_tri  
DFB_IN  
IN  
IN  
IN  
DFB_IN#  
Complementary half of differential feedback output, provides feedback signal  
to the PLL for synchronization with input clock to eliminate phase error.  
17  
18  
DFB_OUT#  
DFB_OUT  
OUT  
OUT  
True half of differential feedback output, provides feedback signal to the PLL  
for synchronization with the input clock to eliminate phase error.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
DIF_0  
DIF_0#  
VDD  
DIF_1  
DIF_1#  
DIF_2  
DIF_2#  
GND  
DIF_3  
DIF_3#  
DIF_4  
DIF_4#  
VDD  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
DIF_5  
DIF_5#  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 5.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
34  
OE5#  
IN  
35  
36  
DIF_6  
DIF_6#  
OUT  
OUT  
0.7V differential Complementary clock output  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
3
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Pin Description (continued)  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
Active low input for enabling DIF pair 6.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 7.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 8.  
1 =disable outputs, 0 = enable outputs  
Ground pin.  
37  
OE6#  
DIF_7  
IN  
38  
39  
OUT  
OUT  
DIF_7#  
40  
OE7#  
IN  
41  
42  
DIF_8  
OUT  
OUT  
DIF_8#  
43  
OE8#  
IN  
44  
45  
46  
47  
GND  
VDD  
PWR  
PWR  
OUT  
OUT  
Power supply, nominal 3.3V  
0.7V differential true clock output  
DIF_9  
DIF_9#  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 9.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 10.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 11.  
1 =disable outputs, 0 = enable outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Active low input for enabling DIF pair 12.  
1 =disable outputs, 0 = enable outputs  
Power supply, nominal 3.3V  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
48  
OE9#  
IN  
49  
50  
DIF_10  
DIF_10#  
OUT  
OUT  
51  
OE10#  
IN  
52  
53  
DIF_11  
DIF_11#  
OUT  
OUT  
54  
OE11#  
IN  
55  
56  
DIF_12  
DIF_12#  
OUT  
OUT  
57  
OE12#  
IN  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
VDD  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
DIF_13  
DIF_13#  
DIF_14  
DIF_14#  
GND  
DIF_15  
DIF_15#  
DIF_16  
DIF_16#  
VDD  
DIF_17  
DIF_17#  
DIF_18  
DIF_18#  
0.7V differential Complementary clock output  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
4
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Electrical Characteristics - Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
4.6  
3.3V Core Supply Voltage  
3.3V Logic Supply Voltage  
Input Low Voltage  
VDDA  
VDD  
VIL  
V
V
V
V
1,2  
1,2  
1
GND-0.5  
Input High Voltage  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
1
Input High Voltage  
VIHSMB  
V
1
°C  
°C  
V
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics - Input/Supply/Common Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0
TYP  
MAX  
70  
UNITS NOTES  
Ambient Operating  
Temperature  
TCOM  
Commmercial range  
°C  
V
1
1
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
VDD + 0.3  
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
1
V
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
400  
105  
140  
7
MHz  
MHz  
MHz  
nH  
2
2
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
2
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
2.7  
pF  
1,4  
COUT  
Output pin capacitance  
6
pF  
1
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Allowable Frequency  
Clk Stabilization  
TSTAB  
1.8  
ms  
1,2  
Input SS Modulation  
Frequency  
fMODIN  
tLATOE#  
tDRVPD  
30  
1
33  
3
kHz  
cycles  
us  
1
(Triangular Modulation)  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
1,3  
1,3  
300  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
V
1,2  
1,2  
1
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
1
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
1
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
V
1
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
1
fMAXSMB  
Maximum SMBus operating frequency  
100  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4 DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
5
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Electrical Characteristics - Clock Input Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
600  
TYP  
750  
MAX  
1150  
UNITS NOTES  
Differential inputs  
(single-ended measurement)  
Differential inputs  
Input High Voltage - DIF_IN  
VIHDIF  
mV  
mV  
mV  
1
1
1
Input Low Voltage - DIF_IN  
VILDIF  
VCOM  
V
SS - 300  
300  
0
300  
(single-ended measurement)  
Input Common Mode  
Voltage - DIF_IN  
Common Mode Input Voltage  
1000  
Input Amplitude - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Peak to Peak value  
Measured differentially  
VIN = VDD , VIN = GND  
300  
0.4  
-5  
1450  
8
5
mV  
V/ns  
uA  
1
1,2  
1
Input Duty Cycle  
dtin  
Measurement from differential wavefrom  
Differential Measurement  
45  
0
55  
125  
%
1
Input Jitter - Cycle to Cycle  
JDIFIn  
ps  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
1
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Rise/Fall Time Matching  
dV/dt  
ΔdV/dt  
Scope averaging on  
Slew rate matching, Scope averaging on  
Rise/fall matching, Scope averaging off  
2.5  
4
20  
1, 2, 3  
1, 2, 4  
1, 7, 8  
ps  
Trf  
125  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
660  
750  
850  
1
1
mV  
VLow  
-150  
150  
Max Voltage  
Min Voltage  
Vswing  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vswing  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
1150  
1
1
1, 2  
1, 5  
1, 6  
mV  
-300  
300  
250  
mV  
mV  
mV  
Vcross_abs  
Scope averaging off  
Scope averaging off  
550  
140  
Δ
-Vcross  
1
Ω
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA.  
Ω Ω  
OH = 6 x IREF and VOH = 0.7V @ ZO=50 (100 differential impedance).  
I
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross  
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.  
7 Measured from single-ended waveform  
8 Measured with scope averaging off, using statistics function. Variation is difference between min and max.  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
6
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Electrical Characteristics - Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
Operating Supply Current  
Powerdown Current  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
IDD3.3OP  
IDD3.3PDZ  
All outputs active @100MHz, CL = Full load;  
All differential pairs tri-stated  
mA  
mA  
1
1
407  
12  
500  
36  
1Guaranteed by design and characterization, not 100% tested in production.  
Electrical Characteristics - Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
-200  
MAX  
-100  
UNITS NOTES  
Input-to-Output Skew in PLL mode  
nominal value @ 25°C, 3.3V  
CLK_IN, DIF[x:0]  
tSPO_PLL  
-300  
ps  
1,2,4,5,8  
Input-to-Output Skew in Bypass mode  
nominal value @ 25°C, 3.3V  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
2.5  
-50  
3.5  
0
4.5  
50  
ns  
ps  
1,2,3,5,8  
1,2,3,5,8  
tDSPO_PLL  
Input-to-Output Skew Varation in Bypass mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF{x:0]  
tDSPO_BYP  
-250  
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZX devices in Hi BW Mode  
ps  
(rms)  
tDTE  
3
Random Differential Spread Spectrum Tracking  
error beween two 9ZX devices in Hi BW Mode  
tDSSTE  
15  
45  
75  
65  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode)  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
1
1
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
3
4
MHz  
MHz  
%
0.7  
45  
1
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
50  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-2  
0
2
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
24  
20  
50  
50  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. Feedback  
path is 695 mils long.  
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate.  
6.t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
7
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Electrical Characteristics - Phase Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
MIN  
TYP  
36  
MAX  
86  
UNITS  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
Notes  
1,2,3  
1.2  
1.9  
3
3.1  
1
1,2  
1,2  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
tjphPCIeG3  
0.5  
1,2,4  
1,5  
Jitter, Phase  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.31  
0.21  
0.5  
0.3  
tjphQPI_SMI  
1,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
0.17  
4
0.2  
10  
1,5  
(rms)  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,6  
0.25  
0.3  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.57  
0.20  
0.22  
0.08  
0.08  
0.7  
1,2,6  
1,2,4,6  
1,5,6  
0.3  
AdditivePhase Jitter,  
tjphPCIeG3  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.3  
0.1  
0.1  
tjphQPI_SMI  
1,5,6  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,5,6  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Subject to final radification by PCI SIG.  
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3  
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
8
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Clock Periods - Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods - Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+  
accuracy requirements (+/-100ppm). The 9ZX21901 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
Power Management Table  
Inputs  
Control Bits/Pins  
DIF(5:12)/  
OE# Pin DIF(5:12)#  
Outputs  
DFB_OUT/  
DFB_OUT#  
PLL  
State  
DIF_IN/  
DIF_IN#  
SMBus  
EN bit  
Other DIF/  
DIF#  
CKPWRGD_PD#  
Hi-Z1  
Hi-Z1  
Hi-Z1  
Running  
Running  
Running  
0
1
X
X
0
1
1
X
OFF  
ON  
ON  
ON  
Hi-Z1  
X
Hi-Z1  
Running  
0
1
Running  
Hi-Z1  
Running  
Running  
NOTE:  
1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs  
Differential Output Termination Table  
Ω
Ω
Ω
Ω
DIF Zo ( ) Iref ( ) Rs ( ) Rp ( )  
100  
85  
475  
412  
33  
27  
50  
43.2  
9ZX21901 Differential Test Loads  
10 inches  
Rs  
Differential Zo  
2pF  
2pF  
Rp  
Rp  
Rs  
HCSL Output  
Buffer  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
9
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
General SMBus serial interface information for the 9ZX21901B  
(See also 9ZX21901 SMBus Addressing on page 2)  
How to Write:  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address XX(H)  
• IDT clock will acknowledge  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address XX(H)  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• IDT clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read addressYY(H)  
• IDT clock will acknowledge  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• vclock will send the data byte count = X  
• IDT clock sends Byte N + X -1  
• IDT clock sends Byte 0 through byte X (if X(H)  
was written to byte 8).  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
Controller (Host)  
IDT (Slave/Receiver)  
IDT (Slave/Receiver)  
starT bit  
T
starT bit  
T
Slave Address XX(H)  
Slave Address XX(H)  
WR  
WRite  
WR  
WRite  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address YY(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
Note: XX(H) is defined by SMBus address select pins  
N
P
Not acknowledge  
stoP bit  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
10  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin #  
Name  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Reserved  
Type  
R
R
RW  
RW  
RW  
0
1
Default  
Latch  
Latch  
1
5
See PLL Operating Mode  
PLL Mode 1  
PLL Mode 0  
DIF_18_En  
DIF_17_En  
DIF_16_En  
5
Readback Table  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
72/71  
70/69  
67/66  
Hi-Z  
Hi-Z  
Hi-Z  
Enable  
Enable  
Enable  
1
1
0
Reserved  
Frequency Select Readback  
0
133MHz  
100MHz  
4
100M_133M#  
Latch  
R
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
39/38  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
1
1
1
1
1
1
1
1
35/36  
32/33  
29/30  
27/28  
24/25  
22/23  
19/20  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Hi-Z  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Bit 7  
Pin #  
65/64  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_15_En  
DIF_14_En  
DIF_13_En  
DIF_12_En  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
1
1
1
1
1
1
1
1
62/61  
60/59  
56/55  
53/52  
50/49  
47/46  
42/41  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Hi-Z  
Enable  
SMBusTable: Output Enable Pin Status Readback Register  
Byte 3  
Bit 7  
Pin #  
57  
Name  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
OE_RB12  
OE_RB11  
OE_RB10  
OE_RB9  
OE_RB8  
OE_RB7  
OE_RB6  
OE_RB5  
Real Time readback of OE#12  
Real Time readback of OE#11  
Real Time readback of OE#10  
Real Time readback of OE#9  
Real Time readback of OE#8  
Real Time readback of OE#7  
Real Time readback of OE#6  
Real Time readback of OE#5  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
Real time  
54  
51  
48  
43  
40  
37  
34  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
OE# pin Low OE# Pin High  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
11  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
SMBusTable: Reserved Register  
Byte 4  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
X
X
X
X
0
0
0
1
B rev = 0001  
C Rev = 0010  
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6  
Bit 7  
Pin #  
-
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
1
1
0
1
1
0
1
1
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Device ID is 219 decimal or  
DB hex.  
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin #  
Name  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
12  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
DIF Reference Clock  
Common Recommendations for Differential Routing  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs  
Rt  
49.9  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max  
inch  
inch  
1
1
L4 length, route as coupled stripline 100ohm differential trace  
1.8 min to 14.4 max  
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max  
inch  
inch  
2
2
L4 length, route as coupled stripline 100ohm differential trace  
0.225 min to 12.6 max  
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Down Device  
REF_CLK Input  
L3' L3  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Add-in Board  
REF_CLK Input  
L3' L3  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
13  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Alternative Termination for LVDS and other Common Differential Signals (figure 3)  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
Figure 3  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Cable Connected AC Coupled Application (figure 4)  
Component  
R5a, R5b  
R6a, R6b  
Cc  
Value  
8.2K 5%  
1K 5%  
Note  
0.1 µF  
Vcm  
0.350 volts  
Figure 4  
3.3 Volts  
R5a  
R6a  
R5b  
R6b  
Cc  
L4  
L4'  
Cc  
PCIe Device  
REF_CLK Input  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
14  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
(Ref. )  
Seating Plane  
(ND - 1)x  
e
&
NE  
ND  
(Ref. )  
Even  
A1  
Index Area  
N
L
A3  
E2  
N
e
(Typ.)  
2
If N &  
NE  
D
Anvil  
Singulation  
are Even  
1
2
1
(N - 1)x  
e
E
OR  
E
(Ref. )  
E2  
2
Sawn  
Singulation  
Top View  
D
b
e
Thermal  
Base  
(Ref.)  
D2  
A
N &  
NE  
Odd  
D
2
D2  
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
C
C
0.08  
THERMALLY ENHANCED, VERY THIN, FINE PITCH  
QUAD FLAT / NO LEAD PLASTIC PACKAGE  
DIMENSIONS  
DIMENSIONS (mm)  
SYMBOL  
72L  
72  
18  
SYMBOL  
MIN.  
0.8  
0
MAX.  
1.0  
0.05  
N
ND  
A
A1  
NE  
18  
A3  
b
e
0.25 Reference  
0.18 0.3  
0.50 BASIC  
10.00 x 10.00  
D x E BASIC  
D2 MIN. / MAX.  
E2 MIN. / MAX.  
L MIN. / MAX.  
5.75  
5.75  
0.3  
6.15  
6.15  
0.5  
Ordering Information  
Part / Order Number Shipping Package  
Package  
72-pin MLF  
72-pin MLF  
Temperature  
0 to +70°C  
0 to +70°C  
9ZX21901BKLF  
9ZX21901BKLFT  
Trays  
Tape and Reel  
"LF" designates PB-free configuration, RoHS compliant.  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1586J - 12/08/11  
15  
9ZX21901B  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Revision History  
Rev.  
Issue Date Who Description  
1. Slightly modified name of pin 6 and corrected pin description of pin 6, to remove  
Page #  
reference to CK505  
A
5/13/2009 RDW  
Various  
2. Added Typical numbers to key parameters in electrical characteristics tables.  
3. Move to final.  
1. Updated Pin 8 name to VDDR to indicate that it is the VDD for the input receiver.  
2. Change MAX operating current from 600 to 500mA.  
B
8/7/2009  
RDW  
Various  
C
D
E
8/12/2009 RDW 1. Updated VDDR pin description to include 3.3V information.  
Various  
2
8/14/2009 RDW 1. Inserted Pins 19 and 72 into pinout after they were inadvertenly removed.  
10/7/2009 RDW 1. Corrected units from ns to ps for the tDSPO_PLL and tDSPO_BYP parameters  
1. Updated QPI reference to 9.6GTs, added note about variable feedback path  
2. Reformatted electrical tables to fit new standard format  
3. Merged Phase Jitter Tables into Single Table.  
F
6/22/2010 RDW  
4. Added output termination/test load drawing and table  
1, 5, 6, 9  
1. Updated front page to standard 9ZX format.  
2. Clarified that SMBus Address Selection table includes the Read/Write Bit. Minor  
clarifications to other tables.  
3. Added additive phase jitter table for bypass mode.  
G
8/3/2010  
3/2/2011  
RDW  
1-3, 5-11  
H
J
RDW 1. Added rise/fall varation spec to HCSL_Out table  
12/8/2011 RDW 1. Updated tDSPO_BYP parameter from +/-350 to +/-250ps.  
6
7
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
IDT Singapore Pte. Ltd.  
1 Kallang Sector #07-01/06  
KolamAyer Industrial Park  
Singapore 349276  
IDT Europe Limited  
321 Kingston Road  
Leatherhead, Surrey  
KT22 7TU  
United States  
800 345 7015  
+408 284 8200 (outside U.S.)  
Phone: 65-6-744-3356  
Fax: 65-6-744-1764  
England  
Phone: 44-1372-363339  
Fax: 44-1372-378851  
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of  
Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks are  
a
or may be trademarks or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
16  
厂商 型号 描述 页数 下载

IDT

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IDT

 		9ZX21201AKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLF 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21501B 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLF 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLFT 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901B 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901BKLFT 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

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