请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

TXS0206-29_1007

型号：

TXS0206-29_1007

描述：

MMC卡，SD卡，记忆棒电压转换收发器和LDO稳压器具有ESD保护和EMI滤波[ MMC, SD CARD, Memory Stick VOLTAGE-TRANSLATION TRANSCEIVER AND LDO VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

25 页

PDF大小：

563 K

下载PDF手册
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO  
VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING  
1
FEATURES  
•
Level Translator  
•
•
ESD Protection Exceeds JESD 22 (A Port)  
–
–
VCCA Range of 1.1 V to 3.6 V  
–
–
2000-V Human-Body Model (A114-B)  
1000-V Charged-Device Model (C101)  
Fast Propagation Delay (4 ns Max When  
Translating Between 1.8 V and 2.9 V)  
±8-kV Contact Discharge IEC 61000-4-2 ESD  
(B Port)  
•
Low-Dropout (LDO) Regulator  
–
–
–
–
200-mA LDO Regulator With Enable  
2.9-V Output Voltage  
3.05-V to 5.5-V Input Voltage Range  
Very Low Dropout: 200 mV at 200 mA  
YFP PACKAGE  
(TOP VIEW)  
TERMINAL ASSIGNMENTS  
1
2
3
4
1 2  
3
4
A
B
C
D
E
DAT2A  
DAT3A  
CMDA  
DAT0A  
DAT1A  
VCCA  
VBATT  
GND  
CLKA  
CLK-f  
WP/CD  
VCCB O/P  
GND  
DAT2B  
DAT3B  
CMDB  
DAT0B  
DAT1B  
A
B
C
D
E
CLKB  
EN  
DESCRIPTION/ORDERING INFORMATION  
The TXS0206-29 is a complete solution for interfacing microprocessors with MultiMediaCards (MMCs), secure  
digital (SD) cards, and Memory Stick™ cards. It is comprised of a high-speed level translator, a low-dropout  
(LDO) voltage regulator, IEC level ESD protection, and EMI filtering circuitry.  
The voltage-level translator has two supply voltage pins. VCCA can be operated over the full range of 1.1 V to  
3.6 V. VCCB is set at 2.9 V and is supplied by an internal LDO. The integrated LDO accepts input voltages from  
3.05V to as high as 5.5 V and outputs 2.9 V, 200 mA to the B-side circuitry and to the external memory card. The  
TXS0206-29 enables system designers to easily interface low-voltage microprocessors to memory cards  
operating at 2.9 V.  
Memory card standards recommend high-ESD protection for devices that connect directly to the external memory  
card. To meet this need, the TXS0206-29 incorporates ±8-kV Contact Discharge protection on the card side.  
Since memory cards are widely used in mobile phones, PDAs, digital cameras, personal media players,  
camcorders, set-top boxes, etc. Low static power consumption and small package size make the TXS0206-29 an  
ideal choice for these applications. The TXS0206-29 is offered in a 20-bump wafer chip scale package (WCSP).  
This package has dimensions of 1.96 mm × 1.56 mm, with a 0.4-mm ball pitch for effective board-space savings  
ORDERING INFORMATION(1)  
TA  
–40°C to 85°C WCSP – YFP (Pb-free)  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(3)  
Tape and reel  
TXS0206-29YFPR  
_ _ _ 3 V 2  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) The actual top-side marking has three preceding characters to denote year, month, and sequence code.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
REFERENCE DESIGN  
V
CCB  
V
CCA  
V
CCB  
C3  
C4  
C1  
0.1 μF  
0.1 μF  
0.1 μF  
J1  
U1A  
U2  
DAT2B  
DAT3B  
CMDB  
0
1
A2  
B3  
D4  
DAT2  
DAT3  
CMD  
VSS1  
VDD  
VDDA  
DAT0  
DAT1  
DAT2  
DAT3  
CMD  
VCCA  
VCCB O/P  
D1  
E1  
A1  
B1  
C1  
D2  
E2  
C2  
DAT0B  
DAT0A  
DAT1A  
DAT2A  
DAT3A  
CMDA  
CLKA  
CLK-f  
GND  
2
DAT0B  
3
4
E4 DAT1B  
A4 DAT2B  
B4 DAT3B  
DAT1B  
DAT2B  
DAT3B  
5
CLKB  
CLK  
6
VSS2  
DAT0  
DAT1  
DAT0B  
DAT1B  
7
8
C4 CMDB  
CLK  
CMDB  
CLKB  
9
CLKB  
D3  
WP/CD (Physical)  
CD (Physical)  
GND  
CLKin  
GND  
10  
11  
12  
13  
CD  
C3  
GND  
A3  
WP/CD  
GND  
WP  
WP/CD  
WP (Physical)  
Processor  
SD/SDIO MMC  
54794-0978  
SD/SDIO  
CardConnector  
TXS0206-29  
WP/CD  
Figure 1. Interfacing With SD/SDIO Card  
ESD – 8-kV Contact Discharge  
B Side 2.9 V  
ESD – 2 kV  
1.8 V A Side  
CLK  
Feedback CLK  
CMD  
CLK  
CMD  
Data 0–3  
Level-Shifter  
Integrated  
ASIP  
Antenna  
Pins 10, 11  
CPU  
Data 0–3  
EN  
MMC,  
SD Card, or  
MS Card  
EMI Filter  
WP, CD  
WP, CD 1.8-V Pullup  
Integrated PSU  
2.9 V, 200 mA  
WP, CD  
Integrated Pullup/Pulldown Resistors  
Figure 2. Typical Application Circuit  
2
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
Table 1. LOGIC TABLE  
EN  
L
LDO  
Disabled  
Active  
TRANSLATOR I/Os  
Disabled, pulled to VCCA, VCCB O/P through R1 and R2  
at 70kΩ pullup resistors respectively  
H
Active  
TERMINAL FUNCTIONS  
TERMINAL  
TYPE  
DESCRIPTION  
NO.  
A1  
NAME  
DAT2A  
VCCA  
I/O  
Data bit 2 connected to host. Referenced to VCCA. Includes R1 pullup resistor to VCCA (see Note A).  
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.  
A2  
Power  
Connected to write protect on the mechanical connector. The WP pin has an internal 100-kΩ pullup  
A3  
A4  
WP/CD  
DAT2B  
Output  
I/O  
resistor to VCCA  
.
Data bit 2 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to  
VCCBO/P (see Note A).  
B1  
B2  
B3  
DAT3A  
VBATT  
I/O  
Data bit 3 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).  
LDO input voltage from Battery-Supply  
Input  
VCCB O/P  
Output  
LDO output voltage and B-port supply voltage. VCCBO/P powers all B-port I/Os.  
Data bit 3 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to  
VCCBO/P (see Note A).  
B4  
C1  
DAT3B  
CMDA  
GND  
I/O  
I/O  
Command bit connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note  
A).  
C2,  
C3  
Ground  
Command bit connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to  
VCCBO/P (see Note A).  
C4  
CMDB  
I/O  
D1  
D2  
D3  
DAT0A  
CLKA  
CLKB  
I/O  
Data bit 0 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).  
Input  
Clock signal connected to host. Referenced to VCCA.  
Output  
Clock signal connected to memory card. Referenced to VCCBO/P.  
Data bit 0 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to  
VCCBO/P (see Note A).  
D4  
DAT0B  
I/O  
E1  
E2  
DAT1A  
CLK-f  
I/O  
Data bit 1 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).  
Clock feedback to host for resynchronizing data to a processor. Leave unconnected if not used.  
Enable/disable control. Pull EN low to place all outputs in Hi-Z state and to disable the LDO.  
Output  
E3  
E4  
EN  
Input  
I/O  
Referenced to VCCA  
.
Data bit 1 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to  
VCCBO/P (see Note A).  
DAT1B  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
VCCA  
EN  
(see Note B)  
VCCB  
CLKA  
CLKB  
CLK-f  
VCCA  
VCCA  
VCCA  
VCCA  
VCCA  
VCCB  
VCCB  
VCCB  
VCCB  
VCCB  
One-Shot  
One-Shot  
R1  
(see Note A)  
R2  
(see Note A)  
Translator  
Gate Control  
CMDA  
CMDB  
One-Shot  
One-Shot  
Translator  
One-Shot  
One-Shot  
R1  
(see Note A)  
R2  
(see Note A)  
Translator  
Gate Control  
DAT0A  
DAT0B  
One-Shot  
One-Shot  
Translator  
One-Shot  
One-Shot  
R1  
(see Note A)  
R2  
(see Note A)  
Translator  
Gate Control  
DAT1A  
DAT1B  
One-Shot  
One-Shot  
Translator  
One-Shot  
One-Shot  
R2  
(see Note A)  
R1  
(see Note A)  
Translator  
Gate Control  
DAT2A  
DAT2B  
One-Shot  
One-Shot  
Translator  
One-Shot  
One-Shot  
R1  
(see Note A)  
R2  
(see Note A)  
Translator  
Gate Control  
DAT3A  
DAT3B  
One-Shot  
One-Shot  
Translator  
VCCA  
100 kW  
WP/CD  
A. R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows:  
R1 and R2 = 40 kΩ when a logic level low is applied to the A port or B port.  
R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port.  
R1 and R2 = 70 kΩ when the port is deselected (or in High-Z or 3-state).  
B. EN controls all output buffers. When EN = low, all outputs are Hi-Z.  
Figure 3. Logic Diagram  
4
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
V
CCB  
R7 R8 R9 R10 R11  
HOST  
CLK  
CARD  
R1  
CLKB  
R2  
R4  
R6  
CMD  
Data0  
Data1  
Data2  
Data3  
CMDB  
DAT0B  
DAT1B  
DAT2B  
DAT3B  
R3  
R5  
GND  
GND  
RESISTORS  
R1, R2, R3, R4, R5, R6  
Tolerance  
BIDIRECTIONAL ZENER DIODES  
40 Ω  
20ꢀ  
Vbr min  
14 V at 1 mA  
<20 pF  
Line capacitance  
R7, R8, R9, R10, R11  
Tolerance  
40 kΩ  
30ꢀ  
Figure 4. ASIP Block Diagram  
V
CCA  
R
WP/CD  
WP/CD  
RESISTORS  
R
100 kΩ  
30%  
WP/CD  
Tolerance  
Figure 5. WP/CD Pullup Resistor  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
Level Translator  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
MAX UNIT  
VCCA  
Supply voltage range  
Input voltage range  
4.6  
4.6  
V
I/O ports (A port)  
I/O ports (B port)  
Control inputs  
A port  
VI  
4.6  
V
4.6  
4.6  
Voltage range applied to any output in the high-impedance or  
power-off state  
VO  
VO  
V
V
B port  
4.6  
A port  
4.6  
Voltage range applied to any output in the high or low state  
B port  
4.6  
IIK  
IOK  
IO  
Input clamp current  
VI < 0  
–50  
–50  
±50  
±100  
150  
mA  
mA  
mA  
mA  
°C  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCCA or GND  
Storage temperature range  
Tstg  
–65  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
THERMAL IMPEDANCE RATINGS  
TYP  
UNIT  
θJA  
Package thermal impedance(1)  
117  
°C/W  
(1) The package thermal impedance is calculated in accordance with JESD 51-7.  
ABSOLUTE MAXIMUM RATINGS(1)  
LDO  
over operating free-air temperature range (unless otherwise noted)  
MIN  
MAX UNIT  
VIN  
Input voltage range  
2.3  
6.5  
4.6  
V
V
VOUT  
Output voltage range  
–0.3  
Peak output current  
220  
mA  
Continuous total power dissipation  
Junction temperature range  
Storage temperature range  
TBD mW  
TJ  
–55  
–55  
150  
150  
°C  
°C  
Tstg  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
6
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
RECOMMENDED OPERATING CONDITIONS(1)  
Level Translator  
VCCA  
VCCB  
2.9 V  
2.9 V  
2.9 V  
2.9 V  
MIN  
MAX  
3.6  
UNIT  
VCCA  
Supply voltage  
1.1  
V
1.1 V to 1.95 V  
1.95 V to 3.6 V  
1.1 V to 1.95 V  
1.95 V to 3.6 V  
1.1 V to 3.6 V  
1.1 V to 1.95 V  
1.95 V to 3.6 V  
1.1 V to 1.95 V  
1.95 V to 3.6 V  
1.1 V to 3.6 V  
VCCI – 0.2  
VCCI  
A-Port CMD and  
DATA I/Os  
VCCI – 0.4  
VCCI  
VIH  
High-level input voltage  
VCCI – 0.2  
VCCI  
V
B-Port and DATA  
I/Os  
VCCI – 0.4  
VCCI  
OE and CLKA  
VCCI × 0.65  
VCCI  
0
0
0
0
0
0.15  
A-Port CMD and  
DATA I/Os  
0.15  
VIL  
VO  
IOH  
Low-level input voltage  
Output voltage  
0.15  
V
V
B-Port CMD and  
DATA I/Os  
0.15  
OE and CLKA  
Active state  
3-state  
VCCI × 0.35  
0
VCCO  
1.1 V to 1.3 V  
1.4 V to 1.6 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
3 V to 3.6 V  
–0.5  
–1  
–2  
–4  
–8  
0.5  
1
High-level output current (CLK-f output)  
Low-level output current (CLK-f output)  
2.9 V  
2.9 V  
mA  
1.1 V to 1.3 V  
1.4 V to 1.6 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
3 V to 3.6 V  
IOL  
2
mA  
4
8
IOH  
High-level output current (CLK output)  
Low-level output current (CLK output)  
Input transition rise or fall rate  
2.9 V  
2.9 V  
–8  
8
mA  
mA  
ns/V  
°C  
IOL  
Δt/Δv  
TA  
5
Operating free-air temperature  
–40  
85  
(1) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
RECOMMENDED OPERATING CONDITIONS  
LDO  
MIN  
200  
1
MAX  
UNIT  
mA  
μF  
IOUT(PK)  
COUT  
TJ  
Peak output current  
Output capacitance  
100  
125  
Operating junction temperature  
–40  
°C  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
MAX UNIT  
V
ELECTRICAL CHARACTERISTICS  
Level Translator  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
IOH = –100 μA  
VCCA  
1.1 V to 3.6 V  
1.1 V  
VCCBO/P  
MIN  
VCCA × 0.8  
0.8  
TYP(1)  
IOH = –0.5 mA  
IOH = –1 mA  
IOH = –2 mA  
IOH = –4 mA  
IOH = –8 mA  
1.4 V  
1.05  
A port  
(CLK-f output)  
1.65 V  
2.3 V  
1.2  
VOH  
2.9 V  
1.75  
3 V  
2.3  
A port  
(DAT and CMD IOH = –20 μA  
1.1 V to 3.6 V  
VCCA × 0.8  
outputs)  
IOL = 100 μA  
1.1 V to 3.6 V  
1.1 V  
VCCA × 0.8  
IOL = 0.5 mA  
0.35  
0.35  
0.45  
0.55  
0.7  
IOL = 1 mA  
IOL = 2 mA  
IOL = 4 mA  
IOL = 8 mA  
IOL = 135 μA  
IOL = 180 μA  
1.4 V  
A port  
(CLK-f output)  
2.9 V  
V
V
1.65 V  
2.3 V  
VOL  
3 V  
0.4  
0.4  
A port  
(DAT and CMD IOL = 220 μA  
1.1 V to 3.6 V  
2.9 V  
0.4  
outputs)  
IOL = 300 μA  
0.4  
IOL = 400 μA  
0.55  
VCCBO/P ×  
0.8  
IOH = –100 μA  
IOH = –8 mA  
IOH = –20 μA  
B port  
(CLK output)  
2.9 V  
2.9 V  
2.9 V  
VOH  
1.1 V to 3.6 V  
1.1 V to 3.6 V  
2.3  
V
V
B port  
(DAT output)  
VCCBO/P ×  
0.8  
VCCBO/P ×  
0.8  
IOL = 100 μA  
CLKB output  
port  
IOL = 8 mA  
0.7  
0.4  
0.4  
0.4  
0.4  
0.55  
±1  
IOL = 135 μA  
IOL = 180 μA  
VOL  
B port  
(DAT and CMD IOL = 220 μA  
1.1 V to 3.6 V  
2.9 V  
V
outputs)  
IOL = 300 μA  
IOL = 400 μA  
II  
Control inputs  
VI = VCCA or GND  
1.1 V to 3.6 V  
1.1 V to 3.6 V  
1.1 V to 3.6 V  
2.9 V  
2.9 V  
2.9 V  
μA  
μA  
μA  
ICCA  
ICCB  
VI = VCCI or GND,  
VI = VCCI or GND,  
IO = 0  
IO = 0  
6
5
A port  
5.5  
15  
3.5  
3
6.5  
17.5  
4.5  
4
Cio  
Ci  
pF  
pF  
B port  
Control inputs  
Clock input  
VI = VCCA or GND  
(1) All typical values are at TA = 25°C.  
8
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
ELECTRICAL CHARACTERISTICS  
LDO  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP(1)  
VOUT + VDO  
MAX  
UNIT  
VBATT  
VOUT  
Input voltage  
5.5  
V
Nominal TA = 25°C  
All conditions  
2.9  
Output voltage  
V
2.75  
3.05  
ΔVOUT  
Output voltage tolerance  
Dropout voltage  
Nominal TA = 25°C  
IOUT = 200 mA  
IOUT = 0  
±3  
%
VDO  
200  
250  
40  
mV  
IGND  
Ground-pin current  
IOUT < 100 mA  
100 mA ≤ IOUT ≤ 200 mA  
RL = 0 Ω  
200  
400  
μA  
IOUT(SC)  
PSRR  
tSTR  
Short-circuit current  
Power-supply rejection ratio  
Start-up time  
300  
50  
mA  
dB  
μs  
f = 1 kHz  
VIN = 3.05 V, VOUT = 2.9 V,  
CNR = 0.01 μF, IOUT = 200 mA  
f = 10 kHz  
40  
VOUT = 2.9 V, IOUT = 200 mA, COUT = 2.2 μF  
200  
(1) All typical values are at TA = 25°C.  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range, VCCB = 2.9 V ± 5% (unless otherwise noted)  
VCCA = 1.2 V  
± 0.1 V  
VCCA = 1.5 V  
± 0.1 V  
VCCA = 1.8 V  
± 0.15 V  
VCCA = 2.5 V VCCA = 3.3 V  
± 0.2 V  
± 0.3 V  
UNIT  
MIN  
MAX MIN  
MAX MIN  
MAX  
MIN MAX  
MIN MAX  
Push-pull driving  
40  
1
60  
1
60  
1
60  
60  
Command  
Mbps  
Open-drain driving  
1
1
Data rate  
Clock  
Data  
60  
40  
60  
60  
60  
60  
60  
60  
MHz  
Mbps  
ns  
Push-pull driving  
60  
60  
Push-pull driving  
25  
1
17  
1
17  
1
17  
1
17  
1
Command  
Open-drain driving  
μs  
Pulse  
tW  
duration  
Clock  
Data  
8.3  
25  
8.3  
17  
8.3  
17  
8.3  
17  
8.3  
17  
ns  
Push-pull driving  
ns  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range, VCCB = 2.9 V ± 5% (unless otherwise noted)  
VCCA  
VCCA  
VCCA  
VCCA  
VCCA  
= 1.2 V  
± 0.1 V  
= 1.5 V  
± 0.1 V  
= 1.8 V  
± 0.15 V  
= 2.5 V  
± 0.2 V  
= 3.3 V  
± 0.3 V  
FROM  
(INPUT) (OUTPUT)  
TO  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
MIN MAX  
MIN MAX  
MIN  
MAX  
MIN MAX  
MIN  
MAX  
Push-pull driving  
10.8  
6.1  
4.6  
5.5  
3.7  
3.8  
4.1  
Open-drain driving  
(H-to-L)  
3.2  
71  
10.6  
2.7  
83  
6.6  
2.4  
89  
2.1  
98  
4.4  
2
CMDA  
CMDB  
CMDB  
CMDA  
Open-drain driving  
(L-to-H)  
175  
12  
180  
6.8  
7.3  
201  
5.2  
6.4  
249  
4.1  
5.7  
101  
233  
3.4  
4.6  
Push-pull driving  
Open-drain driving  
(H-to-L)  
2.9  
77  
9.4  
2.1  
87  
2
2
2.2  
tpd  
ns  
Open-drain driving  
(L-to-H)  
243  
214  
93  
215  
99  
261  
105  
248  
CLKA  
DATxA  
DATxB  
CLKA  
EN  
CLKB  
DATxB  
DATxA  
CLK-f  
Push-pull driving  
11.7  
11.1  
11.5  
24.7  
1
6.2  
6.2  
6.2  
13  
4.7  
4.7  
5
3.7  
3.7  
3.9  
6.8  
1
3.5  
3.7  
6.2  
4.8  
1
Push-pull driving  
Push-pull driving  
Push-pull driving  
Push-pull driving  
Push-pull driving  
Push-pull driving  
Push-pull driving  
Open-drain driving  
8.9  
1
B-port  
A-port  
B-port  
A-port  
1
ten  
μs  
EN  
1
1
1
1
1
EN  
40  
39  
35  
38  
34  
tdis  
ns  
EN  
40  
38  
38  
38  
36  
1.6  
32  
0.6  
1.6  
1.7  
66  
1.7  
0.4  
0.8  
1.6  
1
12.2  
120  
12.7  
11.6  
6.7  
214  
4.8  
6.8  
4
0.4  
44  
8.3  
127  
7.2  
8.4  
5.6  
196  
4.9  
5
1.1  
52  
5.9  
150  
4.5  
6.3  
5.2  
184  
4.9  
5.2  
3.1  
3.7  
1.5  
2.7  
5
1.9  
62  
3.3  
201  
1.5  
4.2  
5.2  
214  
5
0.8  
74  
4.2  
194  
1.4  
3.3  
5
CMDA rise time  
trA  
trB  
tfA  
ns  
ns  
ns  
ns  
CLK-f rise time  
DATxA rise time  
0.5  
0.6  
0.5  
71  
0.4  
1
0.7  
1.8  
1.5  
76  
0.7  
1.1  
1.9  
79  
Push-pull driving  
Push-pull driving  
1
CMDB rise time  
Open-drain driving  
73  
185  
5.1  
14  
CLKB rise time  
DATxB rise time  
1.5  
0.6  
0.8  
1.6  
0.4  
0.1  
1.4  
1
1.5  
0.2  
0.2  
1.6  
0.1  
0.2  
1.6  
0.8  
1.7  
0.8  
1.6  
0.9  
0.3  
1.6  
0.3  
0.3  
1.6  
0.8  
1.7  
0.2  
1.6  
1
Push-pull driving  
5.3  
1.5  
3.7  
2.8  
2.9  
5.6  
1.6  
4.5  
4.9  
Push-pull driving  
2.3  
3.7  
6.8  
3.8  
5.4  
2.3  
4.1  
4.3  
1
2.3  
3.9  
1.3  
1.8  
6.3  
1.3  
5.1  
6.9  
CMDA fall time  
Open-drain driving  
3.9  
4
1.6  
0.6  
0.4  
0.8  
0.9  
0.9  
0.8  
CLK-f fall time  
DATxA fall time  
Push-pull driving  
1
3.9  
4.5  
4.3  
4
Push-pull driving  
1.5  
1
CMDB fall time  
Open-drain driving  
1.9  
4.2  
4.9  
tfB  
CLKB fall time  
DATxB fall time  
1.6  
1
1.6  
2.3  
Push-pull driving  
Push-pull driving  
4.8  
Channel-to-channel  
skew  
tSK(O)  
1
1
1
1
1
ns  
Push-pull driving  
40  
1
60  
1
60  
1
60  
1
60  
1
Command  
Mbps  
Open-drain driving  
Max data rate  
Clock  
Data  
60  
40  
60  
60  
60  
60  
60  
60  
60  
60  
MHz  
Push-pull driving  
Mbps  
10  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
OPERATING CHARACTERISTICS  
TA = 25°C, VCCB = 2.9 V  
VCCA TYP  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
3.3 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3 V  
CLK  
Enabled  
15  
15  
15  
15.7  
17.1  
17.1  
6.5  
A-port input,  
B-port  
output  
DATA  
Enabled  
6.3  
6.4  
6.5  
6.5  
6.5  
14  
B-port input,  
A-port  
output  
DATA  
Enabled  
12.5  
12.3  
12.3  
12.5  
14  
CL = 0,  
f = 10 MHz,  
tr = tf = 1 ns  
(1)  
CpdA  
pF  
CLK  
Disabled  
0.2  
1.2  
0.2  
1.2  
0.2  
1.2  
0.3  
1.2  
0.3  
1.2  
0.3  
A-port input,  
B-port  
output  
DATA  
Disabled  
1.2  
0.3  
B-port input,  
A-port  
output  
DATA  
Disabled  
0.2  
0.2  
0.2  
0.3  
0.3  
A-port input,  
B-port  
output  
DATA  
Enabled  
31.2  
30.6  
30.3  
29.5  
28.5  
28.5  
27  
CLK  
Enabled  
28.1  
12.9  
27.2  
12.8  
27  
26.9  
13.2  
27  
B-port input,  
A-port  
output  
DATA  
Enabled  
12.9  
13.2  
13.2  
pF  
CL = 0,  
f = 10 MHz,  
tr = tf = 1 ns  
(1)  
CpdB  
A-port input,  
B-port  
output  
DATA  
Disabled  
0.6  
0.5  
0.5  
0.5  
0.5  
0.6  
CLK  
Disabled  
0.6  
1.2  
0.5  
1.2  
0.5  
1.2  
0.5  
1
0.5  
1
0.6  
1
B-port input,  
A-port  
output  
DATA  
Disabled  
(1) Power dissipation capacitance per transceiver  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
Frequency (Hz)  
Figure 6. Typical ASIP EMI Filter Frequency Response  
200  
150  
100  
50  
60  
80 100  
Junction Temperature, TJ (°C)  
Figure 7. LDO Output Current Derating  
0
20  
40  
–40 –20  
12  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
TYPICAL CHARACTERISTICS  
LOAD REGULATION  
LOAD REGULATION, LIGHT LOADS  
200  
160  
120  
80  
100  
80  
60  
40  
20  
40  
0
TA = 25°C  
0
TA = -40°C  
-20  
-40  
-60  
-80  
-100  
-40  
-80  
-120  
-160  
TA = -40°C  
TA = 85°C  
TA = 25°C  
TA = 85°C  
-200  
0
0
1
2
3
4
5
50  
100  
150  
200  
IOUT (mA)  
IOUT (mA)  
LINE REGULATION  
(IOUT = 5 mA)  
LINE REGULATION  
(IOUT = 150 mA)  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
1
0
TA = -40°C  
TA = -40°C  
-1  
-2  
-3  
-4  
-5  
TA = 25°C  
TA = 25°C  
TA = 85°C  
-1.2  
-1.4  
-1.6  
-1.8  
-2  
TA = 85°C  
-2.2  
-2.4  
3
-6  
3
3.25 3.5 3.75  
4
4.25 4.5 4.75  
VIN (V)  
5
5.25 5.5  
3.25 3.5 3.75  
4
4.25 4.5 4.75  
VIN (V)  
5
5.25 5.5  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
OUTPUT VOLTAGE  
DROPOUT VOLTAGE  
vs  
vs  
TEMPERATURE  
OUTPUT CURRENT  
2
1
250  
200  
150  
100  
50  
TA = 85°C  
TA = 25°C  
0
IOUT = 50 mA  
TA = -40°C  
IOUT = 5 mA  
-1  
-2  
-3  
-4  
IOUT = 150 mA  
0
0
50  
100  
150  
200  
-40  
-15  
10  
35  
60  
85  
IOUT (mA)  
TJ (°C)  
DROPOUT VOLTAGE  
vs  
GROUND PIN CURRENT  
vs  
TEMPERATURE  
OUTPUT CURRENT  
200  
175  
150  
125  
100  
75  
300  
250  
200  
150  
100  
50  
IOUT = 150 mA  
IOUT = 100 mA  
50  
25  
IOUT = 5 mA  
0
0
0
50  
100  
150  
200  
-40  
-15  
10  
35  
60  
85  
IOUT (mA)  
TJ (°C)  
14  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
TYPICAL CHARACTERISTICS (continued)  
GROUND PIN CURRENT  
CURRENT LIMIT  
vs  
vs  
TEMPERATURE (ENABLE)  
INPUT VOLTAGE  
300  
250  
200  
150  
100  
50  
0.40  
0.38  
0.36  
0.34  
0.32  
0.30  
IOUT = 150 mA  
IOUT = 100 mA  
TA = -40°C  
TA = 25°C  
TA = 85°C  
IOUT = 2 mA  
0
3
3.5  
4
4.5  
5
5.5  
-40  
-15  
10  
35  
60  
85  
VIN (V)  
TJ (°C)  
POWER SUPPLY RIPPLE REJECTION  
vs  
OUTPUT SPECTRAL NOISE DENSITY  
(COUT = 1 µF)  
FREQUENCY (VIN - VOUT = 1 V)  
10  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
9
8
7
6
5
4
3
2
1
0
100 mA  
0 mA  
200 mA  
50 mA  
10 mA  
1101k10k100k1M10M
Frequency (Hz)  
Frequency (Hz)  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
LINE TRANSIENT RESPONSE  
(COUT = 1 µF)  
LOAD TRANSIENT RESPONSE  
(COUT = 1 µF, VIN = 3.3 V, IOUT = 0 to 100 mA)  
2.94  
2.93  
2.92  
2.91  
2.9  
5.5  
5.25  
5
3.00  
2.95  
2.90  
2.85  
2.80  
2.75  
2.70  
2.65  
2.60  
2.55  
2.50  
0.18  
0.16  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0.00  
-0.02  
VIN  
VOUT  
4.75  
4.5  
4.25  
4
2.89  
2.88  
2.87  
2.86  
2.85  
VOUT  
3.75  
3.5  
3.25  
3
IOUT  
-0.35  
-0.25  
-0.15  
-0.05  
0.05  
0.15  
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1  
time (ms)  
0
0.1  
time (ms)  
POWER-UP/POWER-DOWN  
(COUT = 1 µF, IOUT = 150 mA)  
TURN-ON RESPONSE  
4
3.5  
3.5  
3
3
2.5  
2
2.5  
2
VIN  
1.5  
1
VIN  
VOUT  
1.5  
1
(COUT = 1 µF)  
0.5  
0
VOUT  
(COUT = 3 µF)  
VOUT  
0.5  
0
-0.5  
-0.5  
-0.001  
0
0.001 0.002 0.003 0.004 0.005 0.006  
time (s)  
-0.1 -0.05  
0
0.05  
0.1 0.15  
0.2 0.25  
0.3  
time (ms)  
16  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
PARAMETER MEASUREMENT INFORMATION  
V
CCI  
V
CCO  
V
CCI  
V
CCO  
DUT  
DUT  
IN  
IN  
OUT  
OUT  
1 MW  
1 MW  
15 pF  
15 pF  
DATA RATE, PULSE DURATION, PROPAGATION DELAY,  
OUTPUT RISE AND FALL TIME MEASUREMENT USING  
AN OPEN-DRAIN DRIVER  
DATA RATE, PULSE DURATION, PROPAGATION DELAY,  
OUTPUT RISE AND FALL TIME MEASUREMENT USING  
A PUSH-PULL DRIVER  
2 × V  
CCO  
S1  
50 kW  
Open  
From Output  
Under Test  
15 pF  
50 kW  
TEST  
/t  
S1  
2 × V  
t
PZL PLZ  
CCO  
LOAD CIRCUIT FOR ENABLE/DISABLE  
TIME MEASUREMENT  
t
/t  
Open  
PHZ PZH  
t
w
V
CCI  
V
CCA  
V
/2  
V
/2  
Output  
Control  
(low-level  
enabling)  
Input  
CCI  
CCI  
V /2  
CCA  
V /2  
CCA  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
0 V  
t
PLZ  
t
PZL  
V
V
CCO  
Output  
Waveform 1  
V
CCI  
V
V
/2  
CCO  
Input  
V
/2  
/2  
V
/2  
CCI  
CCI  
0.1 y V  
CCO  
S1 at 2 × V  
CCO  
OL  
0 V  
(see Note B)  
t
PHZ  
t
t
t
PLH  
PHL  
PZH  
Output  
Waveform 2  
S1 at GND  
V
OH  
0.9 y V  
V
OH  
CCO  
0.9 y V  
CCO  
/2  
Output  
V
CCO  
V
CCO  
/2  
CCO  
(see Note B)  
0.1 y V  
CCO  
0 V  
V
OL  
t
f
t
r
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
A.  
C
L
includes probe and jig capacitance.  
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
H.  
I.  
t
t
t
V
V
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
pd  
PHL  
is the V associated with the input port.  
CC  
CCI  
is the V associated with the output port.  
CCO  
CC  
J. All parameters and waveforms are not applicable to all devices.  
Figure 8. Load Circuit and Voltage WaveformsN  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
PRINCIPLES OF OPERATION  
Applications  
The TXS0206-29 device is a complete application-specific voltage-translator designed to bridge the  
digital-switching compatibility gap and interface logic threshold levels between a micrprocessor with MMC, SD,  
and Memory Stick™ cards. It is intended to be used in a point-to-point topology when interfacing these devices  
that may or may not be operating at different interface voltages.  
Architecture  
The CLKA, CLKB, and CLK-f subsystem interfaces consist of a fully-buffered voltage translator design that has  
its output transistors to source and sink current optimized for drive strength.  
The SDIO lines comprise a semi-buffered auto-direction-sensing based translator architecture (see Figure 9) that  
does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B to A  
ports).  
VCCA  
VCCB O/P  
One-Shot  
One-Shot  
R1  
T1  
R2  
Translator  
T2  
SDIO-DATAx(A)  
SDIO-DATAx(B)  
Bias  
N1  
One-Shot  
T3  
Translator  
One-Shot  
T4  
Figure 9. Architecture of an SDIO Switch-Type Cell  
Each of these bidirectional SDIO channels independently determines the direction of data flow without a  
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is  
how this auto-direction feature is realized.  
The following two key circuits are employed to facilitate the "switch-type" voltage translation function:  
1. Integrated pullup resistors to provide dc-bias and drive capabilities  
2. An N-channel pass-gate transistor topology (with a high RON of ~300 Ω) that ties the A-port to the B-port  
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B  
ports  
18  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
 
TXS0206-29  
www.ti.com  
SCES690 –DECEMBER 2009  
For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.  
The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for  
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance  
from a control signal.  
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,  
helping maintain the data rate through the device.  
During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T1, T3) and its associated  
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase  
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever  
occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during  
the low-to-high transition to speed up the rising-edge signal.  
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated  
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase  
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever  
occurs first.  
To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to  
turn-off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum  
pulse-width number provided in the Timing Requirements section of this data sheet.  
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or  
both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the  
pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change  
value based on whether a Low or a High is being passed through the SDIO lines, as follows:  
•
•
•
RPU1 and RPU2 values are a nominal 40 kΩ when the output is driving a low  
RPU1 and RPU2 values are a nominal 4 kΩ when the output is driving a high  
RPU1 and RPU2 values are a nominal 70 kΩ when the device is disabled via the EN pin or by pulling the either  
VCCA or VCCBO/P to 0 V.  
The reason for using these "smart" pullup resistors is to allow the TXS0206-29 to realize a lower static power  
consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and  
improved simultaneous switching performance.  
Input Driver Requirements  
The continuous dc-current "sinking" capability is determined by the external system-level driver interfaced to the  
SDIO pins. Since the high bandwidth of these bidirectional SDIO circuits necessitates the need for a port to  
quickly change from an input to an output (and vice-vera), they have a modest dc-current "sourcing" capability of  
hundreds of micro-Amps, as determined by the smart pullup resistor values.  
The fall time (tfA, tfB) of a signal depends on the edge rate and output impedance of the external device driving  
the SDIO I/Os, as well as the capacitive loading on these lines.  
Similarly, the tpd and max data rates also depend on the output impedance of the external driver. The values for  
tfA, tfB, tpd, and maximum data rates in the data sheet assume that the output impedance of the external driver is  
less than 50 Ω.  
Output Load Considerations  
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading  
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough  
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity  
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay  
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends  
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is  
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC  
,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the  
capacitance that the TXS0206-29 SDIO output sees, so it is recommended that this lumped-load capacitance be  
considered and kept below 50 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other  
adverse system-level affects.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
TXS0206-29  
SCES690 –DECEMBER 2009  
www.ti.com  
When using the TXS0206-29 device with MMCs, SD, and Memory Stick™ to ensure that a valid receiver input  
voltage high (VIH) is achieved, the value of any pulldown resistors (external or internal to a memory card) must  
not be >10-kΩ value. The impact of adding too heavy a pulldown resistor (i.e. <10-kΩ value) to the data and  
command lines of the TXS0206-29 device and the resulting 4-kΩ pullup & 10-kΩ pulldown voltage divider  
network has a direct impact on the VIH of the signal being sent into the memory card and its associated logic.  
The resulting VIH voltage for the 10-kΩ pulldown resistor value would be:  
VCC × 10 kΩ / (10 kΩ+ 4 kΩ) = 0.714 × VCC  
This is marginally above a valid input high voltage for a 1.8-V signal (i.e., 0.65 × VCC).  
The resulting VIH voltage for 20-kΩ pulldown resistor value would be:  
VCC × 20 kΩ / (20 kΩ + 4 kΩ) = 0.833 × VCC  
Which is above the valid input high voltage for a 1.8-V signal of 0.65 × VCC  
.
.
20  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Dec-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TXS0206-29YFPR  
ACTIVE  
DSBGA  
YFP  
20  
3000 Green (RoHS &  
no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TXS0206-29YFPR  
DSBGA  
YFP  
20  
3000  
180.0  
8.4  
1.65  
2.05  
0.6  
4.0  
8.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
DSBGA YFP 20  
SPQ  
Length (mm) Width (mm) Height (mm)  
220.0 220.0 34.0  
TXS0206-29YFPR  
3000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
www.ti.com/audio  
Data Converters  
DLP® Products  
Automotive  
www.ti.com/automotive  
www.ti.com/communications  
Communications and  
Telecom  
DSP  
dsp.ti.com  
Computers and  
Peripherals  
www.ti.com/computers  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
Consumer Electronics  
Energy  
www.ti.com/consumer-apps  
www.ti.com/energy  
Logic  
Industrial  
www.ti.com/industrial  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Medical  
www.ti.com/medical  
microcontroller.ti.com  
www.ti-rfid.com  
Security  
www.ti.com/security  
Space, Avionics &  
Defense  
www.ti.com/space-avionics-defense  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
Video and Imaging  
Wireless  
www.ti.com/video  
www.ti.com/wireless-apps  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2010, Texas Instruments Incorporated  
厂商 型号 描述 页数 下载

TI

 		TXS0101 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DBVR 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DBVRG4 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DBVT 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DBVTG4 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DCKR 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DCKRG4 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DCKT 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DCKTG4 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

TI

 		TXS0101DRLR 1位双向电压电平转换为漏极开路应用[ 1-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN APPLICATIONS ] 18 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.224395s