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4N55/883B#200

型号：

4N55/883B#200

描述：

NPN输出DC- INPUT光电耦合器\n[ NPN-OUTPUT DC-INPUT OPTOCOUPLER ]

品牌：

ETC[ ETC ]

页数：

12 页

PDF大小：

279 K

下载PDF手册
Hermetically Sealed, Transistor  
Output Optocouplers for Analog  
and Digital Applications  
4N55*  
HCPL-257K  
5962-87679 HCPL-655X  
HCPL-553X 5962-90854  
HCPL-653X HCPL-550X  
Technical Data  
*See matrix for available extensions.  
Features  
• Analog Signal Ground  
Isolation (see Figures 7, 8,  
and 13)  
• Isolated Input Line Receiver  
• Isolated Output Line Driver  
• Logic Ground Isolation  
• Harsh Industrial  
Environments  
• Isolation for Test  
Equipment Systems  
improve the speed up to a  
hundred times that of a conven-  
tional phototransistor  
optocoupler by reducing the  
base-collector capacitance.  
• Dual Marked with Device  
Part Number and DSCC  
Drawing Number  
• Manufactured and Tested on  
a MIL-PRF-38534 Certified  
Line  
• QML-38534, Class H and K  
• Five Hermetically Sealed  
Package Configurations  
• Performance Guaranteed,  
Over -55°C to +125°C  
• High Speed: Typically  
400 kBit/s  
• 9 MHz Bandwidth  
• Open Collector Output  
• 2-18 Volt VCC Range  
• 1500 Vdc Withstand Test  
Voltage  
• High Radiation Immunity  
• 6N135, 6N136, HCPL-2530/  
-2531, Function  
These devices are suitable for  
wide bandwidth analog applica-  
tions, as well as for interfacing  
TTL to LSTTL or CMOS. Current  
Transfer Ratio (CTR) is 9% mini-  
mum at IF = 16 mA. The 18 V VCC  
Description  
These units are single, dual and  
quad channel, hermetically sealed  
optocouplers. The products are  
capable of operation and storage  
over the full military temperature  
range and can be purchased as  
either standard product or with  
full MIL-PRF-38534 Class Level  
H or K testing or from the  
appropriate DSCC Drawing. All  
devices are manufactured and  
tested on a MIL-PRF-38534  
certified line and are included in  
the DSCC Qualified  
Truth Table  
(Positive Logic)  
Input  
On (H)  
Off (L)  
Output  
L
H
Functional Diagram  
Multiple Channel Devices  
Available  
Compatibility  
• Reliability Data  
V
CC  
Manufacturers List QML-38534  
for Hybrid Microcircuits.  
Applications  
• Military and Space  
V
B
• High Reliability Systems  
• Vehicle Command, Control,  
Life Critical Systems  
Each channel contains a GaAsP  
light emitting diode which is  
optically coupled to an integrated  
photon detector. Separate  
V
O
• Line Receivers  
GND  
• Switching Power Supply  
• Voltage Level Shifting  
connections for the photodiodes  
and output transistor collectors  
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.  
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to  
prevent damage and/or degradation which may be induced by ESD.  
2
capability will enable the designer  
to interface any TTL family to  
CMOS. The availability of the  
base lead allows optimized gain/  
bandwidth adjustment in analog  
applications. The shallow depth  
of the IC photodiode provides  
better radiation immunity than  
conventional phototransistor  
couplers.  
Package styles for these parts are  
8 and 16 pin DIP through hole  
(case outlines P and E respec-  
tively), 16 pin DIP flat pack (case  
outline F), and leadless ceramic  
chip carrier (case outline 2).  
Devices may be purchased with a  
variety of lead bend and plating  
options, see Selection Guide  
Table for details. Standard  
listed in this data sheet, absolute  
maximum ratings, recommended  
operating conditions, electrical  
specifications, and performance  
characteristics shown in the  
figures are identical for all parts.  
Occasional exceptions exist due  
to package variations and  
limitations and are as noted.  
Additionally, the same package  
assembly processes and materials  
are used in all devices. These  
similarities give justification for  
the use of data obtained from one  
part to represent other part’s  
performance for die related  
reliability and certain limited  
radiation test results.  
Microcircuit Drawing (SMD)  
parts are available for each  
package and lead style.  
These products are also available  
with the transistor base node  
connected to improve common  
mode noise immunity and ESD  
susceptibility. In addition, higher  
CTR minimums are available by  
special request.  
Because the same functional die  
(emitters and detectors) are used  
for each channel of each device  
Selection Guide–Package Styles and Lead Configuration Options  
Package  
Lead Style  
16 Pin DIP  
8 Pin DIP  
8 Pin DIP  
16 Pin Flat Pack 20 Pad LCCC  
Through Hole Through Hole Through Hole Unformed Leads  
Surface Mount  
Channels  
2
1
2
4
2
Common Channel Wiring  
Agilent Part # & Options  
Commercial  
None  
None  
V
CC GND  
V
CC GND  
None  
4N55*  
HCPL-5500  
HCPL-5501  
HCPL-550K  
Gold Plate  
HCPL-5530  
HCPL-5531  
HCPL-553K  
Gold Plate  
HCPL-6550  
HCPL-6551  
HCPL-655K  
Gold Plate  
HCPL-6530  
HCPL-6531  
HCPL-653K  
Solder Pads  
MIL-PRF-38534, Class H  
MIL-PRF-38534, Class K  
Standard Lead Finish  
Solder Dipped  
4N55/883B  
HCPL-257K  
Gold Plate  
Option #200  
Option #100  
Option #300  
Option #200  
Option #100  
Option #300  
Option #200  
Option #100  
Option #300  
Butt Cut/Gold Plate  
Gull Wing/Soldered  
Class H SMD Part #  
Prescript for all below  
Either Gold or Solder  
Gold Plate  
5962-  
5962-  
5962-  
5962-  
5962-  
8767901EX  
8767901EC  
8767901EA  
8767901UC  
8767901UA  
8767901TA  
5962-  
9085401HPX  
9085401HPC  
9085401HPA  
9085401HYC  
9085401HYA  
9085401HXA  
5962-  
8767902PX  
8767902PC  
8767902PA  
8767902YC  
8767902YA  
8767902XA  
5962-  
8767904FX  
8767904FC  
87679032X  
Solder Dipped  
87679032A  
Butt Cut/Gold Plate  
Butt Cut/Soldered  
Gull Wing/Soldered  
Prescript for all below  
Either Gold or Solder  
Gold Plate  
5962-  
5962-  
8767905KEX 9085401KPX  
8767905KEC 9085401KPC  
8767905KEA  
8767905KUC 9085401KYC  
8767905KUA 9085401KYA  
8767905KTA 9085401KXA 8767906KXA  
8767906KPX  
8767906KPC  
8767906KPA  
8767906KYC  
8767906KYA  
8767908KFX  
8767908KFC  
8767907K2X  
Solder Dipped  
9085401KPA  
8767907K2A  
Butt Cut/Gold Plate  
Butt Cut/Soldered  
Gull Wing/Soldered  
*JEDEC registered part.  
3
8 Pin Ceramic DIP Single  
Channel Schematic  
I
I
I
CC  
8
7
6
I
F
2
+
V
V
V
CC  
B
ANODE  
B
V
F
O
–
3
O
CATHODE  
5
GND  
Note base pin 7.  
Functional Diagrams  
16 Pin DIP  
Through Hole  
2 Channels  
8 Pin DIP  
Through Hole  
1 Channel  
8 Pin DIP  
Through Hole  
2 Channels  
16 Pin Flat Pack  
Unformed Leads  
4 Channels  
20 Pad LCCC  
Surface Mount  
2 Channels  
15 14  
1
V
16  
1
16  
B1  
V
V
B2  
CC2  
1
V
8
1
V
8
CC  
CC  
19  
20  
13  
12  
2
3
4
V
15  
14  
13  
2
3
4
V
15  
14  
13  
V
CC1  
CC  
O2  
V
V
O1  
O2  
2
3
4
V
B
7
6
5
2
3
4
7
6
5
GND  
2
V
V
V
V
V
O1  
O1  
O2  
O3  
O4  
V
OUT  
V
CC1  
2
3
10  
9
V
O1  
GND  
V
B1  
GND  
1
GND  
GND  
5
12  
5
12  
V
B2  
7
8
V
6
7
8
11  
10  
9
6
7
8
11  
10  
9
CC2  
GND  
GND  
V
O2  
Note: 8 pin DIP and flat pack devices have common VCC and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages  
have isolated channels with separate VCC and ground connections.  
Outline Drawings  
16 Pin DIP Through Hole, 2 Channels  
20.06 (0.790)  
20.83 (0.820)  
8.13 (0.320)  
MAX.  
0.89 (0.035)  
1.65 (0.065)  
4.45 (0.175)  
MAX.  
0.51 (0.020)  
MIN.  
3.81 (0.150)  
MIN.  
0.20 (0.008)  
0.33 (0.013)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
4
Leaded Device Marking  
Leadless Device Marking  
Agilent DESIGNATOR  
A QYYWWZ  
XXXXXX  
XXXXXXX  
XXX XXX  
50434  
COMPLIANCE INDICATOR,*  
DATE CODE, SUFFIX (IF NEEDED)  
Agilent DESIGNATOR  
Agilent P/N  
PIN ONE/  
ESD IDENT  
COUNTRY OF MFR.  
A QYYWWZ  
XXXXXX  
XXXX  
XXXXXX  
XXX 50434  
COMPLIANCE INDICATOR,*  
DATE CODE, SUFFIX (IF NEEDED)  
DSCC SMD*  
DSCC SMD*  
Agilent CAGE CODE*  
Agilent P/N  
DSCC SMD*  
DSCC SMD*  
PIN ONE/  
COUNTRY OF MFR.  
Agilent CAGE CODE*  
ESD IDENT  
* QUALIFIED PARTS ONLY  
* QUALIFIED PARTS ONLY  
Outline Drawings  
16 Pin Flat Pack, 4 Channels  
7.24 (0.285)  
6.99 (0.275)  
2.29 (0.090)  
MAX.  
1.27 (0.050)  
REF.  
11.13 (0.438)  
10.72 (0.422)  
0.46 (0.018)  
0.36 (0.014)  
8.13 (0.320)  
MAX.  
2.85 (0.112)  
MAX.  
0.88 (0.0345)  
MIN.  
0.31 (0.012)  
0.23 (0.009)  
0.89 (0.035)  
0.69 (0.027)  
5.23  
(0.206)  
MAX.  
9.02 (0.355)  
8.76 (0.345)  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
20 Terminal LCCC Surface Mount, 2  
Channels  
8 Pin DIP Through Hole, 1 and 2  
Channel  
8.70 (0.342)  
9.10 (0.358)  
9.40 (0.370)  
9.91 (0.390)  
0.76 (0.030)  
1.27 (0.050)  
8.13 (0.320)  
MAX.  
4.95 (0.195)  
5.21 (0.205)  
7.16 (0.282)  
7.57 (0.298)  
1.78 (0.070)  
2.03 (0.080)  
1.02 (0.040) (3 PLCS)  
1.14 (0.045)  
1.40 (0.055)  
4.32 (0.170)  
MAX.  
8.70 (0.342)  
9.10 (0.358)  
4.95 (0.195)  
TERMINAL 1 IDENTIFIER  
2.16 (0.085)  
5.21 (0.205)  
0.51 (0.020)  
MIN.  
3.81 (0.150)  
MIN.  
0.20 (0.008)  
0.33 (0.013)  
METALIZED  
CASTILLATIONS (20 PLCS)  
1.78 (0.070)  
2.03 (0.080)  
0.64  
(0.025)  
(20 PLCS)  
0.51 (0.020)  
7.36 (0.290)  
7.87 (0.310)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
1.52 (0.060)  
2.03 (0.080)  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
SOLDER THICKNESS 0.127 (0.005) MAX.  
5
Hermetic Optocoupler Options  
Option  
Description  
100  
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This  
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below  
for details).  
4.32 (0.170)  
MAX.  
0.51 (0.020)  
1.14 (0.045)  
MIN.  
1.40 (0.055)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
4.32 (0.170)  
MAX.  
0.51 (0.020)  
MIN.  
1.14 (0.045)  
1.40 (0.055)  
0.20 (0.008)  
0.33 (0.013)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
7.36 (0.290)  
7.87 (0.310)  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
200  
300  
Lead finish is solder dipped rather than gold plated. This option is available on commercial  
and hi-rel product in 8 and 16 pin DIP. DSCC drawing part numbers contain provisions for  
lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a  
standard feature.  
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This  
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below  
for details). This option has solder dipped leads.  
4.57 (0.180)  
MAX.  
0.51 (0.020)  
1.40 (0.055)  
MIN.  
1.65 (0.065)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
4.57 (0.180)  
MAX.  
4.57 (0.180)  
MAX.  
0.20 (0.008)  
0.33 (0.013)  
0.51 (0.020)  
MIN.  
5° MAX.  
1.40 (0.055)  
1.65 (0.065)  
9.65 (0.380)  
9.91 (0.390)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).  
6
Absolute Maximum Ratings  
(No derating required up to +125°C)  
Storage Temperature Range, TS ...................................-65°C to +150°C  
Operating Temperature, TA ..........................................-55°C to +125°C  
Case Temperature, TC ................................................................+170°C  
Junction Temperature, T ...........................................................+175°C  
J
Lead Solder Temperature ............................................... 260°C for 10 s  
Peak Forward Input Current, (each channel,  
≤ 1 ms duration), IF PK.............................................................. 40 mA  
Average Input Forward Current, IF AVG (each channel) ................ 20 mA  
Reverse Input Voltage, BVR ...................... See Electrical Characteristics  
Average Output Current, IO (each channel) ................................... 8 mA  
Peak Output Current, IO (each channel) ...................................... 16 mA  
Supply Voltage, VCC ......................................................... -0.5 V to 20 V  
Output Voltage, VO (each channel)................................... -0.5 V to 20 V  
Input Power Dissipation (each channel) ..................................... 36 mW  
Output Power Dissipation (each channel) .................................. 50 mW  
Package Power Dissipation, PD (each channel) ........................ 200 mW  
Single Channel 8 Pin, Dual Channel 16 Pin,  
and LCCC Only  
Emitter Base Reverse Voltage, VEBO............................................... 3.0 V  
Base Current, IB (each channel) .................................................... 5 mA  
ESD Classification  
(MIL-STD-883, Method 3015)  
4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and  
HCPL-6530/31/3K ............................................................... (∆), Class 1  
HCPL-5530/31/3K, HCPL-6550/51/5K ............................ (Dot), Class 3  
Recommended Operating Conditions  
Parameter  
Symbol  
IFL  
Min.  
Max.  
250  
20  
Units  
µA  
mA  
V
Input Current, Low Level  
Input Current, High Level  
Supply Voltage, Output  
IFH  
VCC  
12  
2
18  
7
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)  
Limits  
Group A[12]  
Sub-groups Min. Typ.** Max. Units Fig. Note  
Parameter  
Symbol  
Test Conditions  
Current Transfer  
Ration  
CTR* VO = 0.4 V, IF = 16 mA,  
VCC = 4.5 V  
1, 2, 3  
9
20  
%
2, 3 1, 2,  
10  
Logic High Out-  
put Current  
IOH  
IOLeak  
II-O*  
VF*  
IF = 0,  
IF (other channels) = 20 mA,  
VO = VCC = 18 V  
IF = 250 µA,  
IF (other channels) = 20 mA,  
VO = VCC = 18 V  
1, 2, 3  
5
100  
250  
1.0  
µA  
4
1
Output Leakage  
Current  
*
1, 2, 3  
1
30  
µA  
µA  
4
1
Input-Output  
Insulation Leak-  
age Current  
Input Forward  
Voltage  
VI-O = 1500 Vdc,  
3, 9  
RH = 45%  
TA = 25°C, t = 5 s  
IF = 20 mA  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1.55  
1.8  
1.9  
V
V
1
1, 14  
1, 13  
1, 14  
1, 13  
1
Reverse Break-  
down Voltage  
BVR* IR = 10 µA  
5
3
Logic  
Single  
ICCH  
*
VCC = 18 V, IF = 0 mA  
0.1  
0.2  
0.4  
35  
10  
20  
µA  
High  
Channel  
Supply  
Current  
Dual  
Channel  
VCC = 18 V, IF = 0 mA  
(all channels)  
VCC = 18 V, IF = 0 mA  
(all channels)  
1, 4  
1
Quad  
Channel  
40  
Logic  
Single  
ICCL*  
VCC = 18 V, IF = 20 mA  
1, 2, 3  
200  
400  
800  
6.0  
µA  
µs  
5
1
Low  
Channel  
Supply  
Current  
Dual  
Channel  
VCC = 18 V,  
IF1 = IF2 = 20 mA  
70  
1, 4  
1
Quad  
Channel  
Propagation  
Delay Time to  
Logic High  
at Output  
VCC = 18 V, IF1 = IF2  
IF3 = IF4 = 20 mA  
RL = 8.2 kΩ,  
CL = 50 pF,  
IF = 16 mA,  
VCC = 5 V  
=
140  
1.0  
tPLH*  
9, 10, 11  
6, 9 1, 6  
Propagation  
Delay Time to  
Logic Low at  
Output  
tPHL*  
0.4  
2.0  
*For JEDEC registered parts.  
**All typical values are at VCC = 5 V, TA = 25°C.  
8
Typical Characteristics, TA = 25°C, VCC = 5 V  
Parameter  
Input Capacitance  
Input Diode Temperature  
Coefficient  
Symbol  
CIN  
∆VF  
Typ.  
60  
-1.5  
Units  
pF  
mV/°C  
Test Conditions  
VF = 0 V, f = 1 MHz  
IF = 20 mA  
Fig. Note  
1
1
∆TA  
Resistance (Input-Output)  
Capacitance (Input-Output)  
Transistor DC Current Gain  
Small Signal Current  
Transfer Ratio  
RI-O  
CI-O  
hFE  
∆IO  
1012  
1.0  
250  
21  
Ω
pF  
-
V
I-O 500 V  
3
1, 11  
1
f = 1 MHz  
VO = 5 V, IO = 3 mA  
VCC = 5 V, VO = 2 V  
%
7
1
∆IF  
Common Mode Transient  
Immunity at Logic High  
Level Output  
Common Mode Transient  
Immunity at Logic Low  
Level Output  
|CMH|  
1000  
-1000  
9
V/µs  
V/µs  
MHz  
IF = 0 mA, RL = 8.2 kΩ,  
VO (min) = 2.0 V  
VCM = 10 VP-P  
IF = 16 mA, RL = 8.2 kΩ,  
VO (max) = 0.8 V  
VCM = 10 VP-P  
10  
1, 7  
|CML|  
BW  
10  
8
1, 7  
8
Bandwidth  
Multi-Channel Product Only  
Input-Input Insulation  
Leakage Current  
Resistance (Input-Input)  
Capacitance (Input-Input)  
II-I  
1
pA  
Relative Humidity = 45%  
5, 9  
V = 500 V, t = 5 s  
I-I  
RI-I  
CI-I  
1012  
0.8  
Ω
V = 500 V  
5
5
I-I  
pF  
f = 1 MHz  
Notes:  
1. Each channel of a multi-channel device.  
2. Current Transfer Ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%.  
CTR is known to degrade slightly over the unit’s lifetime as a function of input current, temperature, signal duty cycle, and system  
on time. Refer to Application Note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25%  
guardband for CTR degradation.  
3. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output  
leads or terminals shorted together.  
4. The 4N55, 4N55/883B, HCPL-257K, HCPL-6530, HCPL-6531, and HCPL-653K dual channel parts function as two independent  
single channel units. Use the single channel parameter limits. IF = 0 mA for channel under test and IF = 20 mA for other  
channels.  
5. Measured between adjacent input pairs shorted together for each multichannel device.  
6. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading  
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the  
1.5 V point on the trailing edge of the output pulse.  
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state  
(VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the  
logic high state (VO > 2.0 V).  
8. Bandwidth is the frequency at which the ac output voltage is 3 dB below the low frequency asymptote. For the HCPL-5530 the  
typical bandwidth is 2 MHz.  
9. This is a momentary withstand test, not an operating condition.  
10. Higher CTR minimums are available to support special applications.  
11. Measured between each input pair shorted together and all output connections for that channel shorted together.  
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and  
-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).  
13. Not required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types.  
14. Required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types only.  
9
Figure 1. Input Diode Forward  
Current vs. Forward Voltage.  
Figure 2. DC and Pulsed Transfer  
Characteristic.  
Figure 3. Normalized Current  
Transfer Ratio vs. Input Diode  
Forward Current.  
100  
I
I
= 250 µA,  
(OTHER CHANNELS) = 20 mA  
F
F
I
I
= 0 µA,  
10  
1
F
F
(OTHER CHANNELS) = 20 mA  
I
= I (OTHER CHANNELS)  
F
= 0 mA  
F
0.1  
0.01  
V
= V = 18 V  
O
CC  
0.001  
-60 -40 -20  
0
20 40 60 80 100 120 140  
T
– TEMPERATURE – °C  
A
Figure 4. Logic High Output Current  
vs. Temperature.  
Figure 5. Logic Low Supply Current  
vs. Input Diode Forward Current.  
Figure 6. Propagation Delay vs.  
Temperature.  
Figure 7. Normalized Small Signal  
Current Transfer Ratio vs. Quiescent  
Input Current.  
10  
+12 V  
D.U.T.  
+12 V  
1.2 kΩ  
9.1 kΩ  
V
CC  
0.01 µF 0.01 µF  
2.1 kΩ  
100 Ω  
Q
3
0.1 µF  
0.1 µF  
V
O
47 µF  
Q
V
(1 M  
2
O
Q
1
Ω, 12 pF  
V
IN  
V
B
TEST INPUT)  
15 kΩ  
470  
Ω
100 Ω  
R
F
51 Ω  
1 kΩ  
GND  
SINGLE CHANNEL TESTING,  
INDEPENDENT V DEVICES  
22 Ω  
CC  
1N4150  
TRIM FOR UNITY GAIN  
Q , Q , Q : 2N3904  
TYPICAL LINEARITY = +3 % AT V = 1 V  
IN  
TYPICAL SNR = 50 dB  
1
2
3
P-P  
TYPICAL R = 375 Ω  
F
TYPICAL V dc = 3.8 V  
O
TYPICAL I = 9 mA  
F
+15  
+10  
T
= 25 °C  
A
D.U.T.  
+5 V  
+15 V  
INDEPENDENT  
DEVICES  
+5  
0
V
CC  
V
100 Ω  
CC  
SET I  
20 kΩ  
F
V
O
2N3053  
1.6 Vdc  
0.25 V  
AC INPUT  
-5  
COMMON V  
DEVICES  
0.1 µF  
CC  
ac  
P-P  
-10  
560 Ω  
100 Ω  
GND  
-15  
-20  
COMMON  
DEVICES  
V
CC  
0.1  
1.0  
10  
100  
f – FREQUENCY – MHz  
Figure 8. Frequency Response.  
PULSE GEN.  
Z
t
= 50 Ω  
= 5 ns  
O
r
D.U.T.  
I
+5 V  
F
V
CC  
R
L
V
O
I
MONITOR  
F
100 Ω  
C * = 50 pF  
L
GND  
SINGLE CHANNEL  
OR COMMON V DEVICES  
CC  
10 % DUTY CYCLE  
1/f < 100 µs  
NOTES:  
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.  
L
BASE LEAD NOT CONNECTED.  
Figure 9. Switching Test Circuit.*  
*JEDEC Registered Data.  
11  
I
F
B
A
D.U.T.  
+5 V  
V
CC  
R
L
R
M
V
O
V
FF  
GND  
SINGLE CHANNEL OR  
COMMON V  
DEVICES  
CC  
V
CM  
+
–
PULSE GEN.  
NOTE: BASE LEAD NOT CONNECTED.  
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.  
V
5 V  
CC  
Logic Family  
Device No.  
VCC  
LSTTL  
54LS14  
5 V  
CMOS  
CD40106BM  
220 Ω  
5 V  
15 V  
R
L
D.U.T.  
RL 5% Tolerance 18 kΩ* 8.2 kΩ 22 kΩ  
V
CC  
*The equivalent output load resistance is affected by the  
LSTTL input current and is approximately 8.2 kΩ.  
TTL  
This is a worst case design which takes into account 25%  
degradation of CTR. See App. Note 1002 to assess actual  
degradation and lifetime.  
LOGIC GATE  
0.01 µF  
GND  
EACH CHANNEL  
Figure 11. Recommended Logic Interface.  
V
CC  
V
D.U.T.*  
OC  
V
CC  
(EACH INPUT)  
–
0.1 µF  
+
V
O
V
IN  
(EACH OUTPUT)  
GND  
NOMINAL CONDITIONS  
PER CHANNEL: I = 20 mA  
F
I
I
= 4 mA  
O
= 30 µA  
CC  
NOTE: BASE LEAD NOT CONNECTED.  
= +125 °C  
T
A
Figure 12. Operating Circuit for Burn-In and Steady State  
Life Tests. All Channels Tested Simultaneously.  
OFFSET ADJUST  
R
3
2
1
2
HCPL-5530  
5 kΩ  
I
F
–
1
220 Ω  
U
8
7
6
5
1
2
3
4
1
+
+
I
I
–
U
3
+
C
C
V
I
F
IN  
2
2
R
1 kΩ  
4
–
5 kΩ GAIN ADJUST  
U
2
–
+
50 kΩ  
R
-15 V  
–
5
R
R
2
2.7 kΩ  
1
U
+
V
OUT  
4
2.7 kΩ  
U
I
, U , U , U , LM307  
1
2
3
4
2
n
1
I
I
F
F
1
I
= K  
C
1
2
6 mA  
CC  
1
1
´
n
2
I
I
F
2
I
= K  
-15 V  
C
2
F
2
´
Figure 13. Isolation Amplifier Application Circuit.  
Description  
The schematic uses a dual-  
Performance of Circuit  
• 1% linearity for 10 V peak-to-  
peak dynamic range  
• Gain drift: -0.03%/°C  
• Offset Drift: ± 1 mV/°C  
• 25 kHz bandwidth (limited by  
Op-Amps U1, U2)  
MIL-PRF-38534 Class H,  
Class K, and DSCC SMD  
Test Program  
Agilent’s Hi-Rel Optocouplers are  
in compliance with MIL-PRF-  
38534 Classes H and K. Class H  
and Class K devices are also in  
compliance with DSCC drawings  
5962-87679, and 5962-90854.  
channel, high-speed optocoupler  
(HCPL-5530) to function as a  
servo type dc isolation amplifier.  
This circuit operates on the  
principle that two optocouplers  
will track each other if their gain  
changes by the same amount over  
a specific operating region.  
Testing consists of 100% screen-  
ing and quality conformance  
inspection to MIL-PRF-38534.  
www.semiconductor.agilent.com  
Data subject to change.  
Copyright © 2000 Agilent Technologies  
Obsoletes 5966-4874E  
5968-9409E (4/00)  
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