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WV3DG7266V7D1-SF

型号：

WV3DG7266V7D1-SF

品牌：

WEDC[ WHITE ELECTRONIC DESIGNS CORPORATION ]

页数：

8 页

PDF大小：

173 K

下载PDF手册
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY*  
512MB – 2x32Mx72 SDRAM, UNBUFFERED, w/PLL  
FEATURES  
DESCRIPTION  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
PC100 and PC133  
The WV3DG7266V is a 2x32Mx72 synchronous DRAM  
module which consists of nine stacked 64Mx8 with 4 banks  
SDRAM components in TSOP II package, and one 2Kb  
EEPROM for Serial Presence Detect which are mounted  
on a 144 pin SO-DIMM multilayer FR4 Substrate.  
Burst Mode Operation  
Auto and Self Refresh capability  
LVTTL compatible inputs and outputs  
Serial Presence Detect with EEPROM  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
Fully synchronous: All signals are registered on the  
positive edge of the system clock  
NOTE: Consult factory for availability of:  
• RoHS compliant products  
ꢀ
Programmable Burst Lengths: 1, 2, 4, 8 or Full  
Page  
• Vendor source control options  
• Industrial temperature option  
ꢀ
ꢀ
ꢀ
3.3V 0.3V Power Supply  
Dual Rank  
144 Pin SO-DIMM JEDEC  
• PCB: 31.75mm (1.25”)  
PIN NAMES  
Address Input (Multiplexed)  
Select Bank  
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)  
A0 – A12  
BA0-1  
PINOUT  
DQ0-63  
CLK0, CLK1 Clock Input  
CB0-7  
CKE0  
Data Input/Output  
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN FRONT PIN BACK  
1
3
5
7
9
11  
13  
15  
17  
19  
21  
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
VSS  
2
4
6
8
10  
12  
14  
16  
18  
20  
22  
VSS  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
DQ13  
DQ14  
DQ15  
VSS  
CB0  
CB1  
CLK0  
VCC  
RAS#  
WE#  
CS0#  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
DQ45  
DQ46  
DQ47 101  
VSS  
CB4  
CB5  
CKE0 109  
VCC 111  
CAS# 113  
97  
99  
DQ22  
DQ23 100 DQ55  
VCC  
A6  
A8  
VSS  
A9  
A10  
VCC  
98  
DQ54  
Check Bit (Data-In/Data-Out)  
Clock Enable Input  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
DQ36  
DQ37  
DQ38  
DQ39  
VSS  
102  
104  
106  
108  
110  
112  
114  
VCC  
A7  
CS0#, CS1# Chip Select Input  
103  
105  
107  
RAS#  
CAS#  
WE#  
DQM0-7  
VCC  
VSS  
SDA  
SCL  
Row Address Strobe  
Column Address Strobe  
#Write Enable  
DQM  
Power Supply (3.3V)  
Ground  
Serial Data I/O  
Serial Clock  
Do Not Use  
BA0  
VSS  
BA1  
A11  
VCC  
CKE1 115 DQM2 116 DQM6  
A12  
NC  
117 DQM3 118 DQM7  
119 VSS 120 VSS  
23 DQM0 24 DQM4 71 CS1#* 72  
DNU  
NC  
25 DQM1 26 DQM5 73  
NC  
VSS  
CB2  
CB3  
VCC  
DQ16  
DQ17  
DQ18  
DQ19  
VSS  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
CLK1 121 DQ24 122 DQ56  
No Connect  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
VCC  
A0  
A1  
A2  
VSS  
DQ8  
DQ9  
DQ10  
DQ11  
VCC  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
VCC  
A3  
A4  
A5  
VSS  
DQ40  
DQ41  
DQ42  
DQ43  
VCC  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
VSS  
CB6  
CB7  
VCC  
123 DQ25 124 DQ57  
125 DQ26 126 DQ58  
127 DQ27 128 DQ59  
* These pins are not used in this module  
** These pins should be NC in the system which does  
not support SPD.  
129  
VCC  
130  
VCC  
DQ48 131 DQ28 132 DQ60  
DQ49 133 DQ29 134 DQ61  
DQ50 135 DQ30 136 DQ62  
DQ51 137 DQ31 138 DQ63  
VSS  
DQ52 141  
DQ53 143  
139  
VSS  
SDA  
VCC  
140  
142  
144  
VSS  
SCL  
VCC  
DQ20  
DQ21  
DQ12  
DQ44  
August 2005  
Rev. 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
FUNCTIONAL BLOCK DIAGRAM  
CS1#  
CS0#  
DQM0  
DQM4  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
I/O 2  
I/O 2  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
I/O 4  
I/O 4  
I/O 4  
I/O 4  
I/O 5  
I/O 5  
I/O 5  
I/O 5  
I/O 6  
I/O 6  
I/O 6  
I/O 6  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQM1  
DQM5  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQ8  
DQ9  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 2  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
I/O 4  
I/O 4  
I/O 4  
I/O 4  
I/O 5  
I/O 5  
I/O 5  
I/O 5  
I/O 6  
I/O 6  
I/O 6  
I/O 6  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQM6  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
I/O 2  
I/O 2  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
I/O 4  
I/O 4  
I/O 4  
I/O 4  
I/O 5  
I/O 5  
I/O 5  
I/O 5  
I/O 6  
I/O 6  
I/O 6  
I/O 6  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQM2  
DQM7  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
I/O 2  
I/O 2  
I/O 2  
I/O 2  
I/O 3  
I/O 3  
I/O 3  
I/O 3  
I/O 4  
I/O 4  
I/O 4  
I/O 4  
I/O 5  
I/O 5  
I/O 5  
I/O 5  
I/O 6  
I/O 6  
I/O 6  
I/O 6  
I/O 7  
I/O 7  
I/O 7  
I/O 7  
DQM3  
10Ω  
DQM CS#  
I/O 0  
DQM CS#  
I/O 0  
PLL CLOCK  
DRIVER  
CLK0  
CK0  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
12pF  
I/O 1  
I/O 1  
I/O 2  
I/O 2  
10pF  
I/O 3  
I/O 3  
I/O 4  
I/O 4  
I/O 5  
I/O 5  
I/O 6  
I/O 6  
10Ω  
I/O 7  
I/O 7  
CLK1  
10pF  
SDA  
A0-A12  
A0-A12: SDRAM  
BA0-BA1  
RAS#  
CAS#  
CKE0  
WE#  
BA0-BA1: SDRAM  
RAS#: SDRAM  
CAS#: SDRAM  
CKE0: SDRAM  
WE#: SDRAM  
CS0#: SDRAM  
CS1#: SDRAM  
Serial PD  
SCL  
A0 A1 A2  
CS0#  
CS1#  
VCC  
SDRAM  
10Ω  
DQn  
Every DQPin of SDRAM  
VSS  
SDRAM  
Two 0.1uf capacitors per each SDRAM  
August 2005  
Rev. 1  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
Units  
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
VIN, VOUT  
VCC, VCCQ  
TSTG  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
V
V
-55 ~ +150  
°C  
W
Power Dissipation  
PD  
18  
50  
Short Circuit Current  
IOS  
mA  
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C  
Parameter  
Symbol  
VCC  
VIH  
Min  
3.0  
2.0  
-0.3  
2.4  
—
Typ  
3.3  
3.0  
—
Max  
3.6  
Unit  
V
Note  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
VCCQ +0.3  
0.8  
V
1
2
VIL  
V
VOH  
VOL  
ILI  
—
—
V
IOH= -2mA  
IOL= -2mA  
3
—
0.4  
V
-10  
—
10  
µA  
Notes:  
1.  
2.  
V
V
IH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.  
IL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.  
3. Any input 0V ≤ VIN ≤ VCCQ  
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.  
CAPACITANCE  
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV  
Parameter  
Symbol  
CIN1  
Max  
95  
95  
95  
18  
50  
10  
95  
16  
16  
Unit  
Input Capacitance (A0-A12)  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (RAS#,CAS#,WE#)  
Input Capacitance (CKE0)  
CIN2  
CIN3  
Input Capacitance (CLK0)  
CIN4  
Input Capacitance (CS0#, CS1#)  
Input Capacitance (DQM0-DQM7)  
Input Capacitance (BA0-BA1)  
Data Input/Output Capacitance (DQ0-DQ63)  
Data Input/Output Capacitance (CB0-7)  
CIN5  
CIN6  
CIN7  
COUT  
COUT1  
August 2005  
Rev. 1  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
OPERATING CURRENT CHARACTERISTICS  
(VCC = 3.3V, TA = 0°C ≤ +70°C)  
Value  
75  
Parameter  
Symbol  
Conditions  
Units  
mA  
Note  
7
10  
Burst Length = 1  
RC ≥ tRC (min)  
IO = 0mA  
Operating current  
(One bank active)  
ICC1  
t
1170  
1080  
1080  
1
3
ICC2P  
CKE ≤ VIL(max), tCC = 10ns  
36  
36  
Precharge standby current in  
power-down mode  
mA  
ICC2PS  
CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS# ≥ VIH(min), tcc =10ns  
Icc2N  
360  
180  
Input signals are charged one time during 20ns  
Precharge standby current in  
non power-down mode  
mA  
mA  
3
3
CKE ≥ VIH(min), CLK ≥VIL(max), tCC = ∞  
Input signals are stable  
ICC2NS  
ICC3P  
CKE ≥ VIL(max), tCC = 10ns  
108  
108  
Active standby current in  
power-down mode  
ICC3PS  
CKE & CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS# ≥ VIH(min), tcc = 10ns Input  
ICC3N  
540  
450  
mA  
mA  
3
3
signals are changed one time during 20ns  
Active Standby Current in  
Non-Power Down Mode  
CKE ≤ VIH(min), CLK ≤ VIL(max), tcc = ∞  
Input signals are stable  
ICC3NS  
Io = mA  
Page burst  
Operating Current (Burst mode)  
ICC4  
1260  
2250  
1260  
1170  
1980  
mA  
1
4 Banks activated  
tCCD = 2CLK  
Refresh Current  
ICC5  
ICC6  
t
RC ≥ tRC(min)  
2070  
54  
mA  
mA  
2
3
Self Refresh Current  
CKE ≤ 0.2V  
Notes:  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. Measured with 1 PLL & 3 Drive ICs.  
August 2005  
Rev. 1  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
AC OPERATING TEST CONDITIONS  
VCC = 3.3v, 0°C - 70°C  
Parameter  
Value  
Unit  
V
AC input levels (VIH/VIL)  
2.4/0.4  
1.4  
Input timing measurement reference level  
Input rise and fall time  
V
tR/tF = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
DC OUTPUT LOAD CIRCUIT  
AC OUTPUT LOAD CIRCUIT  
Vtt = 1.4V  
50Ω  
3.3V  
1200Ω  
V
V
OH (DC) = 2.4V, IOH = -2mA  
OL (DC) = 0.4V, IOL = 2mA  
Z0 = 50Ω  
Output  
Output  
50pF  
50pF  
870Ω  
OPERATING AC PARAMETER  
Parameter  
Symbol  
Version  
Unit  
Note  
7
75  
15  
20  
20  
10  
20  
20  
20  
50  
Row active to row active delay  
RAS# to CAS# delay  
Row precharge time  
Row active time  
tRRD(min)  
tRCD(min)  
tRP(min)  
tRAS(min)  
tRAS(max)  
tRC(min)  
tRDL(min)  
tDAL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
15  
15  
15  
45  
ns  
ns  
ns  
ns  
us  
ns  
CLK  
—
CLK  
CLK  
CLK  
ea  
1
1
1
1
45  
100  
65  
2
Row cycle time  
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
Col. address to col. address delay  
Number of valid output data  
60  
70  
1
2
2 CLK + tRP  
1
1
1
2
1
2
2
3
4
CAS latency=3  
CAS latency=2  
Notes:  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
August 2005  
Rev. 1  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
OPERATING AC PARAMETERS  
7
75  
10  
Parameter  
Symbol  
Unit  
ns  
Note  
1
Min  
7.5  
7.5  
Max  
Min  
7.5  
10  
Max  
Min  
10  
Max  
CAS latency=3  
CAS latency=2  
CAS latency=3  
CAS latency=2  
CAS latency=3  
CAS latency=2  
CLK cycle time  
tCC  
1000  
1000  
1000  
10  
5.4  
5.4  
5.4  
6
6
6
CLK to valid output delay  
Output data hold time  
tSAC  
ns  
1, 2  
2
3
3
3
3
3
3
2
1
1
tOH  
ns  
3
3
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
2.5  
2.5  
1.5  
0.8  
1
2.5  
2.5  
1.5  
0.8  
1
ns  
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
tSS  
tSH  
tSLZ  
Input hold time  
CLK to output in Low-Z  
CAS latency=3  
CAS latency=2  
5.4  
5.4  
5.4  
6
6
6
CLK to outpu in Hi-Z  
tSHZ  
Notes :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
August 2005  
Rev. 1  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
PACKAGE DIMENSIONS FOR D1  
Ordering Information  
WV3DG7266V10D1  
WV3DG7266V7D1  
WV3DG7266V75D1  
NOTES:  
Speed  
100MHz  
133MHz  
133MHz  
CAS Latency  
CL=2  
Height*  
31.75 (1.250”)  
31.75 (1.250”)  
31.75 (1.250”)  
CL=2  
CL=3  
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)  
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is  
shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult  
factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR D1  
67.56 (2.66)  
63.60 (2.50)  
6.35 (0.250) Max  
4.00 0.10  
(0.16 0.039)  
2 - R 2.00  
(0.078) Min  
1
59  
61  
143  
32.80 (1.29)  
4.60 (0.18)  
3.30  
(0.13)  
23.20  
(0.91)  
1.00 0.10  
(0.04 0.0039)  
2 - 1.80  
(0.07)  
2.10 (0.083)  
2.50  
(0.10)  
3.80  
(0.15)  
2
144  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).  
August 2005  
Rev. 1  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3DG7266V-D1  
White Electronic Designs  
PRELIMINARY  
Document Title  
512MB – 2x32Mx72 SDRAM UNBUFFERED, w/PLL  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Rev 1  
Created  
4-05  
8-05  
Preliminary  
Preliminary  
1.1 Update functional block diagram  
August 2005  
Rev. 1  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
厂商 型号 描述 页数 下载

WEDC

 		WV3DG64127V-D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V10D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V75D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V75D2F [ DRAM, ] 8 页

WEDC

 		WV3DG64127V75D2G [ 暂无描述 ] 8 页

WEDC

 		WV3DG64127V7D2 1GB - 2x64Mx64 ， SDRAM UNBUFFERED[ 1GB - 2x64Mx64, SDRAM UNBUFFERED ] 8 页

WEDC

 		WV3DG64127V7D2F [ DRAM, ] 8 页

WEDC

 		WV3DG64127V7D2G [ 暂无描述 ] 8 页

WEDC

 		WV3DG72256V-AD2 2GB - 2x128Mx72 SDRAM ，注册[ 2GB - 2x128Mx72 SDRAM, REGISTERED ] 9 页

MICROSEMI

 		WV3DG72256V10AD2MG [ Synchronous DRAM Module, 256MX72, 5.4ns, CMOS, ROHS COMPLIANT, DIMM-168 ] 9 页

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