P R E L I M I N A R Y
P R O D U C T B R I E F
Infineon’s EasyPort™ is a comprehensive broad-
band communication processor family. Based on
a powerful 64-bit MIPS CPU core sub-system, the
EasyPort™ features packet and ATM cell process-
ing functionality for data and voice/data Integrated
Access Devices (IADs), small and medium enter-
prise gateways, access routers, and Voice over IP
(VoIP) gateways. The EasyPort™ family supports
T1/E1 framers, standard xDSL transceivers, and
10BaseSTM Ethernet over VDSL technology. Easy-
Port™ has the compute power and architecture to
support firewalls and Virtual Private Networks
(VPN), as well as future applications and new con-
nectivity options such as Wireless LANs and
BluetoothTM.
When used in combination with VINETICTM, Infin-
eon's system solution supports VoATM and VoIP
on the same hardware platform, and supports up
to 32 compressed voice channels.
Using the EasyPort™ processor family, communi-
cation system vendors gain a powerful set of
tools enabling the transportation of data, video
and voice services integrated on the same hard-
ware and software platform.
Packet Processing
ATM Cell Processing
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External Bus Unit (50 MHz,
16-bit) for accessing system
memory (SRAM, Flash memory)
and external peripherals
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Embedded RISC coprocessor
Embedded data memory
Two 10/100 Mbit/s Ethernet
MAC controllers, one integrated
Ethernet PHY
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ATM Layer controller
UTOPIA Level 1 and 2
Support for up to 128 VCCs
Independent SDRAM I/F
Traffic classes: CBR, VBR,
(100 MHz, 32-bit, 256 MBytes)
UBR+, GFR, UBR
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USB 1.1 device controller
AAL5 (SAR) controller
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Cell Buffer Manager with
integrated DMA controller for
up to 255 user cell queues
Security Features
DMA controller with a linked list
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Security (VPN) and VoIP support
DES/3DESencryption/decryption
hardware accelerator
Throughput optimized dataflow
for VPN/IPsec processing
QoS optimized VoIP voice data
flow
descriptor buffer
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Queue specific traffic shaper in
Voice Data Processing
hardware
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Embedded RISC coprocessor
Two IOM-2/PCM interfaces
32 HDLC hardware accelerators
AAL2 (CPS) controller
Simple control of DuSLIC,
SICOFI and FALC® devices via a
Synchronous Serial Interface
(SSC)
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Cell filtering
(2 filters; maskable VPI/VCI)
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EPD, PPD congestion control
OAM according to ITU-T I.610
Others
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Embedded Processor Subsystem
Power management
Lifeline service support
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200 MHz MIPS CPU core includ-
ing MMU with 32 dual entry TLB
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E a s y P o r t ™
Multi-Service Access Processor Family
PXB 9101/9102/9201/9202
N e v e r s t o p t h i n k i n g .
