DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER
IDT5V60014
Description
Features
The IDT5V60014 is a high speed, high output drive, low
phase noise Zero Delay Buffer (ZDB) which integrates IDT’s
proprietary analog/digital Phase Locked Loop (PLL)
techniques. The IDT5V60014 is designed to operate at low
frequencies, with faster rise and fall times, and with lower
phase noise. The zero delay feature means that the rising
edge of the input clock aligns with the rising edges of both
outputs, giving the appearance of no delay through the
device. There are two outputs on the chip. The device has
internal feedback loop eliminating the complexity of external
feedback loop.
• Packaged in 8-pin MSOP (Pb free)
• Low phase noise zero delay buffer
• Low skew outputs
• Input clock frequency from 10 MHz to 38 MHz at 3.3 V
• Phase noise of better than -100 dBc/Hz from 1 kHz to
1 MHz offset from carrier
• Recover poor input clock duty cycle
• Output clock duty cycle of 45/55 at 3.3 V
• High drive strength
The chip is ideal for synchronizing outputs in a large variety
of systems, from personal computers to data
communications to video. The low phase noise
performance makes the device particularly suitable for
audio applications. By allowing off-chip feedback paths, the
IDT5V60014 can eliminate the delay through other devices.
• Full CMOS clock swings with 15 mA drive capability at
TTL levels
• Advanced, low power CMOS process
• 3.3 V operating voltages
• Industrial Temperature Range: -40 to +85° C
Block Diagram
Phase
Detector,
Charge
Output
CLK1
Buffer
ICLK
VCO
pump, and
Loop Filter
Output
CLK2
Buffer
Internal feedback
IDT™ LOW PHASE NOISE ZERO DELAY BUFFER
1
IDT5V60014 REV D 040609
