PRELIMINARY DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER
IDT5V60002
Description
Features
The IDT5V60002 is a high speed, high output drive, low
phase noise Zero Delay Buffer (ZDB) which integrates IDT’s
proprietary analog/digital Phase Locked Loop (PLL)
techniques. The IDT5V60002, part of IDT’s ClockBlocks™
family, was designed to operate at higher frequencies, with
faster rise and fall times, and with lower phase noise. The
zero delay feature means that the rising edge of the input
clock aligns with the rising edges of both outputs, giving the
appearance of no delay through the device. There are two
outputs on the chip, one being a low-skew divide by two of
the other.
• Packaged in 8-pin SOIC (RoHS compliant)
• Can function as low phase noise x2 multiplier
• Low skew outputs. One is ÷2 of other
• Input clock frequency up to 160 MHz at 3.3 V
• Phase noise of better than -100 dBc/Hz from 1 kHz to 1
MHz offset from carrier
• Can recover poor input clock duty cycle
• Output clock duty cycle of 45/55 at 3.3 V
• High drive strength for >100 MHz outputs
The chip is ideal for synchronizing outputs in a large variety
of systems, from personal computers to data
• Full CMOS clock swings with 25 mA drive capability at
TTL levels
communications to video. By allowing offchip feedback
paths, the IDT5V60002 can eliminate the delay through
other devices. The use of dividers in the feedback path will
enable the part to multiply by more than two.
• Advanced, low power CMOS process
• Operating voltage of 3.0
Block Diagram
IDT™ LOW PHASE NOISE ZERO DELAY BUFFER
1
IDT5V60002
REV A 010307
