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NWK939/CG/TP1N

型号：

NWK939/CG/TP1N

品牌：

MICROSEMI[ Microsemi ]

页数：

15 页

PDF大小：

305 K

下载PDF手册
This product is obsolete.  
This information is available for your  
convenience only.  
For more information on  
Zarlink’s obsolete products and  
replacement product lists, please visit  
http://products.zarlink.com/obsolete_products/  
NWK939  
10/100 Base-TX Symbol Transeiver  
Advance Information  
DS4733 - 2.2 January 1998  
The NWK939 is a CMOS Fast Ethernet Transceiver with  
integrated clock and data recovery for combined 10BASE-T  
and 100BASE-TX applications. The device connects through  
a 5 bit symbol interface directly with the NWK960 and similar  
controllers that incorporate the PCS function such as the  
DEC21143. The NWK939 incorporates on-chip filtering and  
pulse shaping to allow use of common 1:1 magnetics  
(isolation transformers) for both 10 Mb/s and 100 Mb/s modes.  
RDAT3  
RDAT4  
1
2
3
4
5
6
7
8
9
39 TP_TDP  
38 REFCLK  
37 OSCVDD  
36 XTAL1  
RXC  
SDT100  
ASDT  
35 XTAL2  
FEATURES  
■ 10BASE-T and 100BASE-TX switchable  
■ IEEE-802.3 compatible  
■ ConnectswithNWK960forcomplete10/100NICsolution  
■ Single 1:1 magnetics module for both 10BASE-T and  
100BASE-TX  
RXGND3  
RXVDD3  
LPWR_N  
RESET_N  
34 OSCGND  
33 TXGND4  
32 TXVDD4  
31 SUBVDD  
30 TXVDD3  
29 TXGND3  
28 TXREFF100  
27 TXREF10  
RXVDD2 10  
RXGND2 11  
TXOE 12  
RDOE 13  
■ Industry standard Symbol Interface  
■ Supports half and full-duplex operation  
■ Low latency  
GP52  
TP52  
■ Integrated diagnostic loopback  
■ Low power mode  
Fig.1 Pin connections - top view  
■ Operateswithcrystaloscillatororexternalclocksource  
■ Integrated filters and pulse shaping  
■ QuantizedFeedbackcircuitrytocorrectBaseLineWander  
■ Integrated clock recovery and clock synthesis  
■ Integrated adaptive equalizer  
■ Low power CMOS technology  
■ Single +5V supply  
■ 52 Pin PQFP package  
■ Also available in Thin PQFP package  
■ Full support for auto-negotiation signalling  
■ Internal loop filter components  
■ Low external component count  
ORDERING INFORMATION  
NWK939C/CG/GH1N  
NWK939/CG/TP1N thin quad  
NWK936 10/100 PCS  
or  
Symbol  
Interface  
NIC Controller  
(NWK960, DEC21143 or similar)  
Isolation  
Magnetics  
NWK939  
RJ-45  
or  
Repeater Controller  
(NWK950, MXIC98741  
or similar)  
Fig.2 System block diagram  
NWK939  
Compliance to Standards  
OVERVIEW  
The NWK939 is designed for compliance with the IEEE 802.3  
Standard, Clauses 14, 24 & 25, henceforth referred to as 802.3.  
The 802.3 PMD sub-layer for 100BASE-TX is derived from the  
FDDI TP-PMD Standard, henceforth referred to as TP-PMD.  
The NWK939 is a mixed-signal CMOS 10/100Mb/s  
transceiver which integrates all of the signal processing  
components of the dual speed Ethernet Physical Layer. It is  
designedforcompliancewithIEEE802.3Standardsanddirectly  
interfaces to a variety of Network Interface Card and Repeater  
controllerdevicesthroughtheindustrystandardsymbolinterface.  
The NWK939 employs robust design techniques to provide a  
very low bit-error rate and automatic recovery from fault  
conditions.  
Compatibility With Other Devices  
For Network Interface Card applications the NWK939 is  
designed to operate with controllers such as the NWK960 and  
the DEC21143, connecting via the symbol interface.  
For 100BASE-TX repeater applications the NWK939 is  
designed to operate with controllers such as the NWK950 and  
MXIC98741, also connecting via the symbol interface.  
TX10REF  
TP_TDP  
TX10 PULSE  
SHAPER &  
FILTER  
TX10  
DRIVER  
100MHz  
SYNTHESIZER  
LOOPBACK  
TP_RDP  
TP_RDM  
RX10  
FILTER  
RX10 CLOCK  
RECOVERY  
RX10 SIGNAL  
DETECT  
TXC  
RXC  
TXOP  
TXON  
RXIP  
RXIN  
RDAT[4:0]  
ASDT  
RX100  
EQUALIZER  
& BLW  
RX100 SIPO  
& DECODER  
RX100 CLOCK  
RECOVERY  
SDT100  
CORRECTION  
RX100  
SIGNAL  
DETECT  
LOOPBACK  
125MHz  
SYNTHESIZER  
TX100  
DRIVER  
TX100 PISO  
& ENCODER  
TDAT[4:0]  
TX100REF  
POWER  
ON  
RESET  
CONTROLS  
OSC  
Fig.3 NWK939 block diagram  
2
NWK939  
FUNCTIONAL DESCRIPTION  
TX10 Latency  
TheNWK939hasthreeoperatingmodes:10BASE-Tmode,  
100BASE-TX mode and LOW-POWER mode. The modes are  
selected by the N10/100 and LPWR_N pins.The Control block  
isdesignedtomanagethesemodesbystartingandstoppingthe  
two transceivers in a well-controlled manner such that no  
spurious signals are output on either the symbol or twisted-pair  
interfaces. Furthermore, it continuously monitors the behaviour  
of the transceivers and takes corrective action if a fault is  
detected.  
When connected to appropriate magnetics the latency  
through the TX10 path is less than 1BT (100ns) for data  
transmissions. This timing is measured from the falling edge of  
TXC to the output of the transmit magnetics. The TX10 path will  
not transmit the first two Manchester encoded bits of a data  
transmission, as permitted by the 802.3 Standard.  
RX10 Filter & RX10 Signal Detect  
These blocks work in unison to remove noise and to block  
signals that do not achieve the voltage levels specified in 802.3.  
Signals that do not achieve the required level are not sampled  
in the Clock Recovery block and are not passed to the DAT10/  
SDT10 and TP_RDP/TP_RDM outputs.  
25MHz REFERENCE CLOCK  
TheNWK939requiresa25MHz+/-100ppmtimingreference  
for 802.3 compliant operation. This may be supplied either from  
the integrated oscillator or from an external source. When the  
integratedoscillatorisused,asuitablecrystalmustbeconnected  
across the XTAL1 & XTAL2 pins (see “External Components”).  
Whenanexternalsourceisused,itmustbeinputtotheREFCLK  
pinandXTAL1mustbetiedhigh. XTAL2mustbeunconnected.  
RX10 Clock Recovery  
The RX10 Clock Recovery employs a digital delay line  
controlled by the 100MHz Synthesizer DLL to derive a sampling  
clock from the incoming signal. The recovered clock runs at  
twicethedatarate(nominally20MHz).Whenasignalisreceived  
fromtheSignalDetectblock,SDT10isassertedandfallingRXC  
is used to strobe Link Pulses and Manchester encoded serial  
data out on DAT10 and TP_RDP/TP_RDM. When no signal is  
being received, SDT10 is deasserted, RXC is driven from the  
20MHztransmitclock,DAT10isheldlowandTP_RDP/TP_RDM  
is driven to the zero state (see “DC Electrical Characteristics”).  
10BASE-T OPERATION  
In 10BASE-T mode Manchester encoded serial data is  
loaded from the TP_TDP input, processed through the TX10  
Path and output on the TXOP/TXON differential output for  
transmission through 1:1 magnetics and onto the twisted-pair.  
The incoming signal received from the magnetics into the  
RXIP/RXIN differential input is processed through the RX10  
Path. Received data is output serially on 2 interfaces. The  
DAT10 & SDT10 signals form a Mitel Semiconductor-specific  
interface for connection to the NWK936 PCS device. For NIC  
controllers that have in-built 10BASE-T receivers, the received  
signal is also provided on the TP_RDP/TP_RDM differential  
output. The TX10 & RX10 paths are disabled when the device  
is not in 10BASE-T mode.  
RX10 Latency  
When connected to appropriate magnetics the latency  
through the RX10 path is less than 1BT (100ns). This timing is  
measured from the input of the receive magnetics to the falling  
edgeofRXC.TheRX10pathmayignoreuptothreeManchester  
encoded bits at the start of data reception (802.3 allows up to 5  
bits) and the first bit forwarded to TP_RDP/TP_RDM may have  
timing violations (802.3 allows 1 bit).  
100MHz Synthesizer  
This synthesizer employs a delay-locked loop (DLL) to  
generate a 100MHz timing reference from the 25MHz reference  
clock.This100MHzreferenceisusedbythe10BASE-Ttransmit  
and receive functions and is divided by 5 to provide a 20MHz  
data strobe on TXC. The synthesizer is disabled when not in  
10BASE-T mode.  
100BASE-TX OPERATION  
In 100BASE-TX mode 5-bit NRZ symbols are loaded from  
theTDATbus,processedthroughtheTX100Pathandoutputon  
theTXOP/TXONdifferentialoutputfortransmissionthroughthe  
1:1 magnetics and onto the twisted-pair.  
The incoming signal received from the magnetics into the  
RXIP/RXIN differential input is processed through the RX100  
Pathandoutputin5-bitparallelNRZformontheRDATbus. The  
TX100 path is disabled when not in 100BASE-TX mode and,  
with the exception of the RX100 Signal Detect, the RX100  
Receive Path is disabled when not in 100BASE-TX mode.  
TX10 Pulse Shaper & Filter  
This block loads Link Pulses and Manchester encoded  
serial data from the TP_TDP input on the falling edge of TXC.  
This input may be connected directly to the TP_TDP output of  
the DEC21143 and similar NIC controllers. The Pulse Shaper &  
Filter employs a digital finite impulse response filter (FIR) to pre-  
compensate for line distortion and to remove high frequency  
components in accordance with the 802.3 Standard. The Pulse  
Shaper & Filter is disabled when not in 10BASE-T mode.  
125MHz Synthesizer  
This synthesizer employs a phase-locked loop (PLL) to  
generate a 125MHz timing reference from the 25MHz reference  
clock. This 125MHz reference is used by the 100BASE-TX  
transmit function and is divided by 5 to provide a 25MHz data  
strobe on TXC. TXC is frequency and phase locked to the  
25MHz reference with a small phase offset. The synthesizer is  
disabled when not in 100BASE-TX mode.  
TX10 Driver  
The TX10 Driver operates with 1:1 magnetics to provide  
impedancematchingandamplificationofthesignalinaccordance  
with the 802.3 specifications. The transmit current is governed  
bythecurrentthroughtheTXREF10pin,whichmustbegrounded  
through a resistor as described in “External Components”.  
3
NWK939  
TX100 PISO & Encoder  
RX100 Equalizer & Base-line Wander Correction  
The TX100 PISO & Encoder loads NRZ-coded symbols  
from TDAT on the rising edge of TXC, and converts them to  
serial MLT3 for outputting to the TX100 Driver. The TDAT[4] bit  
is output first. The PISO & Encoder do not operate until the  
125MHz Synthesizer is locked to the 25MHz reference. This  
avoids transmission of spurious signals onto the twisted-pair.  
TheRX100Equalizercompensatesforthesignalattenuation  
and distortion resulting from transmission down the cable and  
throughtheisolationtransformers.TheEqualizerisself-adjusting  
and is designed to restore signals received from up to 10dB  
cable attenuation. The Equalizer is inactive when ASDT is  
deasserted. WhenASDTisassertedhigh, theEqualizeradjusts  
to the incoming signal within 1ms. Thereafter, the Equalizer will  
continuously adjust to small variations in signal level without  
corrupting the received data.  
The 100BASE-TX MLT3 code contains significant low  
frequencycomponentswhicharenotpassedthroughtheisolation  
transformers and cannot be restored by an adaptive equalizer.  
This leads to a phenomenon known as base-line wander which  
willcauseanunacceptableincreaseinerrorrateifnotcorrected.  
The NWK939 employs a quantized feedback technique to  
restore the low frequency components and thus maintain a very  
low error rate even when receiving signals such as the “killer  
packet” described in the TP_PMD spec.  
TX100 Driver  
The TX100 Driver outputs the differential signal onto the  
TXOP and TXON pins. It operates with 1:1 magnetics to provide  
impedancematchingandamplificationofthesignalinaccordance  
with the 802.3 specifications. The transmit current is governed  
by the current through the TXREF100 pin, which must be  
grounded through a resistor as described in “External  
Components”. The TX100 driver is disabled in 10BASE-T mode  
and when LBEN is active.  
TX100 Latency  
When connected to appropriate magnetics the typical latency  
through the TX100 path is 1.2BT (12ns). This timing is measured  
fromtherisingedgeofTXCtotheoutputofthetransmitmagnetics.  
RX100 Clock Recovery  
The RX100 Clock Recovery circuit uses a Phase-Locked  
Loop (PLL) to derive a sampling clock from the incoming signal.  
The recovered clock runs at the symbol bit rate rate (nominally  
125MHz) and is used to clock the MLT3 decoder and the Serial  
to Parallel converter (SIPO). The recovered clock is divided by  
5 to generate the receive clock (RXC) which is used to strobe  
received data across the symbol interface. When ASDT is  
deasserted in 100BASE-TX mode, the PLL is locked to the  
reference clock and runs at 125MHz. This ensures that RXC  
runs continuously at 25MHz in 100BASE-TX mode. When  
ASDT is asserted high, the Clock Recovery PLL remains locked  
to the reference until the equalizer has adjusted, then it requires  
up to 1ms to phase lock to the incoming signal. No data is  
passed to the symbol interface until lock is established.  
00000  
TDAT[4:0]  
11111  
00000  
TXC  
+
twisted-pair  
0
–
12ns 8ns 8ns 8ns 8ns  
Fig.4 100BASE-TX transmit latency  
RX100 Signal Detect  
RX100 SIPO & Decoder  
The RX100 SIPO & Decoder converts the received signal  
from serial MLT3 to 5-bit parallel NRZ which is output on RDAT.  
TheNWK939doesnotalignreceivedsymbolstotheRDATbus.  
When ASDT is deasserted, RDAT is driven low. RDAT will  
continue to be driven low until ASDT is asserted, the Equalizer  
has adjusted, and the Clock Recovery is phase locked to the  
incoming signal. This ensures that no invalid data is passed to  
the higher layers.  
TheRX100SignalDetectcontinuouslymonitorsthelevelon  
theRXIP/Ndifferentialinput.ASDT(AsynchronousSignalDetect)  
will be asserted high whenever the signal amplitude exceeds  
the minimum that can be handled by the RX100 Equalizer.  
RX100 Signal Detect does not discriminate between signal  
types, therefore ASDT will be asserted for 10BASE-T signals  
and Link Pulses as well as for100BASE-TX signals. RX100  
Signal Detect is continuously active in all 3 operating modes,  
therefore ASDT may be used to externally generate a wake-up  
signal when the device is in LOW-POWER mode.  
RX100 Signal Detect also generates SDT100 which is a  
synchronousversionofASDT. SDT100issynchronoustoRXC  
rising and operates in both 10BASE-T mode and 100BASE-TX  
mode. In LOW-POWER mode RXC is stopped and SDT100 is  
driven low.  
RX100 Latency  
The typical latency through the RX100 Receive Path is  
6.4BT (64ns). This timing is measured from the start of a bit  
seen on the twisted-pair medium to the RXC falling edge that  
outputs that bit to the RDAT bus. The bit may appear in any  
position on RDAT, and therefore the latency varies as follows:  
twisted-pair -> RDAT[4] = 64ns  
twisted-pair -> RDAT[3] = 56ns  
twisted-pair -> RDAT[2] = 48ns  
twisted-pair -> RDAT[1] = 40ns  
twisted-pair -> RDAT[0] = 32ns  
4
NWK939  
Mode Selection (LPWR_N & N10/100)  
+
0
–
LOW-POWERmodecanbeselectedatanytimebyasserting  
LPWR_N low. When LPWR_N is inactive, 10BASE-T mode is  
selectedbypullingN10/100low,100BASE-TXmodeisselected  
by pulling N10/100 high. During mode changes the TXC & RXC  
clocks will continue to run but there will be no data transfers until  
the appropriate transceiver has been started up.  
twisted-pair  
RXC  
00000  
RDAT[4:0]  
Diagnostic Loopback (LBEN)  
64ns or 56ns or 48ns  
or 40ns or 32ns  
Diagnosticloopbackmaybeselectedatanytimebyasserting  
LBEN high. In 10BASE-T mode transmission to the TXOP/  
TXON output will be stopped and the RX10 Clock Recovery will  
receive input from the TX10 transmit path rather than from the  
RXIP/RXIN inputs. In 100BASE-TX mode transmission to the  
TXOP/TXONoutputwillbestopped,theRX100ClockRecovery  
will receive input from the TX100 transmit path and SDT100 will  
be forced high.  
Fig.5 100BASE-TX receive latency  
LOW-POWER OPERATION  
In LOW-POWER mode the 10BASE-T and 100BASE-TX  
transceivers are disabled. This mode is intended to conserve  
power when the network connection is not required.  
The synthesizers and all TX10 & TX100 functions are  
disabled and the TXOP/TXON output is undriven.  
The oscillator continues to run and the 25MHz reference will  
be driven out onto TXC if RDOE is asserted. This facility is  
provided for interfacing to the DEC21143 where a continuous  
clock is required.  
All RX10 & RX100 functions except RX100 Signal Detect  
are disabled. RX100 Signal Detect continues to monitor the  
RXIP/RXIN input and to drive ASDT accordingly. ASDT may  
therefore be used to externally generate a wake-up signal.  
The RXC clock is stopped in LOW-POWER mode and the  
RDAT & SDT100 outputs are held low.  
Transmitter Output Enable (TXOE)  
The TX10 Driver & TX100 Driver may be disabled by driving  
TXOE low. This control signal is provided for compatibility with  
earlier Mitel Semiconductor transceivers. It provides modest  
power savings and can be used to reduce EMI generation from  
unconnected twisted-pair ports, but is superseded on the  
NWK939 by the LOW-POWER mode.  
Receive Data Output Enable (RDOE)  
ThissignalmustbepulledhighwheninterfacingtoDEC21143  
and similar NIC controllers. RDOE enables the TP_RDP/  
TP_RDM output and also keeps TXC running in LOW_POWER  
mode. In 100Mb/s-only applications, or when interfacing to the  
NWK936, noise and power savings may be achieved by setting  
RDOE low.  
CONTROL SIGNALS  
Initialization,modeselectionandotheroptionsaregoverned  
by the control inputs as described in the following paragraphs.  
Initialization (RESET_N)  
INTERFACE DESCRIPTIONS  
The NWK939 incorporates a power-on-reset circuit for self-  
initialization on power-up. During initialization the open-drain  
RESET_N pin is driven low and all data outputs are disabled to  
prevent spurious outputs to the twisted-pair and to the symbol  
interface. RESET_N will remain low until either the 10BASE-T  
or 100BASE-TX transceiver has been correctly initialized. The  
NWK939 will then release RESET_N allowing the external pull-  
up to pull the pin high. Data transmission and reception will not  
commence until RESET_N is high. This allows the user to  
extend the inactive period by externally holding RESET_N low.  
It will not normally be necessary for the user to drive RESET_N  
becausetheNWK939isdesignedtoautomaticallyrecoverfrom  
fault conditions, however if required, the user may initialize the  
device by pulsing RESET_N low.  
10BASE-T Transmit Data (TP_TDP)  
In 10BASE-T mode Link Pulses and Manchester encoded  
serial data are loaded from the TP_TDP input for transmission  
on the twisted-pair. TP_TDP is sampled on the falling edge of  
TXC. The TP_TDP input is designed to be driven from either the  
DEC21143 TP_TDP output or the NWK936 TP_TDP output.  
LP  
Packet SOI  
LP  
LP  
Packet SOI  
LP  
Note1:HoldingRESET_Nlowwillnotholdthedeviceinastatic,  
lowpowerstate.Itwillinitializetheselectedtransceiverandstart  
the appropriate clocks. For power saving use the LPWR_N pin.  
Note 2: The NWK936 PCS device is initialized by connecting its  
RESET_N input to the NWK939 pin.  
Fig.6 Signals on TP_TDP  
Note 3: If the NWK939 is powered-up with LPWR_N low, then  
the device will immediately enter LOW-POWER mode and  
RESET_N will be held low until LPWR_N is deasserted and one  
of the transceivers is started up.  
10BASE-T data transmissions consist of Manchester  
encoded data packets separated by an idle pattern (see Fig.6).  
The idle pattern comprises a Start-of-Idle (SOI) pulse which is  
appended to the end of each packet, and Link Pulses at 8 to  
24ms intervals. During 802.3 Auto-negotiation a faster burst of  
Link Pulses is transmitted.  
5
NWK939  
TXC  
TXC  
TP_TDP  
(last data = 0)  
TX_TDP  
TP_TDP  
(last data = 1)  
Fig.10 Start-of-Idle on TP_TDP  
Fig.7 Link pulse on TP_TDP  
When no transmission is required, the TP_TDP input must  
beheldlow. ToinitiateLinkPulsetransmission, TP_TDPshould  
be driven high for 2 cycles of TXC (see Fig. 7). The NWK939  
requiresthattheintervalbetweenLinkPulsesbegreaterthan10  
cycles of TXC (500ns).  
The TP_TDP input is ignored when the device is not in  
10BASE_T mode.  
10BASE_T Receive Data (TP_RDP/TP_RDM)  
This serial interface is for passing received signals to the  
DEC21143 and similar controllers. TP_RDP/TP_RDM is  
equivalent to the signal received on RXIP/RXIN after filtering,  
jitterreductionandsuppressionoflowlevelsignals.TheTP_RDP/  
TP_RDM output is disabled when RDOE is deasserted and  
when the device is not in 10BASE-T mode.  
TXC  
10BASE_T Receive Data (DAT10 & SDT10)  
TP_TDP  
This serial interface is for passing received signals to the  
NWK936 PCS device. In 10BASE-T mode DAT10 & SDT10 are  
multiplexed onto RDAT[0:1] and the remaining bits of RDAT are  
heldlow. TheDAT10&SDT10outputsaresynchronoustoRXC  
falling and are intended to be sampled by the NWK936 on RXC  
rising. When no signal is being received from the twisted-pair  
both DAT10 & SDT10 are held low.  
Fig.8 Packet on TP_TDP  
For data packet transmission the Manchester encoded data  
must be presented to the TP_TDP input (see Fig. 8).  
DAT10  
(good polarity)  
DAT10  
(reverse polarity)  
TXC  
TP_TDP  
SDT10  
RXC  
min 10 cycles of TXC  
Fig.11 Link pulse on DAT10 & SDT10  
Fig.9 Interval between link pulse and packet  
When a Link Pulse is received SDT10 will be asserted high  
for 2 or 3 cycles of RXC (see Fig. 11). If the Link Pulse has the  
correct polarity then DAT10 will also be asserted high. If the  
polarityisreversedduetoatwisted-pairwiringfault,thenDAT10  
will remain low during reception of the Link Pulse. The NWK936  
will check and correct for polarity reversal. Packet data and  
Start-of-Idle (SOI) pulse reception are illustrated in Figs. 12 & 13.  
The interval between a Link Pulse and the first logic 1 in the  
packet signal should be greater than 10 cycles of TXC (see  
Fig. 9). If theintervalislessthan10cyclesthenthefirstbitofthe  
packettransmissionmaybecorrupted, butthecorruptionwillbe  
within that allowed by 802.3.  
The SOI pulse will be transmitted if the TP_TDP input is held  
high for 6 cycles of TXC at the end of the data packet. If the last  
data bit transmitted was a logic 1 then the latter half of this bit will  
merge with the SOI pulse such that TP_TDP is high for 7 cycles  
of TXC (see Fig.10).  
DAT10  
SDT10  
RXC  
Fig.12 Start of packet on DAT10 & SDT10  
6
NWK939  
as the source of the MII TX_CLK. When working with the  
DEC21143 TXC should be used to drive the SYM_TCLK &  
XTAL1 inputs.  
DAT10  
(good polarity)  
DAT10  
(reverse polarity)  
Receive Clock (RXC)  
In 10BASE-T mode RXC is a continuous clock. During  
signal reception it is recovered from the incoming signal and  
runs nominally at 20MHz. When no signal is being received it  
is driven from the 20MHz transmit clock. At the start of data  
receptionRXCmustsynchronisetotheincomingsignal, during  
this time RXC conforms to the “during synchronization” timing  
indicated in “AC Electrical Characteristics”.  
In100BASE-TXmodeRXCisacontinuousclockrecovered  
from the incoming signal and running nominally at 25MHz.  
When there is no incoming signal the clock recovery PLL locks  
to the 25MHz reference. In LOW-POWER mode RXC is held  
low. On power-up, or following an external reset, RXC will be  
held low until the appropriate clock source is available and  
within specification. RXC starts up cleanly, i.e. with no short  
pulses or spikes. When the operating mode is changed, RXC  
continues to be driven from the old source until the new source  
is available and within specification. At changeover there will be  
no spikes, but RXC will have extended timing for one cycle only,  
see “AC Electrical Characteristics” for details. These  
specifications for start up and changeover ensure that higher  
layer devices can safely use RXC. In particular, it can be used  
as the source of the MII RX_CLK. When working with the  
DEC21143 RXC should be used to drive the SYM_RCLK input.  
SDT10  
RXC  
min 2 bit times  
3 ->6 bit times  
Fig.13 Start-of-Idle on DAT10 & SDT10  
100BASE-TX Transmit Data (TDAT)  
In 100BASE-TX mode symbol data is loaded from TDAT on  
TXC rising. Symbol data is defined as data which is 4B/5B  
encoded and scrambled. The user may present data either on  
TXC or on REFCLK (if the integrated oscillator is not being  
used). TXC & REFCLK are frequency and phase locked with a  
small phase error. TDAT timing is quoted with respect to both  
clocks, see “AC Electrical Characteristics”. TDAT is ignored  
when the device is not in 100BASE-TX mode.  
100BASE-TX Receive Data (RDAT)  
In 100BASE-TX mode received symbols are output on  
RDAT on RXC falling. The data is 5-bit parallel but symbols are  
not aligned to the bus.  
Signal Detect (ASDT & SDT100)  
Transmit Clock (TXC)  
ASDT (Asynchronous Signal Detect) will be asserted high  
whenever the signal amplitude exceeds the minimum that  
can be handled by the RX100 Equalizer. ASDT does not  
discriminate between signal types, and therefore will be  
asserted for 10BASE-T signals and Link Pulses as well as for  
100BASE-TX signals. ASDT is available in all 3 operating  
modes, therefore may be used to externally generate a wake-  
up signal when the device is in LOW-POWER mode.  
SDT100 is a synchronized and filtered version of ASDT,  
intended for connection to controllers such as the DEC21143.  
SDT100 is synchronous to RXC rising and pulses shorter than  
30µs are filtered out. In 10BASE-T mode and 100BASE-TX  
mode, SDT100 will respond to valid 100BASE-TX signals and  
10BASE-T packets but will not respond to 10BASE-T Link  
Pulses. In LOW-POWER mode RXC is stopped and SDT100 is  
driven low.  
In 10BASE-T mode TXC is a continuous 20MHz clock. In  
100BASE-TXmodeTXCisacontinuous25MHzclock,frequency  
&phaselockedtothe25MHzreference. InLOW-POWERmode  
TXC is driven from the 25MHz reference if RDOE is asserted,  
otherwise it is held low. On power-up, or following an external  
reset, TXC will be held low until the appropriate clock source is  
availableandwithinspecification.TXCstartsupcleanly,i.e.with  
noshortpulsesorspikes. Whentheoperatingmodeischanged,  
TXC continues to be driven from the old source until the new  
sourceisavailableandwithinspecification.Atchangeoverthere  
willbenospikes,butTXCwillhaveextendedtimingforonecycle  
only, see “AC Electrical Characteristics” for details. These  
specifications for start up and changeover ensure that higher  
layer devices can safely use TXC. In particular, it can be used  
7
NWK939  
PIN DESCRIPTIONS  
Pin Name  
Pin Type  
Pin Number  
Pin Description  
SYMBOL Interface  
RXC  
digital output  
3
Receive Clock. Recovered from the incoming signal.  
Derived from the reference clock when no incoming signal.  
Runs at 25MHz nominal in 100BASE-TX mode, 20MHz nominal in  
10BASE-T mode, and is held low in LOW-POWER mode.  
SDT100  
ASDT  
digital output  
digital output  
4
5
100BASE-TX Signal Detect. Active high, synchronous to RXC rising.  
Indicatestheincomingsignalexceeds100BASE-TXthresholds.Operatesin  
both 100BASE-TX & 10BASE-T modes. Held low in LOW-POWER mode.  
(Note: this signal responds to both 100BASE-TX & 10BASE-T signals.)  
Asynchronous Signal Detect. Active high, independent of all clocks.  
Indicates that the incoming signal exceeds 100BASE-TX thresholds.  
Operates in 100BASE-TX, 10BASE-T & LOW-POWER modes.  
(Note: this signal responds to both 100BASE-TX & 10BASE-T signals.)  
TDAT4  
TDAT3  
TDAT2  
TDAT1  
TDAT0  
digital inputs  
no pull-up  
42  
43  
44  
45  
46  
100BASE-TX Transmit Data. In 100BASE-TX mode, transmit symbols  
(i.e. encoded & scrambled data) are loaded on TXC rising. TDAT4 is  
transmitted first. These inputs are ignored in 10BASE-T &  
LOW-POWER modes.  
TXC  
digital output  
49  
Transmit Clock. Runs at 25MHz in 100BASE-TX mode and 20MHz in  
10BASE-T mode. In LOW-POWER mode TXC runs at 25MHz if RDOE=1,  
or is held low if RDOE=0.  
RDAT0/DAT10 digital outputs  
RDAT1/SDT10  
RDAT2  
RDAT3  
RDAT4  
50  
51  
52  
1
ReceiveData.SynchronoustoRXCfalling.In100BASE-TXmodereceived  
symbols (i.e. encoded & scrambled data) are output on RDAT[4:0].  
RDAT4 is the first bit received, symbols are not aligned to the bus.  
In 10BASE-T mode serial Manchester encoded receive data is output  
on DAT10, and SDT10 indicates the incoming signal exceeds 10BASE-T  
thresholds. In LOW-POWER mode RDAT[4:0] is held low.  
2
Network Interface  
RXIP  
RXIN  
differential  
analog input  
15  
16  
Receive Input. Input from the magnetics for both 100BASE-TX and  
10BASE-T reception.  
TXOP  
TXON  
differential  
analog output  
22  
21  
Transmit Output. Output to the magnetics for both 100BASE-TX and  
10BASE-T transmission. High impedance in LOW-POWER mode and  
when TXOE=0.  
TXOE  
digital input  
no pull-up  
12  
Transmit Output Enable. Active high. Enables the TXOP/TXON output.  
10BASE-T Interface  
TP_RDM  
TP_RDP  
differential  
analog output  
41  
40  
10BASE-T Receive Signal. In 10BASE-T mode this is a filtered and  
retimed copy of the twisted-pair receive signal. Held in the zero state  
(TP-RDP = TP-RDM) in 100BASE-TX and LOW-POWER modes. High  
impedance when RDOE=0.  
RDOE  
digital input  
no pull-up  
13  
39  
Receive differential output enable. Active high. Enables the TP-RDP/  
TP-RDM output.  
TP_TDP  
digital input  
no pull-up  
10BaseTTransmitData.In10BASE-Tmode,serialManchesterencoded  
data is loaded on TXC falling. This input is ignored in 100BASE-TX &  
LOW-POWER modes.  
8
NWK939  
PIN DESCRIPTIONS CONT.  
Pin Name  
Pin Type  
Pin Number  
Pin Description  
Control Pins  
LBEN  
digital input  
no pull-up  
25  
Loopback Enable. Active high. Enables internal loopback for diagnostic  
purposes in both 100BASE-TX & 10BASE-T modes. Suppresses  
transmission on TXOP/TXON.  
N10/100  
digital input  
no pull-up  
open drain digital  
output with digital  
input,no pull up  
26  
9
10BASE-T/100BASE-TX Select. Low selects 10BASE-T mode, high  
selects 100BASE-TX mode.  
Reset. Active low, bidirectional. Driven low by the NWK939 during  
initialisation. May be driven low from an external source to retrigger or  
extend initialisation.  
RESET_N  
LPWR_N  
TXREF10  
TXREF100  
digital input  
no pull-up  
8
LOW-POWER Mode Select. Active low.  
analog  
27  
28  
10BASE-TTransmitterReference.Setsthe10BASE-Ttransmittercurrent.  
Connect to ground through external resistor.  
analog  
100BASE-TX Transmitter Reference. Sets the 100BASE-TX transmitter  
current. Connect to ground through external resistor.  
Clocks  
REFCLK  
digital input  
with pull-up  
38  
36  
35  
25MHz Reference. Drive from external 25MHz source when the on-chip  
oscillator is not used. Connect to OSCVDD when on-chip oscillator is used.  
XTAL1  
XTAL2  
analog  
25MHz crystal input. Connect to OSCVDD when the on-chip oscillator is  
not used.  
analog  
25MHz crystal input. Leave unconnected when the on-chip oscillator  
is not used.  
Power  
DIGGND  
DIGVDD  
RXGND  
RXVDD  
TXGND  
TXVDD  
ground  
power  
ground  
power  
ground  
power  
ground  
power  
power  
47  
48  
Digital ground  
Digital power  
6,11,14  
7,10,17  
23,24,29,33  
20,30,32  
34  
Receive ground  
Receive power  
Transmitter ground  
Transmitter power  
Oscillator ground  
Oscillator power  
Substrate power  
OSCGND  
OSCVDD  
SUBVDD  
37  
31  
No Connects  
-
-
-
-
18  
19  
do not connect to this pin  
do not connect to this pin  
9
NWK939  
RECOMMENDED OPERATING CONDITIONS  
Neither performance nor reliability are guaranteed outside  
these limits. Extended operation above these limits may affect  
device reliability.  
ABSOLUTE MAXIMUM RATINGS  
Exceeding the absolute maximum ratings may cause  
permanent damage to the device. Extended exposure at the  
maximum ratings will affect device reliability.  
Supply voltage (VDD  
Input voltage  
Output voltage  
Static discharge voltage  
Storage temperature (TA)  
)
–0.5 to +7V  
–0.5 to VDD+0.5V  
–0.5 to VDD+0.5V  
4kV HBM  
Supply voltage (VDD  
Input voltage  
Output voltage  
Current per pin  
Ambient temperature (TA)  
)
+5V ±5%  
0 to VDD  
0 to VDD  
100mA  
0°C to +70°C  
-40 to +125°C  
SUPPLY CURRENT  
Recommended operating conditions apply except where stated.  
Value  
Typ.  
Characteristic  
Symbol  
Units  
Conditions  
Min.  
Max.  
With external components  
as shown in Fig.14.  
Supply currents quoted  
here include currents  
through external  
10BASE-T mode, not transmitting  
10BASE-T mode, transmitting  
100BASE-TX mode  
IDD  
IDD  
IDD  
IDD  
-
-
-
-
105  
178  
108  
35  
115  
190  
120  
40  
mA  
mA  
mA  
mA  
Low Power mode  
components.  
DC ELECTRICAL CHARACTERISTICS  
Recommended operating conditions apply except where stated.  
Value  
Typ.  
Characteristic  
Symbol  
Units  
Conditions  
Min.  
Max.  
Digital input, no pull-up  
Input high voltage  
Input low voltage  
Hysteresis  
Input high current  
Input low current  
Capacitance  
VIH  
VIL  
VH  
IIH  
IIL  
CI  
2
VSS  
0.3  
-
-
-
-
-
-
-
-
-
VDD  
0.8  
-
1
–1  
8
V
V
V
µA  
µA  
pF  
including package  
including package  
Digital input, with pull-up  
Input high voltage  
Input low voltage  
Hysteresis  
Input high current  
Input low current  
Capacitance  
VIH  
VIL  
VH  
IIH  
IIL  
CI  
2
VSS  
0.3  
-
–17  
-
-
-
-
-
-
-
VDD  
0.8  
-
V
V
V
µA  
µA  
pF  
1
–130  
8
Digital output  
Output high voltage  
Output low voltage  
Rise time  
Fall time  
Capacitance  
VOH  
VOL  
tR  
tF  
CO  
4
VSS  
-
-
-
-
-
-
-
-
VDD  
0.4  
4
3
8
V
V
ns  
ns  
pF  
IOH = –6mA  
IOL = 6mA  
0.4V to 2.4V into 20pF  
2.4V to 0.4V into 20pF  
including package  
Open drain digital output  
Output low voltage  
Fall time  
Capacitance  
VOL  
tF  
CO  
VSS  
-
-
-
-
-
0.4  
TBD  
8
V
ns  
pF  
IOL = 6mA  
5V to 0.4V into 20pF  
including package  
TP_RDP/TD_RDM differential output  
High level  
Zero level  
Low level  
Centred voltage  
VH  
V0  
VL  
VC  
1
-200  
–1  
-
-
-
-
3
200  
–3  
-
V
mV  
V
VDD/2  
V
10  
NWK939  
AC ELECTRICAL CHARACTERISTICS  
Recommended operating conditions apply except where stated.  
Value  
Typ.  
Characteristic  
Symbol  
Units  
Conditions  
Min.  
Max.  
REFCLK  
Frequency  
Duty cycle  
25±100ppm  
MHz  
%
45  
-
55  
TXC  
10BASE-T Mode  
Frequency  
20±100ppm  
MHz  
%
Duty cycle  
45  
45  
40  
-
55  
55  
60  
100BASE-TX Mode  
Frequency  
25±100ppm  
MHz  
%
Duty cycle  
-
LOW-POWER Mode with RDOE=1  
Frequency  
25±100ppm  
MHz  
%
Duty cycle  
-
During transitions between modes  
High pulse width  
thi  
tlo  
15  
15  
-
-
30  
110  
ns  
ns  
for 1 cycle only  
for 1 cycle only  
Low pulse width  
RXC  
10BASE-T Mode  
Frequency  
20  
-
-
MHz  
%
ns  
Duty cycle  
High pulse width  
Low pulse width  
45  
15  
15  
55  
110  
110  
during data reception  
during synchronization  
during synchronization  
-
ns  
100BASE-TX Mode  
Frequency  
25  
-
MHz  
%
Duty cycle  
45  
55  
During transitions between modes  
High pulse width  
thi  
tlo  
15  
15  
-
-
30  
110  
ns  
ns  
for 1 cycle only  
for 1 cycle only  
Low pulse width  
TDAT[4:0] (100BASE-TX Mode only)  
Setup to TXC↑  
-
-
-
-
-
-
-
-
20  
0
10  
0
ns  
ns  
ns  
ns  
NIC applications  
NIC applications  
Repeater applications  
Repeater applications  
Hold from TXC↑  
Setup to REFCLK↑  
Hold from REFCLK↑  
TP-TDP (10BASE-T Mode only)  
Setup to TXC↓  
Hold from TXC↓  
-
-
-
-
10  
0
ns  
ns  
RDAT[4:0] & DAT10 & SDT10  
Prop delay from RXC↓  
0
0
-
-
-
7
7
-
ns  
ns  
ns  
SDT100  
Prop delay from RXC↑  
RESET_N  
Pulse width  
100  
11  
NWK939  
AC Characteristics TXOP/TXON in 10BASE-T Mode  
AC Characteristics TXOP/TXON in 100BASE-TX Mode  
(Continued)  
Parameter  
Reference  
Parameter  
Reference  
The peak differential voltage on the TD circuit  
when terminated with a 100Ω resistive load  
shall be between 2.2V and 2.8V for all data  
sequences.  
802.3 -  
14.3.1.2.1  
The rise and fall times measured from 10% to TP-PMD  
90% of the steady state output voltage shall be  
between 3ns and 5ns.  
9.1.6.  
When driven by an all-ones Manchester-  
encoded signal, any harmonic measured  
on the TD circuit shall be at least 27dB below  
the fundamental.  
The TX10 Transmitter shal provide equalisation 802.3 -  
such that the output waveform shall fall within 14.3.1.2.1  
the template shown in 802.3 Fig 14-9 for all  
data sequences.  
802.3 -  
Difference between max. and min. rise and TP-PMD  
fall times shall be less than 0.5ns. 9.1.6.  
14.3.1.2.1  
Duty cycle distortion must be less than ±0.25ns TP-PMD  
measured at 50% of the steady state output  
voltage for a data sequence of 01010101 (NRZ).  
9.1.8.  
Total transmit jitter, including duty cycle  
distortionand baseline wander, must be less  
than 1.4ns peak to peak.  
TP-PMD  
9.1.9.  
The Start-of-Idle pulse shall conform to the  
template of 802.3 Fig 14-10  
802.3 -  
14.3.1.2.1  
AC Characteristics RXIP/RXIN in 10BASE-T Mode  
The Link Pulse shall conform to the template  
of 802.3 Fig 14-12.  
802.3 -  
14.3.1.2.1  
Parameter  
Reference  
The differential output impedance as measured 802.3 -  
on TD shall be such that any reflection shall be 14.3.1.2.2  
at least 15dB below the incident.  
Differential signals received on the RD that are 802.3  
within the envelope of 802.3 Figs 14-16 &14-17 14.3.1.3.1  
shall be passed to RX10DATA.  
RD signals with up to ±13.5ns zero crossing 802.3  
jitter is accepted.  
The transmitter shall add no more than 3.5ns 14.3.1.2.3  
jitter when TD drives into 100Ω through the  
twisted pair.  
802.3 -  
14.3.1.3.1  
The transmitter shall add no more than 8ns  
jitter when TD drives into 100Ω.  
802.3 -  
14.3.1.2.3  
RD signals corresponding to the envelope of  
802.3  
802.3 Fig 14-12 shall be accepted as a link pulse. 14.3.1.3.2  
The common-mode to differential-mode  
balance shall exceed 29-17log10 (f/10) dB  
over the frequency range 1-20MHz.  
The common-mode output voltage shall not  
exceed 50mV peak.  
802.3 -  
The receiver shall reject as data signals which 802.3  
14.3.1.2.4  
would produce a peak magnitude of less than  
300mV after being filtered through a 3-pole low-  
pass Butterworth with a 3dB cutoff at 15MHz.  
14.3.1.3.2  
802.3 -  
14.3.1.2.5  
802.3 -  
The receiver shall reject as data continuous  
sinusoidal signals of amplitude less than 6.2V  
peak-to-peak and frequency less than 2MHz.  
802.3  
14.3.1.3.2  
Application of a common-mode 15V peak  
10.1MHz sinusoid to the test circuit shall not 14.3.1.2.6  
change the differentail voltage by more than  
100mV and will add no more than 1ns jitter.  
The receiver shall reject as data sine waves of 802.3  
single cycle duration,starting with phase 0 or 14.3.1.3.2  
180 degrees, and of amplitude less than 6.2V  
peak-to-peak where the frequency is between  
2MHz & 15MHz.  
The RD circuit differential input impedance shall 802.3  
be such that the reflection of any signal in the 14.3.1.3.4  
frequency range 5MHz to 10MHz is at least  
15dB below the incident.  
Application of a short circuit to TD shall not 802.3 -  
damage the circuit.  
The short circuit shall not exceed 300mA.  
14.3.1.2.7  
802.3 -  
14.3.1.2.7  
802.3 -  
14.3.1.2.7  
The transmitter shall withstand without  
damage a 1000V common-mode impulse.  
There shall be no extraneous signals on TD  
during normal power-up and power-down.  
802.3 -  
14.3.2.3  
The RD circuit common mode rejection shall 802.3  
be as defined in 802.3 14.3.1.3.5.  
14.3.1.3.5  
The RD circuit shall tolerate an indefinite  
short circuit.  
The RD circuit shall withstand a 1000V  
common modeimpulse.  
802.3  
14.3.1.3.6  
AC Characteristics TXOP/TXON in 100BASE-TX Mode  
802.3  
14.3.1.3.6  
Parameter  
The differential output voltage shall be in the TP-PMD  
range 950mV to 1050mV. 9.1.2.2  
Reference  
AC Characteristics RXIP/RXIN in 100BASE-TX Mode  
The differential overshoot shall not exceed 5%. TP-PMD  
9.1.3.  
Overshoot transients must decay to within 1% TP-PMD  
of the steady state voltage within 8ns of the start 9.1.3.  
of the differential signal transition.  
Parameter  
Reference  
The return loss shall be greater than 16dB from TP-PMD  
2MHz to 30MHz.  
The return loss shall be greater than (16dB-20 TP-PMD  
log(f/30MHz)) dB from 30MHz to 60MHz. 9.2.2  
The return loss shall be greater than 10dB from TP-PMD  
60MHz to 80MHz. 9.2.2  
9.2.2  
The signal amplitude symmetry shall be in the  
range 98% to 102%.  
TP-PMD  
9.1.4.  
The return loss shall be greater than 16dB from TP-PMD  
2MHz to 30MHz.  
9.1.5.  
The return loss shall be greater than (16-20log  
(f/30MHz) dB from 30MHz to 60MHz.  
TP-PMD  
9.1.5.  
The return loss shall be greater than 10dB from TP-PMD  
60MHz to 80MHz. 9.1.5.  
12  
NWK939  
0.1µF  
0.1µF  
RDAT3  
RDAT4  
RXC  
1
2
3
4
5
6
7
8
9
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
TP_TDP  
RFCLK  
OSVDD  
XTAL1  
SDT100  
ASDT  
25MHz  
C2  
XTAL2  
RXGND3  
RXVDD3  
OSCGND  
TXGND4  
TXVDD4  
SUBVDD  
TXVDD3  
C2  
5k(5%)  
LPWR_N  
RESET_N  
RXVDD2 10  
RXGND2 11  
TXOE 12  
TXGND3  
TXREFF100  
TXREF10  
RDOE 13  
1k2  
1k2  
(0.1%) (0.1%)  
50.1 (1%)  
34 (1%)  
34 (1%)  
50.1 (1%)  
0.01µF  
0.01µF  
16.2  
(1%)  
0.1µF  
16.2  
(1%)  
1:1 MAGNETICS  
Fig.14 External components  
EXTERNAL COMPONENTS  
Connecting an External 25MHz Reference  
Let PC = power dissipation of the crystal in mW,  
and ESR = equivalent series resistance of the crystal  
If an external clock is used then it should be driven into the  
REFCLK input, and XTAL1 must be connected to OSCVDD.  
XTAL2 must be left unconnected.  
in W.  
IfPC >2.6mWthenC1 & C2 aredeterminedbytheloopgain:  
RESET_N Pull-up Resistor  
184  
√ESR  
This resistor is required regardless of whether RESET_N is  
used externally.  
C1 = C2 =  
–7pF  
TP-RDP/TP-RDM AC-coupling  
If PC<2.6mW then C1 & C2 are determined by the power  
dissipation of the crystal:  
TP-RDP/TP-RDM must be AC-coupled when working with  
a DEC21143 controller (or equivalent), but should be left  
unconnected when working with the NWK936.  
PC  
C1 = C2 = 114  
–7pF  
RX Input Decoupling  
√ ESR  
The method of using a split input load resistor and de-  
coupling the centre tap reduces common mode noise.  
Tracking to the crystal and the capacitors must be as short  
as possible. Other signal paths must not cross the area.  
Crystal Oscillator  
ForIEEE802.3compliancetheoscillatormustrunat25MHz  
±100ppm. The NWK939 on-chip circuitry contributes less than  
40ppm variability to the oscillator frequency, therefore the  
crystalmustbespecifiedto60ppm.Thismustincludevariations  
due to temperature and ageing.  
The NWK939 is supported by magnetics from the following  
vendors:  
VENDOR  
MAGNETICS  
Bel  
Pulse  
Valor  
S558-5999-39  
H1012  
External capacitors are required on the XTAL1 & XTAL2  
pins. The values of these capacitors are dependent on the  
power dissipation and the equivalent series resistance of the  
chosen crystal, as follows:  
ST6118  
13  
For more information about all Zarlink products  
visit our Web Site at  
www.zarlink.com  
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such  
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property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in  
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any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and  
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not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in  
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.  
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system  
conforms to the I2C Standard Specification as defined by Philips.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright Zarlink Semiconductor Inc. All Rights Reserved.  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  
厂商 型号 描述 页数 下载

SEMIKRON

 		NWK40 对于SKiiP的2 + 3[ For SKiiP 2 + 3 ] 3 页

SEMIKRON

 		NWK40/180 对于SKiiP的2 + 3[ For SKiiP 2 + 3 ] 3 页

SEMIKRON

 		NWK40/240 对于SKiiP的2 + 3[ For SKiiP 2 + 3 ] 3 页

SEMIKRON

 		NWK40/300 对于SKiiP的2 + 3[ For SKiiP 2 + 3 ] 3 页

ZARLINK

 		NWK914B PHY / PMD高速铜介质收发器[ PHY/PMD High Speed Copper Media Transceiver ] 9 页

ETC

 		NWK914BCGGH1N LAN收发器\n[ LAN Transceiver ] 10 页

MITEL

 		NWK914CG PHY / PMD高速铜介质收发器[ PHY/PMD High Speed Copper Media Transceiver ] 9 页

MITEL

 		NWK914D PHY / PMD高速铜介质收发器[ PHY/PMD High Speed Copper Media Transceiver ] 9 页

ZARLINK

 		NWK914D PHY / PMD高速铜介质收发器[ PHY/PMD High Speed Copper Media Transceiver ] 9 页

ZARLINK

 		NWK914DCG PHY / PMD高速铜介质收发器[ PHY/PMD High Speed Copper Media Transceiver ] 9 页

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