WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
ICC SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Parameter
Symbol
Conditions
DDR400 @ DDR333 @
Unit
CL = 3
CL = 2.5
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN)
;
Operating current
Operating current
ICC0*
DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
1,585
mA
TBD
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN)
IOUT = 0mA; Address and control inputs change once per clock cycle
;
ICC1*
1,855
460
mA
mA
TBD
TBD
Percharge power-
down standby current
ICC2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address
and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS and DM
Idle standby current
ICC2F**
ICC3P**
ICC3N**
ICC4R*
ICC4W*
1,900
1,540
2,080
1,900
1,990
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
Active power-down
standby current
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX)
;
Active standby
current
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA
Operating current
Operating current
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and
DQS inputs change twice per clock cycle
Auto refresh current
Self refresh current
ICC5**
ICC6**
tRC = tRFC(MIN)
CKE < 0.2V
10,720
460
mA
mA
TBD
TBD
Four device bank interleaving Reads Burst = 4 with auto precharge;
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during
Active READ, or WRITE commands
Operating current
ICC7*
4,060
mA
TBD
NOTE:
I
CC specification is based on Micron components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in ICC2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
March 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
