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CYM9272APM-50C

型号：

CYM9272APM-50C

品牌：

CYPRESS[ CYPRESS ]

页数：

10 页

PDF大小：

185 K

下载PDF手册
1CYM9272A/B  
fax id: 2043  
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
64K x 36 SRAM Module  
128K x 36 SRAM Module  
256K x 36 SRAM Module  
512K x 36 SRAM Module  
9272A) or 256K x 18 SRAM’s (9272B, 9273). in plastic surface  
mount packages on an epoxy laminate board with pins. The  
modules are designed to be incorporated into large memory  
arrays.  
Features  
• Operates at 50 MHz  
• Uses 64K x 18/ 128K x 18 or256K x 18 highperformance  
synchronous SRAMs.  
• 144-position Angled DIMM from Berg p/n 61178  
• 3.3V inputs/data outputs  
The modules are configured as single banks or multiple banks  
depending on the SRAM used to make the module. Separate  
clock are provided for each of the banks. Separate clocks are  
provided for each of the SRAM’s.  
Functional Description  
Multiple ground pins and on-board de-coupling capacitors en-  
sure high performance with maximum noise immunity.  
The CYM9270, CYM9271, CYM9272 and the CYM9273 are  
high-performance synchronous memory modules organized  
as 64K(9270), 128K(9271), 256K(9272), 512K(9273) by 36  
bits. These modules are constructed using either 64K x 18  
SRAM’s (CYM9270, CYM9271A), 128K x 18 SRAM’s (9271B,  
All components on the cache modules are surface mounted  
on a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by 30  
micro-inches of gold flash.  
Logic Block Diagram - CYM9270/CYM9271A  
A[15:0]  
(2) 64K x 18 SRAM’S  
A15:0  
WE  
SGW  
D[0:31]  
OE0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS0  
DQ[0:3]  
BWE  
WEH  
WEL  
ADSP  
CLK[0:3]  
ADSC  
CLK  
Bank 0  
CLK[0:1]  
(2) 64K x 18 SRAM’S  
A15:0  
SGW  
OE  
OE1  
CS1  
D[0:15]  
DQ[0:1]  
CS  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank 1  
PD  
1
PD  
0
CLK[2:3]  
GND NC  
NC GND  
Bank 0  
64Kx36  
Bank 0 and Bank 1  
128KX36  
9270/71A  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
August 15, 1997  
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
LogicBlockDiagram- CYM9271B/CYM9272A  
A[16:0]  
(2) 128K x 18 SRAM’S  
A16:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE0  
CS0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
BWE  
WEH  
WEL  
ADSP  
CLK[0:3]  
ADSC  
CLK  
Bank 0  
CLK[0:1]  
(2) 128K x 18 SRAM’S  
A16:0  
SGW  
OE  
OE1  
CS1  
D[0:15]  
DQ[0:1]  
CS  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank 1  
CLK[2:3]  
9271B/72A  
PD  
PD  
1
0
Bank 0  
NC  
GND  
128Kx36  
256KX36  
GND GND Bank 0 and Bank 1  
2
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
LogicBlockDiagram- CYM9272B/CYM9273  
A[17:0]  
(2) 256K x 18 SRAM’S  
A17:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[0]  
BWE  
WEH  
WEL  
ADSP  
CLK[0:3]  
ADSC  
CLK  
Bank 0  
CLK[0:1]  
(2) 256K x 18 SRAM’S  
A17:0  
SGW  
OE1  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[1]  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank 1  
CLK[2:3]  
9272/73  
PD  
1
PD  
0
Bank 0  
256KX36  
512KX36  
GND GND  
Bank 0 and 1  
NC NC  
3
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
PinConfiguration  
Dual Read-Out SIMM (DIMM)  
Top View  
1
3
2
4
6
8
GND  
A1  
GND  
A0  
A2  
A3  
5
A4  
VCC3  
NC  
NC  
GND  
A6  
A8  
A10  
A5  
VCC3  
NC  
NC  
GND  
A7  
7
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
A9  
A11  
NC  
NC  
VCC3  
A13  
VCC3  
A12  
A14  
A16  
A15  
A17  
GND  
GND  
PD0  
PD  
1
GND  
GND  
BW[0]  
CS[0]  
BW[1]  
OE[0]  
GND  
CLK0  
GND  
D1  
VCC3  
D3  
D5  
D7  
GND  
GND  
CLK1  
GND  
45  
47  
49  
51  
53  
55  
57  
59  
D0  
VCC3  
D2  
D4  
58  
60  
D6  
GND  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
61  
63  
65  
67  
69  
71  
VCC3  
D9  
D11  
GND  
D13  
D15  
VCC3  
D8  
D10  
GND  
D12  
D14  
DQ0  
NC  
NC  
DQ  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
NC1  
NC  
GND  
WE  
GND  
ADSP  
NC  
VCC3  
NC  
NC  
NC  
NC  
VCC3  
NC  
NC  
NC  
V
V
CC3  
NCCC3  
NC  
NC  
NC  
NC  
GND  
BW[2]  
CS[1]  
NC  
GND  
BW[3]  
OE[1]  
VCC3  
VCC3  
D17  
D16  
D18  
NC  
NC  
NC  
GND  
CLK3  
GND  
D20  
GND  
D22  
D24  
D26  
D28  
D19  
NC  
NC  
NC  
GND  
CLK2  
GND  
D21  
GND  
D23  
D25  
D27  
D29  
VCC3  
VCC3  
D30  
D31  
DQ3  
DQ2  
142  
144  
141  
143  
GND  
GND  
4
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
Pin Definitions  
Signal  
Description  
V
3V Supply  
CC3  
GND  
Ground  
A[17:0]  
ADSP  
OE[1:0]  
BW[0:3]  
WE  
Addresses from processor  
Address strobe from the processor  
Output Enables for each of the banks  
Byte writes  
Global Write  
CS[1:0]  
Chip Select for the two banks.  
Presence Detect output pins  
Data lines from processor  
Data Parity lines from processor  
Clock lines to the module.  
Signal not connected on module  
Reserved  
PD -PD  
0
1
D[31:0]  
DQ[3:0]  
CLK[0:3]  
NC  
RSVD  
Presence Detect Pins  
PD  
PD  
0
1
CYM9270 - 64K x 36  
CYM9271 - 128K x 36  
CYM9272 - 256K x 36  
CYM9273 - 512K x 36  
GND  
NC  
NC  
GND  
GND  
NC  
GND  
NC  
5
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
DC Input Voltage ........................................... –0.5V to +4.6V  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature ................................. –55°C to +125°C  
Ambient  
Ambient Temperature  
with Power Applied ........................................ –0°C to +70°C  
Range  
Temperature  
V
CC  
Commercial  
0°C to +70°C  
3.3V ± 5%  
3.3V Supply Voltage to Ground Potential...... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State .............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
Max.  
Unit  
V
V
2.2  
–0.3  
2.4  
V
+ 0.3  
CC  
IH  
V
V
V
0.8  
V
IL  
V
V
V
=Min. I = −4 mA  
V
OH  
CC  
CC  
CC  
OH  
=Min. I = 8 mA  
0.4  
V
OL  
OL  
I
I
I
I
V
V
V
V
Operating Supply Current  
Operating Supply Current  
Operating Supply Current  
Operating Supply Current  
=Max., I  
=Max., I  
=Max., I  
=Max., I  
=0 mA, f=f  
=0 mA, f=f  
=0 mA, f=f  
=0 mA, f=f  
=1/t  
=1/t  
=1/t  
=1/t  
TBD  
mA  
cc(9270)  
CC  
CC  
CC  
CC  
OUT  
OUT  
OUT  
OUT  
MAX  
MAX  
MAX  
MAX  
RC  
RC  
RC  
RC  
V
V
V
TBD(64K)  
500(128K)  
mA  
mA  
mA  
cc(9271)  
CC  
CC  
CC  
1000(128K)  
600(256K)  
CC (9272))  
CC (9273)  
1200(256K)  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
Max.  
9270  
9271  
Max.  
Unit  
C
C
C
C
Address Input Capacitance T = 25°C, f = 1 MHz,  
12  
pF  
A
A
V
= 5.0V  
CC  
24(64K x 18)  
7(128K x 18)  
9272  
14(128K x 18)  
10(256K x 18)  
9273  
9270  
9271  
20(256K x18)  
12  
pF  
pF  
Control Input Capacitance  
T = 25°C, f = 1 MHz,  
A
CC  
I
V
= 5.0V  
24(64K x 18)  
8(128K x 18)  
9272  
16(128K x 18)  
10(256K x 18)  
9273  
9270  
9271  
20(256K x 18)  
9
pF  
pF  
Input / Output Capacitance T = 25°C, f = 1 MHz,  
O
A
V
= 5.0V  
CC  
18(64K x 18)  
5(128K x 18)  
9272  
10(128K x 18)  
8(256K x 18)  
9273  
9270  
9271  
16(256K x 18)  
6
pF  
pF  
Clock Capacitance  
T = 25°C, f = 1 MHz,  
A
CLK  
V
= 5.0V  
CC  
6(64K x 18)  
3(128K x 18)  
9272  
9273  
3(128K x 18)  
5(256K x 18)  
5(256K x 18)  
pF  
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
6
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
10%  
R =  
50 Ω  
L
90%  
10%  
R2  
5 pF  
V = 1.5V  
L
INCLUDING  
JIGAND  
≤ 3 ns  
≤ 3 ns  
[2]  
SCOPE  
(a)  
(b)  
Switching Characteristics Over the Operating Range  
CYM9270  
Min. Max.  
CYM9271  
Min. Max.  
CYM9272  
Min. Max.  
CYM9273  
Parameter  
Description  
Clock Cycle Time  
Min.  
12  
4
Max. Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
12  
4
12  
4
12  
4
ns  
ns  
ns  
ns  
ns  
CYC  
CH  
Clock HIGH  
Clock LOW  
4
4
4
4
CL  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
3
3
3
3
AS  
0.5  
0.5  
0.5  
0.5  
AH  
10.3  
10.3  
10.3  
10.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CDV  
DOH  
WES  
WEH  
DS  
3
3
3
3
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
DH  
3.1  
0.5  
CSS  
CSH  
Chip Select Hold After CLK Rise  
OE HIGH to Output High Z  
OE LOW to Output Valid  
[4]  
7
7
7
7
EOZ  
7
7
7
7
EOV  
Notes:  
2. Resistor values for VCCQ=3.3V are R1=317Ω and R2=351Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are at room temperature.  
4.  
tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
7
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
Switching Waveforms  
[5]  
Single Read  
t
t
CL  
t
CYC  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
[6]  
t
t
ADSH  
ADS  
ADSP  
or  
ADSC  
t
t
WEH  
WES  
[7]  
WH, WL  
t
t
DOH  
CDV  
DATA OUT  
Single Write Timing  
t
t
CL  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
t
t
ADSH  
ADS  
ADSC  
t
t
WEH  
WES  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
Notes:  
5. OE is LOW throughout this operation.  
6. If ADSP is asserted while CS is HIGH, ADSP will be ignored.  
7. ADSP has no effect on ADV, WL, and WH if CS is HIGH.  
8
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
Switching Waveforms (continued)  
Output (Controlled by OE)  
DATA OUT  
OE  
t
t
EOV  
EOZ  
Output Timing (Controlled by CS)  
CLK  
t
t
ADSH  
ADS  
t
t
ADS  
ADSH  
ADSC  
CS  
t
t
CSH  
CSS  
t
t
CSH  
CSS  
t
t
CSOZ  
CDV  
DATA OUT  
Output Timing (Controlled by WH/ WL)  
CLK  
t
ADSH  
t
t
t
ADSH  
ADS  
ADS  
ADSC and  
ADSP  
t
t
WES  
WEH  
WH, WL  
t
t
WEOZ  
WEOV  
DATA OUT  
Ordering Information  
Speed(  
Package  
Name  
Operating  
Range  
MHz)  
Ordering Code  
CYM9270PM-50C  
CYM9271APM-50C  
CYM9271BPM-50C  
CYM9272APM-50C  
CYM9272BPM-50C  
CYM9273PM-50C  
Package Type  
Description  
Sync 64K x 36  
50  
PM45  
PM46  
PM45  
PM46  
PM45  
PM46  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
Commercial  
Sync 128K x 36  
Sync 128K x 36  
Sync 256K x 36  
Sync 256K x 36  
Sync 512K x 36  
Document #: 38-M-00083  
9
CYM9270  
CYM9271A/B  
CYM9272A/B  
CYM9273  
PRELIMINARY  
Package Diagrams  
144-Pin Single-Sided DIMM PM45  
144-Pin Dual-Sided DIMM PM46  
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
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