5V80001
MOST® CLOCK INTERFACE
SYNTHESIZERS
External Components
The 5V80001 requires a minimum number of external
components for proper operation.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between each VDD pins and the ground plane, as close to
these pins as possible. For optimum device performance,
the decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
3) The external loop filter components should be mounted
close to the 5V80001 and away from digital signals,
switching power supply components, and other sources of
noise.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
5V80001. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
The value (in pF) of these crystal caps should equal (C -6
L
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
External Loop Filter
An external loop filter is required for operation of the CDR
PLL.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
®
IDT™ MOST CLOCK INTERFACE
3
5V80001
REV A 082906
