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5V80001PGGW3

型号：

5V80001PGGW3

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

294 K

下载PDF手册
DATASHEET  
MOST® CLOCK INTERFACE  
IDT5V80001  
Description  
Features  
The IDT5V80001 is a high performance clock interface for  
use in MOST (Media Oriented Systems Transport)  
enabled systems. It can be used in two modes: generating  
a master clock for the ring, or performing clock/data  
recovery in a slave node.  
• Packaged in 20-pin TSSOP  
®
• -40 to +85°C temperature range (industrial)  
• Compliant to AEC Q100  
• Operating voltage of 3.3 V  
• 5 volt tolerant input for FOT  
• Low jitter generation  
• Power-down tri-state mode  
• Advanced, low-power CMOS process  
Block Diagram  
BYPASS  
FOT_IN  
1
FOT_OUT  
Retiming  
0
MOST_Din  
RESET  
MUX  
0
1
CDR  
PLL  
INPUT_COPY  
RCLK  
X1  
Crystal  
Oscillator  
Master  
PLL  
MCLK  
X2  
OEM  
S1  
S0  
®
IDT™ MOST CLOCK INTERFACE  
1
IDT5V80001 REV S 083109  
IDT5V80001  
MOST® CLOCK INTERFACE  
SYNTHESIZERS  
Pin Assignment  
Frequency Selection Tables  
S1 S0  
Operating  
Frequency (RCLK)  
Mode  
Sampling  
Frequency  
1
2
3
4
5
6
7
8
9
10  
X2  
X1  
NC  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
MOST_Din  
INPUT_COPY  
0
0
1
1
0
1
0
1
45.1584 MHz  
49.152 MHz  
90.3168 MHz  
98.304 MHz  
MOST 25  
MOST 25  
MOST 50  
MOST 50  
44.1 kHz  
48 kHz  
RESET  
VDD  
VDD  
FOT_OUT  
GND  
RCLK  
GND  
44.1 kHz  
48 kHz  
MCLK  
OEM  
S1  
FOT_IN  
S0  
BYPASS  
LFR  
LF  
OEM MCLK Output Source for Retiming Block  
20-pin TSSOP  
0
1
LOW  
RCLK (slave node)  
Running  
MCLK (master node)  
OEM Node Bypass  
FOT_OUT  
Retimed (RCLK) MOST_Din*  
FOT_IN  
0
Slave  
0
1
0
1
1
Master  
Retimed (MCLK) MOST_Din  
FOT_IN  
* FOT_IN must be present in order to generate RCLK and  
Retimed (RCLK) MOST_Din.  
Pin Descriptions  
Pin  
1
Name  
Type  
Pin Description  
X2  
X1  
Input  
Input  
Input  
Connect to 21.504 MHz crystal.  
2
Connect to 21.504 MHz crystal.  
3
RESET  
VDD  
Low to reset CDR PLL. Internal pull-up resistor.  
4
Power Connect to 3.3 V supply.  
5
FOT_OUT  
GND  
Output Output for fiber optic MOST transceiver. 3.3 V LVTTL levels.  
Power Connect to ground.  
6
7
S1  
Input  
Input  
Input  
Frequency select input pin. See table above. No internal pull-up or pull-down  
resistor.  
8
9
FOT_IN  
S0  
Input to device from fiber optic MOST transceiver. 3.3 V LVTTL levels, 5 V  
tolerant.  
Frequency select input pin. See table above. No internal pull-up or pull-down  
resistor.  
®
IDT™ MOST CLOCK INTERFACE  
2
IDT5V80001 REV S 083109  
IDT5V80001  
MOST® CLOCK INTERFACE  
SYNTHESIZERS  
Pin  
10  
Name  
LF  
Type  
Input  
Input  
Input  
Pin Description  
Loop filter connection for CDR PLL.  
Loop filter return. Connected to ground internally.  
11  
LFR  
12  
BYPASS  
MUX control to bypass CDR PLL. Active high. No internal pull-up or pull-down  
resistor.  
13  
14  
OEM  
Input  
High to enable MCLK. See table above. No internal pull-up or pull-down  
resistor.  
MCLK  
Output Master clock output. Clean clock derived from crystal. See table above. Weak  
pull-down when OEM = 0.  
15  
16  
17  
18  
19  
20  
GND  
RCLK  
VDD  
Power Connect to ground.  
Output Recovered clock out. See table above.  
Power Connect to 3.3 V supply.  
INPUT_COPY Output Retimed copy of FOT_IN input.  
MOST_Din  
NC  
Input  
—
MOST data input.  
No Connect. Do not connect this pin to anything.  
Operation  
The IDT5V80001 performs clock generation and recovery  
for either a master or slave node in a MOST ring. It provides  
a interface between a controller (typically implemented in an  
ASIC or FPGA) and the fiber optic transceiver (FOT).  
To recover the clock from the data stream, the two PLLs  
work together. The lock sequence from power on is:  
1. Crystal oscillator starts and stabilizes.  
2. Master (frequency synthesis) PLL starts and locks to the  
crystal.  
3. CDR PLL starts and locks to the master PLL to obtain a  
frequency operation point.  
4. Activity is detected on FOT_IN.  
5. CDR PLL phase-locks to incoming data.  
When used in a Master node (OEM = High), the Master PLL  
synthesizes a frequency of twice the MOST data rate as the  
MCLK output, and also reclocks the data from the controller  
that is input on the FOT_IN pin to the INPUT_COPY output.  
The output data on FOT_OUT is the MOST_Din data  
retimed to MCLK if BYPASS is driven low, or the FOT_IN  
data if BYPASS is driven high. Simultaneously, the device  
recovers the clock from data on the FOT_IN pin and outputs  
a 2x clock on RCLK.  
Extreme conditions, such as electrical transients, phase  
steps or brief dropouts on the FOT_IN pin may cause the  
CDR PLL to unlock. If this occurs and the controller begins  
to experience data errors, it should set RESET low for at  
least 50 ns to restart the data lock sequence from step 3.  
In a slave node, OEM is set low and the MCLK output is  
disabled. Data from the controller (FOT_IN) is retimed using  
the recovered clock and output on the INPUT_COPY. If  
BYPASS is driven high, the controller data (FOT_IN) is also  
transmitted on the FOT_OUT output but is not retimed to  
RCLK. If BYPASS is driven low, the MOST_Din data is  
retimed and transmitted on the FOT_OUT output.  
®
IDT™ MOST CLOCK INTERFACE  
3
IDT5V80001 REV S 083109  
IDT5V80001  
MOST® CLOCK INTERFACE  
SYNTHESIZERS  
External Components  
The IDT5V80001 requires a minimum number of external  
components for proper operation.  
The nominal impedance of the clock output is 20 Ω.  
PCB Layout Recommendations  
Decoupling Capacitor  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
A decoupling capacitor of 0.01µF must be connected  
between each VDD pins and the ground plane, as close to  
these pins as possible. For optimum device performance,  
the decoupling capacitor should be mounted on the  
component side of the PCB.  
1) The 0.01µF decoupling capacitors should be mounted on  
the component side of the board as close to the VDD pin as  
possible. No vias should be used between decoupling  
capacitor and VDD pin. The PCB trace to VDD pin should  
be kept as short as possible, as should the PCB trace to the  
ground via.  
Crystal  
The IDT5V80001 requires a 21.504 MHz parallel resonant  
crystal. Recommended devices are:  
2) The external crystal should be mounted just next to the  
device with short traces.  
Manufacturer  
Abracon  
Package  
Part #  
5x7 mm ceramic  
AAH-363-21.504MHz  
3) The external loop filter components should be mounted  
close to the IDT5V80001 and away from digital signals,  
switching power supply components, and other sources of  
noise.  
NDK  
3.2x5 mm ceramic EXS00A-CG00294  
Crystal Load Capacitors  
The device crystal connections should include pads for  
capacitors from X1 to ground and from X2 to ground. These  
capacitors are used to adjust the stray capacitance of the  
board to match the nominally required crystal load  
capacitance.  
4) To minimize EMI, 33 Ωseries termination resistors should  
be placed close to the clock outputs.  
5) An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers. Other signal traces should be routed away from the  
IDT5V80001. This includes signal traces just underneath  
the device, or on layers adjacent to the ground plane layer  
used by the device.  
The value (in pF) of these crystal caps should equal (C -12  
L
pF)*2. In this equation, C = crystal load capacitance in pF.  
L
For the specified 16 pF load capacitance, each crystal  
capacitor would be 8 pF [(16-12) x 2 = 8].  
External Loop Filter  
External Loop Filter  
An external loop filter is required for operation of the CDR  
PLL. Recommended components are:  
9
12  
11  
R = 1210 Ω, 1% tolerance  
10  
LFR  
LF  
S
C = 10 nF, use capacitor with a non-piezoelectric dielectric.  
S
Recommended type is Panasonic ECH-U01103GX5 or  
equivalent.  
RS  
CS  
Series Termination Resistor  
Termination should be used on the FOT_OUT, MCLK,  
RCLK, and INPUT_COPY output (pins 5, 14, 16, and 18  
respectively). To series terminate a 50 Ωtrace (a commonly  
used trace impedance) place a 33 Ω resistor in series with  
the clock line, as close to the clock output pin as possible.  
®
IDT™ MOST CLOCK INTERFACE  
4
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT5V80001. These ratings, which  
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at  
these or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical  
parameters are guaranteed only over the recommended operating temperature range.  
Item  
Rating  
Supply Voltage, VDD  
Inputs and Outputs  
Input (FOT_IN only)  
Storage Temperature  
Junction Temperature  
Soldering Temperature  
7 V  
-0.5 V to VDD+0.5 V  
7 V  
-65 to +150° C  
125°C  
260°C  
Recommended Operation Conditions  
Parameter  
Min.  
-40  
Typ.  
Max.  
+85  
+3.6  
4
Units  
°C  
Ambient Operating Temperature  
Power Supply Voltage (measured with respect to GND)  
Power Supply Ramp Time  
+3.0  
+3.3V  
V
ms  
®
IDT™ MOST CLOCK INTERFACE  
5
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C  
Parameter  
Symbol  
Conditions  
Min.  
Typ.  
Max.  
Units  
Operating Supply Current  
IDD  
No load, F  
= 49.152 MHz  
35  
mA  
RCLK  
FOT_IN, MOST_Din  
2
5.5  
High Level Input Voltage  
Low Level Input Voltage  
High Level Output Voltage  
Low Level Output Voltage  
V
V
RESET, BYPASS, OEM, S0,  
S1  
2.0  
VDD+0.3  
IH  
FOT_IN, MOST_Din  
-0.3  
-0.3  
0.8  
0.8  
V
V
V
V
RESET, BYPASS, OEM, S0,  
S1  
IL  
FOT_OUT only, I = -2 mA  
2.4  
OH  
V
MCLK, RCLK, INPUT_COPY VDD-0.2  
= -100 µA  
OH  
I
OH  
FOT_OUT only, I = 2 mA  
0.4  
0.2  
OH  
V
MCLK, RCLK, INPUT_COPY  
OL  
I
= 100 µA  
OH  
Short Circuit Current  
Input Capacitance  
I
FOT_OUT  
35  
5
mA  
pF  
OS  
C
FOT_IN, MOST_Din, RESET,  
BYPASS, OEM, S0, S1  
10  
IN  
Nominal Output Impedance  
Z
FOT_OUT, MCLK, RCLK,  
INPUT_COPY  
20  
Ω
OUT  
On-Chip Pull-up or  
Pull-down Resistor  
R
RESET  
500  
kΩ  
P
®
IDT™ MOST CLOCK INTERFACE  
6
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Timing Requirements  
Parameter  
Symbol  
Conditions  
Min.  
Typ.  
Max.  
Units  
Crystal Frequency  
F
21.504  
MHz  
IN  
S1=0, S0=0 (See Fig. 1)  
S1=0, S0=1 (See Fig. 1)  
S1=1, S0=0 (See Fig. 1)  
S1=1, S0=1 (See Fig. 1)  
S1=0, S0=0 (See Fig. 1)  
S1=0, S0=1 (See Fig. 1)  
S1=1, S0=0 (See Fig. 1)  
S1=1, S0=1 (See Fig. 1)  
S1=0, S0=0 (See Fig. 2)  
S1=0, S0=1 (See Fig. 2)  
S1=1, S0=0 (See Fig. 2)  
S1=1, S0=1 (See Fig. 2)  
S1=0, S0=0 (See Fig. 2)  
S1=0, S0=1 (See Fig. 2)  
S1=1, S0=0 (See Fig. 2)  
S1=1, S0=1 (See Fig. 2)  
S1=0, S0=0 (See Fig. 3)  
S1=0, S0=1 (See Fig. 3)  
S1=1, S0=0 (See Fig. 3)  
S1=1, S0=1 (See Fig. 3)  
S1=0, S0=0 (See Fig. 4)  
S1=0, S0=1 (See Fig. 4)  
S1=1, S0=0 (See Fig. 4)  
S1=1, S0=1 (See Fig. 4)  
(see Fig. 5)  
10.0  
9.2  
Input Rise Time  
Input Fall Time  
t
ns  
R
5.0  
4.6  
10.0  
9.2  
t
ns  
ns  
ns  
ns  
F
5.0  
4.6  
16.4  
15.1  
8.2  
7.5  
-3.4  
-3.1  
-1.7  
-1.6  
0
31.1  
28.5  
15.6  
14.3  
+7.0  
+6.5  
+3.5  
+3.3  
3.4  
Input Pulse Width Variation  
(FOT_IN and MOST_Din)  
t
PWV  
Average Input Pulse Width  
Distortion  
(FOT_IN and MOST_Din)  
t
APWD  
0
3.1  
One-Sigma Data  
Dependent Jitter (FOT_IN)  
t
DDJ  
0
1.7  
0
1.6  
0
1000  
920  
500  
460  
0
One-Sigma Uncorrelated  
Jitter  
t
ps  
ns  
UJ  
0
0
CDR Reset Time  
t
50  
RESET  
®
IDT™ MOST CLOCK INTERFACE  
7
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Timing Diagrams  
2UI + tPWV(MAX)  
2UI + tPWV(MIN)  
1UI + tPWV(MAX)  
1UI + tPWV(MIN)  
tPWV(MAX)  
tPWV(MIN)  
tF  
tR  
VDD  
90% of VDD  
tAPWD  
tAPWD  
tAPWD  
10% of VDD  
0V  
VOH  
Signal  
1.5 V  
VOL  
1UI  
2UI (bit period)  
3UI (occurs at preambles)  
Figure 1: Rise and Fall Time Definitions  
Figure 2: Pulse Width Variation and Average Pulse Width  
Distortion  
tDDJ  
node n  
tUJ  
Tx  
node n  
(node n-1)  
Trigger  
Tx  
(node n-1)  
Figure 3: Data Dependent Jitter  
Trigger  
Figure 4: Uncorrelated Jitter  
VDD  
0V  
RESET  
1.5 V  
1.5 V  
tRESET  
Output  
VDDs  
RLOAD  
2 kOhm  
0.1µF  
CLOAD  
10pF  
DUT  
RCLK  
RCLK locked to  
MOST data  
RCLK locked to  
MCLK  
GND  
Figure 6: Test and Measurement Setup  
Figure 5: RESET Timing Definition  
®
IDT™ MOST CLOCK INTERFACE  
8
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Power Up  
Time  
VCO Ramp  
Time  
PLL Locked  
t1  
VDD  
t2  
VDD  
1.5 V  
0V  
0V  
Clock  
Output  
VDD  
t2  
t1  
Duty Cycle, D=  
RCLK  
0V  
Figure 7: Duty Cycle Definitions  
0 ms  
tCLOCK  
tDLOCK  
Note: FOT_IN must be running and stable during VCO ramp time.  
1.5 V  
FOT_IN  
Figure 8: Power Up and PLL Lock Timing  
tPD  
1.5 V  
FOT_OUT  
FOT_IN  
t
CDR  
Note: RESET = H, BYPASS = H, OEM = L or H  
RCLK  
Figure 9: Propagation Delay  
t
t
SK  
JIT  
INPUT_COPY  
RESET  
OEM  
Figure 10: Clock Timing  
FOT_IN  
FOT_IN data  
Coding  
Violation  
0
0
1
1
0
1
MOST_Din  
BYPASS  
MOST_Din data  
VDD  
0V  
MOST Input  
(retimed)  
1.5 V  
tBHL  
1.5 V  
tBLH  
Recovered  
Clock  
FOT_IN data  
FOT_OUT  
FOT_IN data  
MOST_Din data  
Figure 12: MOST Data–Clock Example  
Figure 11: BYPASS Timing Definition  
®
IDT™ MOST CLOCK INTERFACE  
9
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
AC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85° C  
Parameter  
Symbol  
Conditions  
Min. Typ. Max. Units  
Crystal Frequency  
FIN  
21.504  
MHz  
ppm  
%
Output Frequency Error  
Output Clock Duty Cycle  
Due to frequency synthesis  
Figures 6 and 7  
0
D
45  
50  
55  
5.0  
S1=0, S0=0 (See Fig. 1)  
S1=0, S0=1 (See Fig. 1)  
S1=1, S0=0 (See Fig. 1)  
S1=1, S0=1 (See Fig. 1)  
S1=0, S0=0 (See Fig. 1)  
S1=0, S0=1 (See Fig. 1)  
S1=1, S0=0 (See Fig. 1)  
S1=1, S0=1 (See Fig. 1)  
S1=0, S0=0 (See Fig. 2)  
S1=0, S0=1 (See Fig. 2)  
S1=1, S0=0 (See Fig. 2)  
S1=1, S0=1 (See Fig. 2)  
S1=0, S0=0 (See Fig. 2)  
S1=0, S0=1 (See Fig. 2)  
S1=1, S0=0 (See Fig. 2)  
S1=1, S0=1 (See Fig. 2)  
S1=0, S0=0 (See Fig. 3)  
S1=0, S0=1 (See Fig. 3)  
S1=1, S0=0 (See Fig. 3)  
S1=1, S0=1 (See Fig. 3)  
S1=0, S0=0 (See Fig. 4)  
S1=0, S0=1 (See Fig. 4)  
S1=1, S0=0 (See Fig. 4)  
S1=1, S0=1 (See Fig. 4)  
4.6  
Output Rise Time  
Output Fall Time  
tR  
ns  
ns  
ns  
ps  
ps  
ps  
2.5  
2.3  
5.0  
4.6  
tF  
2.5  
2.3  
21.2  
19.5  
10.6  
9.8  
-500  
-460  
-250  
-230  
0
23.1  
21.2  
11.5  
10.6  
+500  
+460  
+250  
+230  
220  
200  
110  
100  
95  
Output Pulse Width Variation  
(FOT_OUT)  
tPWV  
tAPWD  
tDDJ  
tUJ  
Average Output Pulse Width Distortion  
(FOT_OUT)  
0
One-Sigma Data dependent Jitter (RCLK)  
0
0
0
0
90  
One-Sigma Uncorrelated Jitter (RCLK)  
Power-up Time  
0
45  
0
45  
tCLOCK  
tDLOCK  
PLL lock-time from 90% VDD  
to RCLK = MCLK, (see Fig. 8)  
200  
µs  
µs  
PLL lock-time from beginning  
of FOT_IN input to stable  
RCLK output, (see Fig. 8)  
400  
Propagation Delay (FOT_IN to FOT_OUT)  
Propagation Delay (FOT_IN to RCLK)  
Skew, recovered clock to retimed input  
One-Sigma Clock Period Jitter  
tPD  
tCDR  
tSK  
(see Fig. 9)  
(see Fig. 10)  
(see Fig. 10)  
MCLK  
3
4
TBD  
0
5
ns  
ns  
ps  
ps  
TBD  
-250  
0
TBD  
+250  
50  
®
IDT™ MOST CLOCK INTERFACE  
10  
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Parameter  
Symbol  
Conditions  
Min. Typ. Max. Units  
RCLK Peak-to-peak Jitter with respect to  
FOT_IN  
tJIT  
-500  
0
+500  
ps  
BYPASS High-to-Low to FOT_OUT  
BYPASS Low-to-High to FOT_OUT  
tBHL  
tBLH  
(see Fig. 11)  
TBD  
TBD  
TBD  
TBD  
ns  
ns  
(see Fig. 11)  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
θ
θ
θ
Still air  
93  
78  
65  
20  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
JA  
JA  
JC  
1 m/s air flow  
3 m/s air flow  
Thermal Resistance Junction to Case  
®
IDT™ MOST CLOCK INTERFACE  
11  
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Marking Diagrams  
20  
11  
IDT5V800  
01PGGI  
ZYYWW$  
10  
11  
1
20  
IDT5V800  
W3  
01PGGI  
ZYYWW$  
10  
1
Notes:  
1. “Z” is the device step (1 to 2 characters).  
2. YYWW is the last two digits of the year and week that the part was assembled.  
3. “$” is the assembly mark code.  
4. “G” after the two-letter package code designates RoHS compliant package.  
5. “I” at the end of part number indicates industrial temperature range.  
6. ‘W3’ denotes automotive grade.  
7. Bottom marking: country of origin if not USA.  
®
IDT™ MOST CLOCK INTERFACE  
12  
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Package Outline and Package Dimensions (20-pin TSSOP, 4.4mm Narrow Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches*  
20  
Symbol  
Min Max  
Min  
Max  
A
A1  
A2  
b
--  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
--  
0.047  
0.006  
0.041  
0.012  
0.05  
0.80  
0.19  
0.09  
6.40  
6.40 BASIC  
4.30 4.50  
0.65 Basic  
0.002  
0.032  
0.007  
0.0035 0.008  
0.252 0.260  
0.252 BASIC  
0.169 0.177  
0.0256 Basic  
E1  
E
INDEX  
AREA  
C
D
E
E1  
e
L
1 2  
D
0.45  
0.75  
0.018  
0.030  
α
0°  
8°  
0°  
8°  
aaa  
--  
0.10  
--  
0.004  
*For reference only. Controlling dimensions in mm.  
A
A2  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
see page 8  
Shipping Packaging  
Tubes  
Package  
Temperature  
-40 to +85° C  
-40 to +85° C  
-40 to +85° C  
-40 to +85° C  
5V80001PGGI  
5V80001PGGI8  
5V80001PGGW3  
5V80001PGGW38  
20-pin TSSOP  
20-pin TSSOP  
20-pin TSSOP  
20-pin TSSOP  
Tape and Reel  
Tubes  
Tape and Reel  
see page 8  
Parts that are ordered with a “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
‘W3’ denotes automotive grade.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
®
IDT™ MOST CLOCK INTERFACE  
13  
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Revision History  
Rev. Originator  
Date  
Description of Change  
A
B
C
J. Gazda  
J. Gazda  
J. Gazda  
08/29/06 Preliminary datasheet.  
09/19/06 Changed block diagram and pinout;  
09/25/06 Changed from 16-pin TSSOP to 20-pin TSSOP; added timing diagrams; changed pinout  
and block diagrams.  
D
E
F
G
H
J
J. Gazda  
J. Gazda  
J. Gazda  
J. Gazda  
J. Gazda  
J. Gazda  
J. Gazda  
09/27/06 New block diagram; changed pinout; added Propagation Delay, Skew, and Clock Jitter  
specs; changed High/Low Input/Output level specs.  
11/02/06 Changed temperature rating from -40/+85 to -40/+105 °C; added “Mode” and “Sampling  
Frequency” to Frequency Selection Table.  
12/14/06 Added “Operation” section; added “External Loop Filter” diagram; added RESET# pin;  
various modifications to “External Components” text.  
02/15/07 Added Feature bullet of “5 V tolerant input for FOT”; add crystal caps and ground to block  
diagram; added “Weak pull-down when OEM=0” statement to MCLK pin description.  
03/22/07 Added NDK crystal part number; changed “MCLK” to “RCLK” in the conditions for “Data to  
clock jitter” spec.  
05/31/07 Removed CP reference on External Loop Filter descriptions; removed one capacitor from  
“CDR PLL” in Block Diagram.  
K
06/22/07 Reversed ’1’ and ‘0’ on the MUX in the block diagram; removed the bar from “BYPASS”;  
added the text “No pull-up” to pin descriptions 7, 9, 12, and 13; removed “Data to clock  
jitter” spec from AC char table.  
L
J. Gazda  
T. Nana  
10/09/07 Removed “Lock” pin.  
M
12/17/07 Updates to timing diagrams; added “Timing Requiremnets” table; updates to pin  
descriptions; multiple updates to AC/DC char tables; added Figure 7.  
N
T. Nana  
12/26/07 Updates to Block Diagram and Timing diagrams; added new “Operation” information;  
added another OEM table for BYPASS and FOT_OUT; updates to AC/DC char tables and  
“Timing Requirementts” table; added “Reset Timing Definition” (Fig. 8) and “BYPASS  
Timing Definition” (Fig. 9) diagrams.  
P
T. Nana  
T. Nana  
01/08/08 Updates to DC Electrical Char table; One-Sigma Jitter specs added to “Timing  
Requirements” table; updates to Timing Diagrams; added jitter and propagation delay  
timing diagrams; added One-Sigma Jitter specs to AC Electrical Char table;  
Q
02/06/08 Removed OEM and MUX from Block Diagram; updates to "Operation" text; updated  
"Propagation Delay" diagram; added additional “Propagation Delay” spec to AC char  
table.  
R
S
11/14/08 Moved from Preliminary to Released.  
D.L.  
08/31/09 Added automotive grade ordering info and marking diagram  
®
IDT™ MOST CLOCK INTERFACE  
14  
IDT5V80001 REV S 083109  
IDT5V80001  
®
MOST CLOCK INTERFACE  
SYNTHESIZERS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device  
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered  
trademarks used to identify products or services of their respective owners.  
Printed in USA  
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