CYIFS741
Regulatory agencies test electronic equipment by the amount of
peak energy radiated from the equipment. By reducing the peak
energy at the fundamental and harmonics, the equipment under
test is able to satisfy agency requirements for Electro-Magnetic
Interference (EMI). Conventional methods of reducing EMI have
been to use shielding, filtering, multi-layer PCB’s etc. The
CYIFS741 uses the approach of reducing the peak energy in the
clock by increasing the clock bandwidth, and lowering the Q.
Theory of Operation
The CYIFS741 is a Phase Lock Loop (PLL) type clock generator
using Direct Digital Synthesis (DDS). By precisely controlling the
bandwidth of the output clock, the CYIFS741 becomes a Low
EMI clock generator. The theory and detailed operation of the
CYIFS741 will be discussed in the following sections.
EMI
SSCG
All clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of the 50/50 duty cycle, digital
clocks generate most of their harmonic energy in the odd
harmonics, i.e.; 3rd, 5th, 7th etc. It is possible to reduce the
amount of energy contained in the fundamental and harmonics
by increasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor, which
means that all of the energy at that frequency is concentrated in
a very narrow bandwidth, consequently, higher energy peaks.
The CYIFS741 uses a proprietary technique to modulate the
clock over a very narrow bandwidth and controlled rate of
change, both peak and cycle to cycle. The CYIFS741 takes a
narrow band digital reference clock in the range 4–68 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand what
happens to an SSCG clock, consider that we have a 20 MHz
clock with a 50% duty cycle. From a 20 MHz clock we know the
following.
Figure 5. SSCG clock
Consider that this 20 MHz clock is applied to the Xin input of the
CYIFS741, either as an externally driven clock or as the result of
a parallel resonant crystal connected to pins 1 and 2 of the
CYIFS741. Also consider that the CYIFS741 is operating from a
5 Volt DC power supply and the loop filter is set for a total
bandwidth spread of 2%. Refer to Table 1 on page 7.
Figure 6. Perfect clock with no noise
From the above parameters, the output clock at Modout will be
sweeping symmetrically around a center frequency of 20 MHz.
The minimum and maximum extremes of this clock will be
+200 kHz and –200 kHz. So, we have a clock that is sweeping
from 19.8 MHz to 20.2 MHz and back again. If we were to look
at this clock on a spectrum analyzer we would see the picture in
Figure 6. Keep in mind that this is a drawing of a perfect clock
with no noise.
We see that the original 20 MHz reference clock is at the center
Frequency, FC, and the minimum and maximum extremes are
positioned symmetrically about the center frequency. This type
of modulation is called Center-Spread. Figure 6 illustrates this as
it is seen on a spectrum analyzer.
Figure 7 on page 11 shows a 20 MHz clock as it would be seen
on an oscilloscope. The top trace is the non-modulated reference
clock, or the Refout clock at pin 7. The bottom trace is the
modulated clock at pin 6. From this comparison chart you can
see that the frequency is decreasing and the period of each
successive clock increasing. The TC measurements on the left
and right of the bottom trace indicate the max. and min. extremes
of the clock. Intermediate clock changes are small and
accumulate to achieve the total period deviation. The reverse of
Document Number: 001-73430 Rev. *A
Page 10 of 19
