CYIA2SC0300AA-BQE
Table 1. IM103 Pin Assignments(continued)
Pin Name
GNDA
[3]
[4]
Function
Class
Type
GND
O
B8,C9,C10
B10
Analog Ground
P
A
P
VREFP
VDDA
Positive A/D Ref. Voltage Capacitor
Analog Power
A8,A9,B9
PWR
The major pin groups are described below:
GPIO: This pin is used primarily for test purposes during
manufacturing. The pin can also be enabled with certain
register settings to acquire data for noise correction. If the pin
is not being used for noise correction, the recommended
configuration is to tie it to ground through a 1-Mohm resistor.
Digital I/O (D0-D7): These eight pins are bidirectional,
tri-stateable digital I/O pins. The state of the pins is determined
by WE and OE. In output mode, the eight pins are used to send
image data out of the sensor to the system; in input mode, the
eight pins are used to receive programming data for the
on-chip registers.
Analog Reference Pins (VREFM, VREFP, VCM): These pins
are used to connect bypass capacitors for the three voltage
references: negative reference (VREFM), positive reference
(VREFP), and analog common-mode (VCM). The recom-
mended bypass circuit is shown in Figure 3.
Write Enable and Output Enable (WE and OE): These two
pins control the digital I/O pins. They determine whether the
I/O pins are in programming, output, or high-impedance
(tri-state) mode. Table 2 presents the I/O state as a function of
WE and OE settings.
The 3 analog references should be bypassed with at least
0.1-µF ceramic capacitors. Cypress recommends the use of
0402-sized chip capacitors placed as close as possible to the
package and sharing GNDA as the common node.
Table 2. Data I/O Table
WE
OE
Data I/O State
VDDA
HIGH
LOW
HIGH
LOW
HIGH Tri-state
HIGH Input (write) enabled
LOW Output (data out) enabled
LOW Undefined
VDDIO
VREFP
GNDA
VREFM
VCM
Note: To minimize temporal noise the use of tri-state mode
should be avoided during active operation of the image sensor.
Either (a) active driving of the data bus or (b) use of pull-ups
to define a known logic level is recommended during active
operation. Tri-state mode can be used when the image sensor
is in standby.
VDDD
RESET: This pin is used to initialize the sensor. It is normally
HIGH during operation, and should be brought LOW for at
least 100 µs to initialize the sensor and set the default register
values.
Figure 3. Bypass capacitor circuit for VREFM, VREFP,
VCM, VDDIO and VDDA. Recommended bypasscapacitor
value is 0.1 µF.
The RESET signal also may be used as a chip enable. When
RESET is LOW, the image sensor goes into sleep mode.
Standby power in this situation is <0.5 mW. The sensor is
brought out of sleep mode by setting RESET to HIGH.
Supply pins (VDDD, VDDIO, VDDA): These three pins
separately supply power for digital circuitry (VDDD), I/O
(VDDIO), and analog circuitry (VDDA). The supplies are run
on separate busses on the chip but are connected through
ESD blocking diodes. Because of the ESD protection diodes,
the three voltages should be kept at the same value.
Data Strobe (DSTR) and System Clock (SCLK): These two
clocks control the sensor. DSTR is used primarily to clock data
out of the data shift registers. SCLK controls the row, frame,
column circuit, and data conversion timings, as well as the
program registers. The clocks can be asynchronous, but
DSTR frequency must be at least 15X SCLK for 8-bit output
format, and at least 22X SCLK for 12-bit output format.
Clocking is described in more detail in section 5.
Grounds (GNDD, GNDIO, GNDA): These three pins
separately supply grounds for digital circuitry (GNDD), I/O
(GNDIO), and analog circuitry (GNDA). The grounds run
separately in metal, but are tied together through the silicon
substrate in the circuit.
Row Synchronization (ROW): This digital output pin
provides a signal that goes HIGH at the end of each row
readout. The signal goes LOW at the start of the next row.
Document #: 001-11358 Rev. **
Page 3 of 18
