WV3HG64M64EEU-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol Proposed Conditions
Operating one bank active-precharge current;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
806
665
534
403
Units
ICC0*
t
800
760
mA
TBD
TBD
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
ICC1*
880
800
mA
TBD
TBD
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
64
64
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
200
240
200
240
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
240
120
240
120
mA
mA
TBD
TBD
TBD
TBD
All banks open; tCK = tCK(ICC); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
ICC3P**
ICC3N**
ICC4W**
ICC4R*
ICC5B**
ICC6*
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
560
1600
1440
1560
44
520
1160
1160
1480
44
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
=
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK
= tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
Normal
FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
=
ICC7*
2200
2160
mA
TBD
TBD
* Value calculated as one module rank in thes operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition
NOTES:
• ICC specifications were calculated using SAMSUNG components. Other manufactures DRAMs may have different values.
October 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
