WV3EG232M64EFSU-D4
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION
SYMBOL
UNITS
DDR333 DDR266 DDR266
@CL=2.5 @CL=2 @CL=2.5
Operating current – One bank Active-Precharge; tRC = tRC(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
IDD0
1160
1000
1000
mA
Operating current – One bank operation ; One bank open, BL=4, Reads — Refer to the following
page for detailed test condition
IDD1
IDD2P
IDD2F
1360
48
1200
48
1200
48
mA
mA
mA
Percharge power-down standby current; All banks idle; power-down mode; CKE ≤ VIL(max); tCK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
Precharge Floating standby current; CS# ≥ VIH(min);All banks idle; CKE ≥ VIH(min); tCK
=
400
320
320
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
Precharge Quiet standby current; CS# ≥ VIH(min); All banks idle; CKE ≥ VIH(min); tCK = 100Mhz
for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with
keeping ≥ VIH(min) or ≤ VIL(max); VIN = VREF for DQ ,DQS and DM
IDD2Q
320
290
290
mA
Active power - down standby current ; one bank active; power-down mode; CKE ≤ VIL (max);
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
IDD3P
IDD3N
560
880
480
720
480
720
mA
mA
Active standby current; CS# ≥ VIH(min); CKE ≥ VIH(min); one bank active; active - precharge;
tRC = tRAS(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and
DM inputs changing twice per clock cycle; address and other control inputs changing once per
clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active;
address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200,
CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data
changing at every burst; lOUT = 0mA
IDD4R
1720
1720
1480
1440
1480
1440
mA
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active
address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200,
CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B; DQ, DM and
DQS inputs changing twice per clock cycle, 50% of input data changing at every burst
IDD4W
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
IDD5
IDD6
1800
48
1640
48
1640
48
mA
mA
mA
Self refresh current; CKE ≤ 0.2V; External clock should be on; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B
Orerating current - Four bank operation ; Four bank interleaving with BL=4
— Refer to the following page for detailed test condition
IDD7A
2680
2360
2360
Note: IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
April 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
