IDT5V50012
CRYSTAL-FREE CLOCK SOURCE
SYNTHESIZERS
External Components
The IDT5V50012 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between each VDD and GND, as close to these pins as
possible. For optimum device performance, the decoupling
capacitor should be mounted on the component side of the
PCB. Avoid the use of vias in the decoupling circuit.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
Series Termination Resistor
2) To minimize EMI, the 33Ω series termination resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5V50012. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
IDT™ CRYSTAL-FREE CLOCK SOURCE
4
IDT5V50012
REV B 061807