IDT5V50009
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Crystal Information
External Components
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
The IDT5V50009 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Crystal caps (pF) = (C - 6) x 2
L
In the equation, C is the crystal load capacitance. So, for a
L
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50Ωtrace (a commonly used trace impedance)
place a 33Ωresistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω.
Spread Spectrum Profile
The IDT5V50009 low EMI clock generator uses an
optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Modulation Rate
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
T i m e
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5V50009. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
IDT™ SPREAD SPECTRUM CLOCK GENERATOR
3
IDT5V50009 REV C 040609
