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9UMS9633BKILF

型号：

9UMS9633BKILF

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

22 页

PDF大小：

211 K

下载PDF手册
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL  
TEMPERATURE RANGE  
ICS9UMS9633BI  
Recommended Application:  
Features/Benefits:  
•
Industrial temperature range compliant  
Poulsbo Based Ultra-Mobile PC (UMPC) for Industrial  
Temperature Range  
•
Supports ULV CPUs with 67 to 167 MHz  
CPU outputs  
Output Features:  
•
Dedicated TEST/SEL and TEST/MODE pins  
saves isolation resistors on pins  
•
•
•
3 - CPU low power differential push-pull pairs  
3 - SRC low power differential push-pull pairs  
•
•
•
CPU STOP# input for power manangment  
Fully integrated Vreg  
1 - LCD100 SSCD low power differential  
push-pull pair  
Integrated series resistors on differential  
outputs  
•
•
1 - DOT96 low power differential push-pull  
pair  
•
•
1.5V VDD IO operation, 3.3V VDD core and  
REF supply pin for REF  
1 - REF, 14.31818MHz, 3.3V SE output  
-40 to +85C operating range  
SSOP Pin Configuration  
REF 1  
GNDREF 2  
48 VDDREF_3.3  
47 X1  
VDDCORE_3.3 3  
FSC_L 4  
TEST_MODE 5  
TEST_SEL 6  
SCLK 7  
46 X2  
45 CLKPWRGD#/PD_3.3  
44 CPU_STOP#  
43 CPUT0_LPR  
42 CPUC0_LPR  
41 VDDIO_1.5  
40 GNDCPU  
39 CPUT1_LPR  
38 CPUC1_LPR  
37 VDDCORE_3.3  
36 VDDIO_1.5  
35 GNDCPU  
SDATA 8  
VDDCORE_3.3 9  
VDDIO_1.5 10  
DOT96C_LPR 11  
DOT96T_LPR 12  
GNDDOT 13  
GNDLCD 14  
LCD100C_LPR 15  
LCD100T_LPR 16  
VDDIO_1.5 17  
VDDCORE_3.3 18  
*CR#0 19  
34 CPUT2_LPR  
33 CPUC2_LPR  
32 FSB_L  
31 *CR#2  
30 SRCT2_LPR  
29 SRCC2_LPR  
28 GNDSRC  
27 SRCT1_LPR  
26 SRCC1_LPR  
25 VDDIO_1.5  
GNDSRC 20  
SRCC0_LPR 21  
SRCT0_LPR 22  
*CR#1 23  
VDDCORE_3.3 24  
48 SSOP Package  
* indicates inputs with internal pull up of ~10Kohm to 3.3V  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
1
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
SSOP Pin Description  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
1
2
3
REF  
GNDREF  
VDDCORE_3.3  
OUT 14.318 MHz reference clock.  
PWR Ground pin for the REF outputs.  
PWR 3.3V power for the PLL core  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values.  
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode  
while in test mode. Refer to Test Clarification Table.  
TEST_SEL: latched input to select TEST MODE  
1 = All outputs are tri-stated for test  
4
5
FSC_L  
IN  
IN  
TEST_MODE  
TEST_SEL  
6
IN  
IN  
0 = All outputs behave normally.  
Clock pin of SMBus circuitry, 5V tolerant.  
7
8
9
SCLK  
SDATA  
VDDCORE_3.3  
I/O Data pin for SMBus circuitry, 3.3V tolerant.  
PWR 3.3V power for the PLL core  
10 VDDIO_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm  
resistor to GND needed. No Rs needed.  
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor  
to GND needed. No Rs needed.  
11 DOT96C_LPR  
12 DOT96T_LPR  
OUT  
OUT  
13 GNDDOT  
14 GNDLCD  
PWR Ground pin for DOT clock output  
PWR Ground pin for LCD clock output  
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm  
resistor to GND needed. No Rs needed.  
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to  
GND needed. No Rs needed.  
15 LCD100C_LPR  
16 LCD100T_LPR  
OUT  
OUT  
17 VDDIO_1.5  
18 VDDCORE_3.3  
19 *CR#0  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 3.3V power for the PLL core  
IN  
Clock request for SRC0, 0 = enable, 1 = disable  
20 GNDSRC  
PWR Ground pin for the SRC outputs  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
21 SRCC0_LPR  
22 SRCT0_LPR  
OUT  
OUT  
23 *CR#1  
IN  
Clock request for SRC1, 0 = enable, 1 = disable  
24 VDDCORE_3.3  
PWR 3.3V power for the PLL core  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
2
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
SSOP Pin Description (continued)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
25 VDDIO_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
26 SRCC1_LPR  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for the SRC outputs  
27 SRCT1_LPR  
28 GNDSRC  
OUT  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
29 SRCC2_LPR  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
Clock request for SRC2, 0 = enable, 1 = disable  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values.  
30 SRCT2_LPR  
31 *CR#2  
OUT  
IN  
IN  
32 FSB_L  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
33 CPUC2_LPR  
34 CPUT2_LPR  
OUT  
OUT  
35 GNDCPU  
PWR Ground pin for the CPU outputs  
36 VDDIO_1.5  
37 VDDCORE_3.3  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 3.3V power for the PLL core  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
38 CPUC1_LPR  
39 CPUT1_LPR  
OUT  
OUT  
40 GNDCPU  
PWR Ground pin for the CPU outputs  
41 VDDIO_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
42 CPUC0_LPR  
OUT  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
Stops all CPU clocks, except those set to be free running clocks  
43 CPUT0_LPR  
44 CPU_STOP#  
OUT  
IN  
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs  
are valid and are ready to be sampled. This is an active low input. / Asynchronous  
active high input pin used to place the device into a power down state.  
45 CLKPWRGD#/PD_3.3  
IN  
46 X2  
47 X1  
48 VDDREF_3.3  
OUT Crystal output, Nominally 14.318MHz  
IN Crystal input, Nominally 14.318MHz.  
PWR Power pin for the XTAL and REF clocks, nominal 3.3V  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
3
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
MLF Pin Configuration  
48 47 46 45 44 43 42 41 40 39 38 37  
CPU_STOP#  
CLKPWRGD#/PD_3.3  
1
2
3
4
5
6
7
36 *CR#2  
SRCT2_LPR  
SRCC2_LPR  
GNDSRC  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
X2  
X1  
VDDREF_3.3  
REF  
SRCT1_LPR  
SRCC1_LPR  
VDDIO_1.5  
VDDCORE_3.3  
*CR#1  
ICS9UMS9633  
GNDREF  
VDDCORE_3.3 8  
FSC_L  
TEST_MODE  
TEST_SEL  
SCLK_3.3  
9
SRCT0_LPR  
SRCC0_LPR  
GNDSRC  
10  
11  
12  
13 14 15 16 17 18 19 20 21 22 23 24  
48-pin MLF, 6x6 mm, 0.4mm pitch  
* indicates inputs with internal pull up of ~10Kohm to 3.3V  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
4
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
MLF Pin Description  
PIN #  
1
PIN NAME  
CPU_STOP#  
TYPE  
IN  
DESCRIPTION  
Stops all CPU clocks, except those set to be free running clocks  
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs  
are valid and are ready to be sampled. This is an active low input. / Asynchronous  
active high input pin used to place the device into a power down state.  
2
CLKPWRGD#/PD_3.3  
IN  
3
4
5
6
7
8
X2  
X1  
OUT Crystal output, Nominally 14.318MHz  
IN Crystal input, Nominally 14.318MHz.  
PWR Power pin for the XTAL and REF clocks, nominal 3.3V  
OUT 14.318 MHz reference clock.  
PWR Ground pin for the REF outputs.  
PWR 3.3V power for the PLL core  
VDDREF_3.3  
REF  
GNDREF  
VDDCORE_3.3  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values.  
9
FSC_L  
IN  
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode  
while in test mode. Refer to Test Clarification Table.  
10 TEST_MODE  
IN  
TEST_SEL: latched input to select TEST MODE  
11 TEST_SEL  
IN  
IN  
1 = All outputs are tri-stated for test  
0 = All outputs behave normally.  
Clock pin of SMBus circuitry, 3.3V tolerant.  
12 SCLK_3.3  
13 SDATA_3.3  
14 VDDCORE_3.3  
15 VDDIO_1.5  
I/O Data pin for SMBus circuitry, 3.3V tolerant.  
PWR 3.3V power for the PLL core  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm  
resistor to GND needed. No Rs needed.  
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor  
to GND needed. No Rs needed.  
16 DOT96C_LPR  
17 DOT96T_LPR  
OUT  
OUT  
18 GNDDOT  
19 GNDLCD  
PWR Ground pin for DOT clock output  
PWR Ground pin for LCD clock output  
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm  
resistor to GND needed. No Rs needed.  
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to  
GND needed. No Rs needed.  
20 LCD100C_LPR  
21 LCD100T_LPR  
OUT  
OUT  
22 VDDIO_1.5  
23 VDDCORE_3.3  
24 *CR#0  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 3.3V power for the PLL core  
IN  
Clock request for SRC0, 0 = enable, 1 = disable  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
5
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
MLF Pin Description (continued)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
25 GNDSRC  
PWR Ground pin for the SRC outputs  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
26 SRCC0_LPR  
27 SRCT0_LPR  
OUT  
OUT  
IN  
28 *CR#1  
Clock request for SRC1, 0 = enable, 1 = disable  
29 VDDCORE_3.3  
30 VDDIO_1.5  
PWR 3.3V power for the PLL core  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
31 SRCC1_LPR  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
PWR Ground pin for the SRC outputs  
32 SRCT1_LPR  
33 GNDSRC  
OUT  
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
34 SRCC2_LPR  
OUT  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series  
resistor. No 50ohm resistor to GND needed.  
Clock request for SRC2, 0 = enable, 1 = disable  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values.  
35 SRCT2_LPR  
36 *CR#2  
OUT  
IN  
IN  
37 FSB_L  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
38 CPUC2_LPR  
39 CPUT2_LPR  
OUT  
OUT  
40 GNDCPU  
PWR Ground pin for the CPU outputs  
41 VDDIO_1.5  
42 VDDCORE_3.3  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 3.3V power for the PLL core  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
43 CPUC1_LPR  
44 CPUT1_LPR  
OUT  
OUT  
45 GNDCPU  
PWR Ground pin for the CPU outputs  
46 VDDIO_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm  
series resistor. No 50 ohm resistor to GND needed.  
47 CPUC0_LPR  
48 CPUT0_LPR  
OUT  
OUT  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
6
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Funtional Block Diagram  
REF  
X1  
X2  
OSC  
SRC(2:0)  
CPU(2:0)  
CPU, SRC  
SS-PLL  
LCD100_SSC  
LCD  
SS-PLL  
96M  
Non-SS  
PLL  
DOT96MHz  
FSLC  
FSLB  
CKPWRGD/PD#  
CPU_STOP#  
Control  
CR#(2:0)  
Logic  
TESTSEL  
TESTMODE  
SMBDAT  
SMBCLK  
Power Groups  
Pin Number  
Description  
VDD GND  
41, 46  
42  
30  
29  
22  
23  
15  
14  
5
Low power outputs  
VDDCORE_3.3V  
Low power outputs  
VDDCORE_3.3V  
Low power outputs  
VDDCORE_3.3V  
Low power outputs  
VDDCORE_3.3V  
Xtal, REF  
40, 45 CPUCLK  
25, 33 SRCCLK  
19  
LCDCLK  
18 DOT 96Mhz  
7
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
7
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
VDDxxx_3.3  
VDDxxx_1.5  
CONDITIONS  
Supply Voltage  
Supply Voltage  
MIN  
MAX  
3.9  
UNITS  
Notes  
1,2  
3.3V Supply Voltage  
1.5V Supply Voltage  
V
V
3.9  
1,2  
VDD_3.3+  
0.3V  
3.3_Input High Voltage  
VIH3.3  
3.3V Inputs  
V
1,2,3  
Minimum Input Voltage  
Storage Temperature  
VIL  
Ts  
Any Input  
-
GND - 0.5  
-65  
V
°C  
V
1
150  
1,2  
1,2  
1,2  
Human Body Model  
Man Machine Model  
2000  
Input ESD protection  
ESD prot  
200  
V
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied, nor guaranteed.  
3 Maximum input voltage is not to exceed maximum VDD  
Electrical Characteristics - Input/Supply/Common Output Parameters  
PARAMETER  
SYMBOL  
TambientITEMP  
VDDxxx_3.3  
VDDxxx_1.5  
VIHSE3.3  
CONDITIONS  
MIN  
MAX  
UNITS  
Notes  
Ambient Operating Temp  
3.3V Supply Voltage  
1.5V Supply Voltage  
3.3V Input High Voltage  
3.3V Input Low Voltage  
Input Leakage Current  
No Airflow  
-40  
85  
°C  
V
1
1
1
1
1
1
3.3V +/- 5%  
3.135  
1.425  
2
3.465  
3.465  
VDD + 0.3  
0.8  
1.5V - 5% to 3.3V + 5%  
Single-ended inputs  
Single-ended inputs  
VIN = VDD , VIN =GND  
V
V
VILSE3.3  
VSS - 0.3  
-5  
V
IIN  
5
uA  
Inputs with pull or pull down  
resistors. (CR# pins)  
Input Leakage Current  
IINRES  
-200  
2.4  
200  
uA  
1
VIN = VDD , VIN =GND  
Output High Voltage  
Output Low Voltage  
VOHSE  
VOLSE  
Single-ended outputs, IOH = -1mA  
Single-ended outputs, IOL = 1 mA  
V
V
1
1
0.4  
1.5  
Low Threshold Input-  
High Voltage  
Low Threshold Input-  
Low Voltage  
VIH_FS  
3.3 V +/-5%  
3.3 V +/-5%  
0.7  
V
V
1
1
VIL_FS  
IDD_DEFAULT  
IDD_LCDEN  
VSS - 0.3  
0.35  
3.3V supply, LCDPLL off  
65  
70  
mA  
mA  
1
1
3.3V supply, LCDPLL enabled  
Operating Supply Current  
1.5V supply, Differential IO current,  
all outputs enabled  
IDD_IO  
55  
2
mA  
mA  
mA  
1
1
1
IDD_PD3.3  
IDD_PDIO  
3.3V supply, Power Down Mode  
1.5V IO supply, Power Down Mode  
VDD = 3.3 V  
Power Down Current  
0.5  
Input Frequency  
Pin Inductance  
Fi  
15  
7
MHz  
nH  
pF  
2
1
1
1
1
Lpin  
CIN  
Logic Inputs  
Output pin capacitance  
X1 & X2 pins  
1.5  
30  
5
Input Capacitance  
COUT  
CINX  
6
pF  
5
pF  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
33  
kHz  
1
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
8
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
AC Electrical Characteristics - Input/Common Parameters  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
MAX  
1.8  
UNITS  
Notes  
1
From VDD Power-Up or de-  
assertion of PD# to 1st clock  
SRC output enable after  
CR# assertion  
Clk Stabilization  
TSTAB  
ms  
ns  
us  
ns  
Tdrive_SRC  
Tdrive_PD#  
Tdrive_CPU  
TDRSRC  
TDRPD  
15  
300  
10  
1
1
1
Differential output enable after  
PD# de-assertion  
CPU output enable after  
CPU_STOP# de-assertion  
TDRSRC  
Tfall_PD#  
TFALL  
TRISE  
5
5
ns  
ns  
1
1
Fall/rise time of PD# and  
CPU_STOP# inputs  
Trise_PD#  
AC Electrical Characteristics - Low Power Differential Outputs  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Rise/Fall Time Variation  
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
SYMBOL  
CONDITIONS  
MIN  
MAX  
6
UNITS  
V/ns  
V/ns  
ps  
NOTES  
tSLR  
Differential Measurement  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
0.5  
1,2  
tFLR  
0.5  
6
1,2  
tSLVAR  
125  
1150  
1
VHIGH  
mV  
mV  
mV  
mV  
mV  
%
1
VLOW  
Includes undershoot  
-300  
300  
300  
1
VSWING  
VXABS  
VXABSVAR  
DCYC  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
1
550  
140  
55  
1,3,4  
1,3,5  
45  
1
1
1
1
1
1
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
CPU[2:0] Skew  
CPUJC2C  
SRCJC2C  
DOTJC2C  
CPUSKEW10  
SRCSKEW  
85  
ps  
125  
250  
100  
250  
ps  
ps  
ps  
SRC[2:0] Skew  
ps  
Electrical Characteristics - REF-14.318MHz  
PARAMETER  
SYMBOL  
CONDITIONS  
see Tperiod min-max values  
14.318MHz output nominal  
14.318MHz output nominal  
IOH = -1 mA  
MIN  
-300  
MAX  
300  
UNITS  
ppm  
ns  
Notes  
Long Accuracy  
ppm  
1,2  
2
Clock period  
Tperiod  
Tabs  
69.8203  
69.8203  
2.4  
69.8622  
70.86224  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
ns  
2
VOH  
V
1
VOL  
IOL = 1 mA  
0.4  
-33  
V
1
VOH @MIN = 1.0 V,  
VOH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
Output High Current  
Output Low Current  
IOH  
-33  
30  
mA  
mA  
1
1
IOL  
38  
VOL @MAX = 0.4 V  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
4
4
V/ns  
V/ns  
%
1
1
1
1
dt1  
45  
55  
Jitter  
tjcyc-cyc  
VT = 1.5 V  
1000  
ps  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
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ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Electrical Characteristics - SMBus Interface  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
2.7  
MAX  
3.3  
UNITS  
Notes  
SMBus Voltage  
VDD  
V
V
1
1
Low-level Output Voltage  
Current sinking at  
VOLSMB  
@ IPULLUP  
0.4  
IPULLUP  
SMB Data Pin  
4
mA  
1
VOLSMB = 0.4 V  
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
TRI2C  
TFI2C  
1000  
300  
ns  
ns  
1
1
1
Clock/Data Fall Time  
Maximum SMBus Operating  
Frequency  
FSMBUS  
Block Mode  
100  
kHz  
Notes on Electrical Characteristics:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through Vswing centered around differential zero  
3 Vxabs is defined as the voltage where CLK = CLK#  
4 Only applies to the differential rising edge (CLK rising and CLK# falling)  
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and  
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.  
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz  
7 Operation under these conditions is neither implied, nor guaranteed.  
Clock Periods Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
Lg-  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Lg+  
Symbol  
-SSC  
-ppm error  
0ppm  
+ ppm error  
+SSC  
Absolute Short-term Long-Term  
Period Average Average  
Long-Term Short-term  
Period  
Period  
Average  
Average  
Definition  
Minimum Minimum Minimum  
Absolute Absolute Absolute  
Nominal  
Maximum  
Maximum Maximum  
Period  
9.87400  
9.91400  
Period  
9.99900  
9.99900  
Period  
9.99900  
9.99900  
Units  
ns  
Notes  
1,2  
10.00000  
10.00000  
10.00100  
10.00100  
10.05130  
10.05130  
10.17630  
10.13630  
SRC 100  
ns  
1,2  
CPU 100  
7.41425  
5.91440  
7.49925  
5.99940  
7.49925  
5.99940  
7.50000  
6.00000  
7.50075  
6.00060  
7.53845  
6.03076  
7.62345  
6.11576  
ns  
ns  
1,2  
1,2  
CPU 133  
CPU 166  
Clock Periods Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
Lg-  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Lg+  
Symbol  
-SSC  
-ppm error  
0ppm  
+ ppm error  
+SSC  
Absolute Short-term Long-Term  
Period Average Average  
Long-Term Short-term  
Period  
Period  
Average  
Average  
Definition  
Minimum Minimum Minimum  
Absolute Absolute Absolute  
Nominal  
Maximum  
Maximum Maximum  
Period  
9.87400  
9.91400  
7.41425  
5.91440  
10.16560  
Period  
Period  
9.99900  
9.99900  
7.49925  
5.99940  
10.41560  
Units  
ns  
Notes  
1,2  
10.00000  
10.00000  
7.50000  
6.00000  
10.41670  
10.00100  
10.00100  
7.50075  
6.00060  
10.41770  
10.17630  
10.13630  
7.62345  
6.11576  
10.66770  
SRC 100  
ns  
1,2  
CPU 100  
CPU 133  
CPU 166  
DOT 96  
ns  
1,2  
ns  
1,2  
ns  
1,2  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
10  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Table 1: CPU Frequency Select Table  
CPU  
MHz  
SRC  
MHz  
DOT  
MHz  
LCD  
MHz  
REF  
MHz  
FSLC1 FSLB1  
0
0
1
1
0
1
0
1
133.33  
166.67  
100.00  
66.67  
100.00  
96.00  
100.00 14.318  
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
Table 2: LCD Spread Select Table (Pin 20/21)  
Spread  
Table 3: CPU N-step Programming  
CPU  
Default N  
(hex)  
64  
B1b5  
B1b4  
B1b3  
Comment  
Fcpu  
P
%
(MHz)  
133.33  
166.67  
100.00  
200.00  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5%  
LCD100  
LCD100  
LCD100  
LCD100  
3
3
4
2
= 4MHz x N/P  
= 4MHz x N/P  
= 4MHz x N/P  
= 4MHz x N/P  
-1%  
7D  
-2%  
64  
-2.5%  
64  
+/- 0.25% LCD100  
+/-0.5% LCD100  
+/-1%  
LCD100  
+/-1.25% LCD100  
CPU Power Management Table  
SMBus Register  
OE  
PD  
CPU_STOP#  
CPU  
CPU#  
0
1
0
0
Enable  
Enable  
Enable  
Disable  
Running Running  
1
X
0
Low/20K  
High  
Low  
Low  
Low  
X
Low/20K  
SRC, LCD, DOT Power Management Table  
SMBus Register  
PD  
CR_x#  
SRC  
SRC# DOT/LCD DOT#/LCD#  
OE  
0
1
0
0
Enable  
X
Enable  
Disable  
Running Running Running  
Running  
Low  
Running  
Low  
0
X
1
Low/20K  
Low/20K  
Low/20K  
Low  
Low  
Low  
Low/20K  
Running  
Low/20K  
X
REF Power Management Table  
SMBus Register  
PD  
REF  
OE  
0
1
0
Enable  
X
Disable  
Running  
Low  
Low  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
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ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
General SMBus serial interface information for the ICS9UMS9633BI  
How to Write:  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address D2(h)  
• ICS clock will acknowledge  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address D2(h)  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address D3(h)  
• ICS clock will acknowledge  
• ICS clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock sends Byte 0 through byte X (if X(h)  
was written to byte 8).  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
Controller (Host)  
ICS (Slave/Receiver)  
ICS (Slave/Receiver)  
starT bit  
T
starT bit  
T
Slave Address D2(h)  
Slave Address D2(h)  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
RT  
Repeat starT  
Slave Address D3(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
12  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
0
PLL & Divider Enable Register  
Name  
Pin #  
Description  
Type  
0
1
Default  
This bit controls whether the PLL driving the CPU  
and SRC clocks is enabled or not.  
This bit controls whether the PLL driving the DOT  
and clock is enabled or not.  
This bit controls whether the PLL driving the LCD  
clock is enabled or not.  
7
6
-
-
PLL1 Enable  
PLL2 Enable  
PLL3 Enable  
RW  
0 = Disabled  
1 = Enabled  
1
RW  
RW  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1
5
4
-
-
1
0
Reserved  
This bit controls whether the CPU output divider is  
enabled or not.  
3
2
1
0
-
-
-
-
CPU Divider Enable  
RW  
RW  
RW  
RW  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
1
1
1
This bit should be automatically set to ‘0’ if  
bit 7 is set to ‘0’.  
NOTE:  
This bit controls whether the SRC output divider is  
enabled or not.  
NOTE: This bit should be automatically set to ‘0’ if  
bit 7 is set to ‘0’.  
This bit controls whether the LCD output divider is  
enabled or not.  
SRC Output Divider  
Enable  
LCD Output Divider  
Enable  
This bit should be automatically set to ‘0’ if  
bit 5 is set to ‘0’.  
NOTE:  
This bit controls whether the DOT output divider is  
enabled or not.  
DOT Output Divider  
Enable  
This bit should be automatically set to ‘0’ if  
bit 6 is set to ‘0’.  
NOTE:  
Byte  
Bit(s)  
1
PLL SS Enable/Control Register  
Name  
Pin #  
Description  
Type  
0
1
Default  
This bit controls whether PLL1 has spread enabled  
or not. Spread spectrum for PLL1 is set at -0.5%  
down-spread. Note that PLL1 drives the CPU and  
SRC clocks.  
7
6
PLL1 SS Enable  
RW  
0 = Disabled  
1 = Enabled  
1
This bit controls whether PLL3 has spread enabled  
or not. Note that PLL3 drives the SSC clock, and  
that the spread spectrum amount is set in bits 3-5.  
PLL3 SS Enable  
PLL3 FS Select  
RW  
RW  
0 = Disabled  
1 = Enabled  
1
5
4
3
2
1
0
These 3 bits select the frequency of PLL3 and the  
0
0
0
0
0
0
See Table 2: LCD Spread  
Select Table  
SSC clock when Byte 1 Bit 6 (PLL3 Spread  
Spectrum Enable) is set.  
Reserved  
Reserved  
Reserved  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
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ICS9UMS9633BI  
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ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
2
Output Enable Register  
Name  
Pin #  
Description  
Type  
0
1
Default  
This bit controls whether the CPU[0] output buffer  
is enabled or not.  
This bit controls whether the CPU[1] output buffer  
is enabled or not.  
This bit controls whether the CPU[2] output buffer  
is enabled or not.  
This bit controls whether the SRC[0] output buffer  
is enabled or not.  
This bit controls whether the SRC[1] output buffer  
is enabled or not.  
This bit controls whether the SRC[2] output buffer  
is enabled or not.  
This bit controls whether the DOT output buffer is  
enabled or not.  
This bit controls whether the LCD output buffer is  
enabled or not.  
7
6
5
4
3
2
1
0
CPU0 Enable  
CPU1 Enable  
CPU2 Enable  
SRC0 Enable  
SRC1 Enable  
SRC2 Enable  
DOT Enable  
RW  
0 = Disabled  
1 = Enabled  
1
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
1
1
1
1
1
1
LCD100 Enable  
Byte  
Bit(s)  
7
3
Output Control Register  
Name  
Pin #  
Description  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
6
This bit controls whether the REF output buffer is  
enabled or not.  
5
4
3
REF Enable  
REF Slew  
RW  
RW  
0 = Disabled  
1 = Enabled  
1
00 = Slow Edge Rate  
01 = Medium Edge Rate  
10 = Fast Edge Rate  
11 = Reserved  
These bits control the edge rate of the REF clock.  
10  
This bit controls whether the CPU[0] output buffer  
is free-running or stoppable. If it is set to stoppable  
the CPU[0] output buffer will be disabled with the  
assertion of CPU_STP#.  
This bit controls whether the CPU[1] output buffer  
is free-running or stoppable. If it is set to stoppable  
the CPU[1] output buffer will be disabled with the  
assertion of CPU_STP#.  
This bit controls whether the CPU[2] output buffer  
is free-running or stoppable. If it is set to stoppable  
the CPU[2] output buffer will be disabled with the  
assertion of CPU_STP#.  
2
1
0
CPU0 Stop Enable  
CPU1 Stop Enable  
CPU2 Stop Enable  
RW  
RW  
RW  
Free Running  
Free Running  
Free Running  
Stoppable  
Stoppable  
Stoppable  
0
0
0
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
14  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
4
CPU PLL N Register  
Name  
Pin #  
Control Function  
Reserved  
Type  
0
1
Default  
1
1
1
1
1
1
1
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
CPU N Div8  
N Divider Prog bit 8  
RW  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
5
CPU PLL/N Register  
Name  
Pin #  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
CPU N Div7  
CPU N Div6  
CPU N Div5  
CPU N Div4  
CPU N Div3  
CPU N Div2  
CPU N Div1  
CPU N Div0  
X
X
X
X
X
X
X
X
Default depends on latched  
input frequency.  
Default for CPU = 166 is 7Dh.  
Default for all other frequencies  
is 64h.  
See Table 3: CPU N-step Programming  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
6
Reserved  
Name  
Pin #  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
1
1
1
1
0
0
1
1
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
7
Reserved  
Name  
Pin #  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
15  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
8
Reserved  
Name  
Pin #  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
9
LCD100 PLL N Register  
Name  
LCD100 N Div7  
LCD100 N Div6  
LCD100 N Div5  
Pin #  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
X
X
X
X
X
X
X
X
N Divider Programming Byte9 bit(7:0) and Byte8  
bit7  
See N-step programming  
formula  
LCD100 N Div4  
LCD100 N Div3  
LCD100 N Div2  
LCD100 N Div1  
LCD100 N Div0  
Byte  
Bit(s)  
10  
Pin #  
37  
9
24  
Status Readback Register  
Name  
Description  
Frequency Select B  
Frequency Select C  
Real time CR0# State Indicator  
Real time CR1# State Indicator  
Real time CR2# State Indicator  
Reserved  
Type  
R
R
R
R
0
1
Default  
Latch  
Latch  
7
6
5
4
3
2
1
0
FSB  
FSC  
CR0# Readbk  
CR1# Readbk  
CR2# Readbk  
See Table 1: CPU Frequency  
Select Table  
CR0# is Low CR0# is High  
CR1# is Low CR1# is High  
CR2# is Low CR2# is High  
X
X
X
0
0
0
28  
36  
R
Reserved  
Reserved  
Byte  
Bit(s)  
11  
Pin #  
Revision ID/Vendor ID Register  
Name  
Description  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
7
6
5
4
3
2
1
0
Rev Code Bit 3  
Rev Code Bit 2  
Rev Code Bit 1  
Rev Code Bit 0  
Vendor ID bit 3  
Vendor ID bit 2  
Vendor ID bit 1  
Vendor ID bit 0  
X
X
X
X
0
0
0
1
Revision ID  
(0 for A rev)  
Vendor specific  
Vendor ID  
Byte  
Bit(s)  
12  
Pin #  
Device ID Register  
Name  
Description  
Device ID MSB  
Device ID 2  
Device ID 1  
Device ID LSB  
Type  
R
R
R
R
0
1
Default  
7
6
5
4
3
2
1
0
DEV_ID3  
DEV_ID2  
DEV_ID1  
DEV_ID0  
0
0
1
1
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
16  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
13  
Pin #  
Reserved Register  
Name  
Control Function  
Reserved  
Type  
Type  
Type  
0
0
0
1
1
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
14  
Pin #  
Reserved Register  
Name  
Control Function  
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
15 Byte Count Register  
Pin #  
Name  
Control Function  
Default  
Reserved  
Reserved  
Byte Count 5  
Byte Count 4  
Byte Count 3  
Byte Count 2  
Byte Count 1  
Byte Count LSB  
0
0
0
0
1
1
1
1
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
RW  
Specifies Number of bytes to  
be read back during an SMBus  
read.  
Default is 0xF.  
Bytes 16:40 are reserved  
Byte  
Bit(s)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
41  
Pin #  
N Program Enable Register  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Reserved  
CPU N Enable  
LCD N Enable  
Enables CPU N programming  
Enables LCD N programming  
RW  
RW  
Disabled  
Disabled  
Enabled  
Enabled  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
17  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Test Clarification Table  
Comments  
HW  
TEST_SEL TEST_MODE  
HW PIN  
HW PIN  
OUTPUT  
<0.35V  
X
NORMAL  
Power-up w/ TEST_SEL = 1 to enter test mode  
>0.7V  
>0.7V  
<0.35V  
>0.7V  
HI-Z  
Cycle power to disable test mode  
TEST_MODE -->low Vth input  
TEST_MODE is a real time input  
REF/N  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
18  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
MLFTop Mark Information (9UMS9633BKILF)  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
3
4
36  
35  
34  
33  
ICS  
5
32  
31  
30  
29  
28  
27  
26  
25  
MS9633BIL  
YYWW  
6
7
8
9
CofO  
10  
11  
12  
######  
13 14 15 16 17 18 19 20 21 22 23 24  
Line 1. Company name  
Line 2. Part Number  
Line 3.YYWW = Date Code  
Line 3. Country of Origin  
Line 4. ####### = Lot Number  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
19  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
300 mil SSOP  
In Millimeters  
In Inches  
SYMBOL  
COMMON DIMENSIONS  
COMMON DIMENSIONS  
MIN  
2.41  
0.20  
0.20  
0.13  
MAX  
2.80  
0.40  
0.34  
0.25  
MIN  
.095  
.008  
.008  
.005  
MAX  
.110  
.016  
.0135  
.010  
A
A1  
b
c
D
E
E1  
e
SEE VARIATIONS  
SEE VARIATIONS  
10.03  
7.40  
10.68  
7.60  
.395  
.291  
.420  
.299  
0.635 BASIC  
0.025 BASIC  
h
L
0.38  
0.50  
0.64  
1.02  
.015  
.020  
.025  
.040  
N
a
SEE VARIATIONS  
SEE VARIATIONS  
0°  
8°  
0°  
8°  
VARIATIONS  
D mm.  
D (inch)  
N
MIN  
15.75  
MAX  
16.00  
MIN  
.620  
MAX  
.630  
48  
Reference Doc.: JEDEC Publication 95, MO-118  
10-0034  
Ordering Information  
9UMS9633BFILFT  
Example:  
XXXX B F I LF T  
Designation for tape and reel packaging  
Lead Free, RoHS Compliant  
Industrial Temperature Range (-40C to +85C)  
Package Type  
F = SSOP  
Revision Designator  
Device Type  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
20  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
(Ref.)  
ND & N  
Even  
Seating Plane  
(ND -1)x e  
(Ref.)  
A1  
Index Area  
L
A3  
N
N
(Typ.)  
e
2
If ND & N  
are Even  
Anvil  
Singulation  
1
2
(N -1)x  
(Ref.)  
e
E2  
OR  
E2  
2
Sawn  
Singulation  
Top View  
D
b
e
Thermal  
Base  
(Re f.)  
D2  
2
A
&
ND  
Odd  
N
D2  
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
C
0. 08  
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH  
QUAD FLAT / NO LEAD PLASTIC PACKAGE  
DIMENSIONS  
DIMENSIONS  
48L  
SYMBOL  
MIN.  
0.8  
0
MAX.  
1.0  
0.05  
SYMBOL  
N
TOLERANCE  
48  
A
A1  
A3  
b
ND  
12  
0.20 Reference  
0.18  
0.40 BASIC  
NE  
12  
0.3  
D x E BASIC  
D2 MIN. / MAX.  
E2 MIN. / MAX.  
L MIN. / MAX.  
6.00 x 6.00  
3.95 / 4.25  
3.95 / 4.25  
0.30 / 0.50  
e
Ordering Information  
9UMS9633BKILFT  
Example:  
XXXX B K I LF T  
Designation for tape and reel packaging  
Lead Free, RoHS Compliant  
Industrial Temperature Range (-40C to +85C)  
Package Type  
K = MLF  
Revision Designator  
Device Type  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
21  
ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Revision History  
Rev.  
Issue Date Description  
Page #  
0.1  
02/15/08 Initial Release  
-
1. Byte 4 default value changed to FF hex  
0.2  
02/27/08 2. Byte 6 default value changed to F3 hex.  
1. Corrected Reference in Byte 5 to CPU NDIV8. Should refer to  
Byte 4, bit 0.  
2. Corrected Reference in LCD100 NDIV to only refer to Byte 9  
3. Corrected headings in clock period table.  
4. Added N-step programming info.  
0.3  
0.4  
0.5  
05/21/08 5. Corrected Byte 4 default value  
11/12/08 Removed reference to 1.5V inputs  
01/20/09 Updated SMBus byte 4/5; added CPU N-step Programming table  
Various  
11, 15  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
United States  
800 345 7015  
Integrated Device Technology  
Singapore (1997) Pte. Ltd.  
Reg. No. 199707558G  
435 Orchard Road  
#20-03 Wisma Atria  
Singapore 238877  
IDT Europe, Limited  
Prime House  
Barnett Wood Lane  
Leatherhead, Surrey  
United Kingdom KT22 7DE  
+44 1372 363 339  
+408 284 8200 (outside U.S.)  
+65 6 887 5505  
TM  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks  
or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
22  
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