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9UMS9001AKLFT

型号：

9UMS9001AKLFT

描述：

电脑主时钟 - CK540[ PC MAIN CLOCK - CK540 ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

104 K

下载PDF手册
PC MAIN CLOCK - CK540  
9UMS9001  
Features/Benefits:  
Recommended Application:  
•
•
•
Supports Dothan ULV CPUs with 100 and  
Calistoga Based Ultra-Mobile PC (UMPC)  
133 MHz CPU outputs  
Output Features:  
Dedicated TEST/SEL and TEST/MODE pins  
saves isolation resistors on pins  
•
•
•
•
2 - CPU Low Power differential push-pull pairs  
1 - ITP low power differential push-pull pair  
4 - SRC low power differential push-pull pairs  
PCI_SRC and CPU STOP inputs for power  
manangment  
•
•
Fully integrated Vreg  
1 - LCD100 SSCD low power differential  
push-pull pair  
Integrated series resistors on differential  
outputs  
•
1 - DOT96 low power differential push-pull  
pair  
•
Supports split rail operation for maximum  
power savings  
•
•
•
3 - PCI, 33MHz  
•
•
Also runs from single 3.3V rail  
1 - USB, 48MHz  
1.05V-3.3V support for differential VDDIO  
1 - REF, 14.31818MHz  
Pin Configuration  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
X2 1  
X1 2  
42 CLKREQ2#  
41 CLKREQ3#  
VDDREFIO_3.3 3  
REF0 4  
40 VDDCORE_3.3  
39 SRC3T_LPRS  
5
6
38  
SRC3C_LPRS  
SDATA  
SCLK  
37 SRC2T_LPRS  
36 SRC2C_LPRS  
35 VDDIO_SRC  
34 GNDSRC  
33 SRC1T_LPRS  
32 SRC1C_LPRS  
31 SRC0T_LPRS  
30 SRC0C_LPRS  
29 CKLREQ0#  
TEST_SEL 7  
TEST_MODE 8  
PCI_STOP# 9  
VDDIO_PCI3.3 10  
PCI0 11  
ICS9UMS9001  
PCI1 12  
PCI_F2 13  
GNDPCI 14  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
56-pin MLF  
1
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Pin Description  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
1
X2  
X1  
OUT Crystal output, nominally 14.318MHz.  
2
3
4
5
6
IN Crystal input, Nominally 14.318MHz.  
VDDREFIO_3.3  
REF0  
PWR Power pin for the REF output and crystal oscillator. 3.3V nominal.  
OUT 3.3V 14.318MHz reference clock  
SDATA  
I/O Data pin for SMBus circuitry, 5V tolerant.  
IN Clock pin of SMBus circuitry, 5V tolerant.  
SCLK  
3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for  
details.  
7
TEST_SEL  
IN  
8
TEST_MODE  
PCI_STOP#  
VDDIO_PCI3.3  
PCI0  
IN When Test mode is selected, this chooses either hi-Z or REF/N for the outputs.  
IN 3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running.  
PWR 3.3V power supply for the PCI outputs  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
OUT 3.3V PCI clock output.  
PCI1  
OUT 3.3V PCI clock output.  
PCI_F2  
OUT Free running 3.3V PCI clock output  
GNDPCI  
PWR Ground for PCI output clocks.  
GND48  
PWR Ground for the USB clock.  
USB_48MHz  
VDD48IO_3.3  
VDD48PLL_3.3  
VDDIO_96Mhz  
OUT Fixed 3.3V 48MHz USB clock output  
PWR 3.3V Power supply for the 48MHz output  
PWR 3.3V Power supply for the 48/96MHz PLL  
PWR Power supply for DOT96 output. VDD_IO = 1.05 to 3.3V +/-5%.  
Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external  
series resistor required).  
True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series  
resistor required).  
20  
21  
DOT96C_LPRS  
DOT96T_LPRS  
OUT  
OUT  
22  
23  
GND  
GND  
PWR Ground for 96MHz output  
PWR Ground for LCD 100 MHz output.  
Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated  
(No external series resistor required).  
24  
LCD100C_LPRS  
OUT  
True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No  
external series resistor required).  
25  
LCD100T_LPRS  
OUT  
26  
27  
VDDIO_LCD  
PWR Power supply for LCD100 output. VDD_IO = 1.05 to 3.3V +/-5%.  
PWR 3.3V Power supply for the LCD100 Spreading PLL  
VDDLCDPLL_3.3  
Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for  
details  
28  
CLKREQ1#  
IN  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
2
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Pin Description (continued)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
Clock request input for SRC output pair 0. See the SRC, LCD, DOT Power Management Table for  
details  
29  
CKLREQ0#  
IN  
Complement side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external  
series resistor required).  
True side of low-power CK505-type SRC0 differential clock. Rs is integrated (No external series  
resistor required).  
Complement side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external  
series resistor required).  
True side of low-power CK505-type SRC1 differential clock. Rs is integrated (No external series  
resistor required).  
30  
31  
32  
33  
SRC0C_LPRS  
SRC0T_LPRS  
SRC1C_LPRS  
SRC1T_LPRS  
OUT  
OUT  
OUT  
OUT  
34  
35  
GNDSRC  
PWR Ground for SRC clocks  
VDDIO_SRC  
PWR Power supply for SRC outputs. VDD_IO = 1.05 to 3.3V +/-5%.  
Complement side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external  
series resistor required).  
True side of low-power CK505-type SRC2 differential clock. Rs is integrated (No external series  
resistor required).  
Complement side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external  
series resistor required).  
36  
37  
38  
SRC2C_LPRS  
SRC2T_LPRS  
SRC3C_LPRS  
OUT  
OUT  
OUT  
True side of low-power CK505-type SRC3 differential clock. Rs is integrated (No external series  
resistor required).  
PWR 3.3V Power supply for 3.3V core  
39  
40  
41  
SRC3T_LPRS  
VDDCORE_3.3  
CLKREQ3#  
OUT  
Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for  
details  
IN  
Clock request input for SRC output pair 2. See the SRC, LCD, DOT Power Management Table for  
details  
42  
CLKREQ2#  
IN  
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and  
Vil_fs specifications.  
IN Stops all CPU clocks except those set to be free running.  
43  
44  
45  
FSLB  
IN  
CPU_STOP#  
CPUITPC_LPRS  
Complement side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external  
series resistor required). Note that this pin is NOT muxed with an SRC output.  
OUT  
True side of low-power CK505-type CPUITP differential clock. Rs is integrated (No external series  
resistor required).  
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external  
series resistor required). Note that this pin is NOT muxed with an SRC output.  
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series  
resistor required).  
46  
47  
48  
CPUITPT_LPRS  
CPU1C_LPRS  
CPU1T_LPRS  
OUT  
OUT  
OUT  
49  
50  
VDDIO_CPU  
GNDCPU  
PWR Power supply for CPU outputs. VDD_IO = 1.05 to 3.3V +/-5%.  
PWR Ground Pin for CPU Outputs  
Complement side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external  
series resistor required). Note that this pin is NOT muxed with an SRC output.  
51  
CPU0C_LPRS  
OUT  
True side of low-power CK505-type CPU1 differential clock. Rs is integrated (No external series  
resistor required).  
PWR 3.3V Power Supply for CPU PLL.  
52  
53  
CPU0T_LPRS  
OUT  
VDDCPUPLL_3.3  
Notifies 9UMS9001 to sample latched inputs or enter power down mode.  
1 = Power down mode  
Falling Edge = Sample latched inputs  
54  
CK_PWRGD#/PD  
IN  
0 = Normal operation  
Low threshold Frequency Select input. See Table 1: CPU Frequency Select Table and the Vih_fs and  
Vil_fs specifications.  
55  
56  
FSLC  
IN  
GNDREF  
PWR Ground pin for crystal oscillator circuit and REF output  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
3
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Functional Block Diagram  
REF  
PCI  
X1  
OSC  
X2  
SRC(3:0)  
CPU(2:0)  
CPU/SRC/  
PC  
SS-PLL  
LCD  
LCD SS  
PLL  
DOT96MHZ  
48MHZ  
Fixed  
EXACT  
48MHz  
FSLC  
FSLB  
CKPWRGD#/PD  
PCI_STOP#  
CPU_STOP#  
Control  
Logic  
CLKREQ(3:0)#  
ITP_EN  
TESTSEL  
TESTMODE  
Power Groups  
Pin Number  
VDDIO 1.05~3.3V  
Description  
Low power outputs  
Analog  
Master Clock, Analog  
VDD3.3V  
GND  
49  
50  
CPUCLK  
53  
53  
35  
26  
19  
Low power outputs  
34  
23  
SRCCLK  
40  
27  
Analog  
Low power outputs  
PLL  
LCDCLK  
22  
15  
56  
14  
DOT 96Mhz  
Low power outputs  
17, 18  
3
10  
USB 48  
Xtal, REF  
PCICLK  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
4
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Table 1: CPU Frequency Select Table  
FSLC1 FSLB1  
CPU  
MHz  
SRC  
MHz  
PCI  
MHz  
REF  
MHz  
USB  
MHz  
DOT  
MHz  
B0b7  
B0b6  
0
0
1
1
0
1
0
1
133.33  
Reserved  
100.00  
100.00  
100.00  
33.33  
33.33  
14.318  
14.318  
48.00  
48.00  
96.00  
96.00  
200.00  
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
Table 2: LCD Quick Configuration  
Spread  
Pin 24/25  
MHz  
B1b3  
B1b2  
B1b1  
B1b0  
Comment  
%
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00 0.25% Down Spread  
100.00 0.5% Down Spread  
100.00 1% Down Spread  
100.00 1.25% Down Spread  
100.00 1.5% Down Spread  
100.00 2% Down Spread  
100.00 2.5% Down Spread  
100.00 3.0% Down Spread  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
100.00 0.25% Center Spread LCDCLK  
100.00 0.5% Center Spread  
100.00 1% Center Spread  
LCDCLK  
LCDCLK  
100.00 1.25% Center Spread LCDCLK  
100.00 1.5% Center Spread  
100.00 2% Center Spread  
100.00 2.5% Center Spread  
100.00 3.0% Center Spread  
LCDCLK  
LCDCLK  
LCDCLK  
LCDCLK  
Table 3: IO_Vout select table  
B5b2  
B5b1  
B5b0 IO_Vout  
0.3V  
0.4V  
0.5V  
0.6V  
0.7V  
0.8V  
0.9V  
1.0V  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
5
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
VDDxxx_3.3  
VDDxxx_1.8  
CONDITIONS  
Supply Voltage  
Supply Voltage  
MIN  
MAX  
UNITS Notes  
Maximum Supply Voltage  
Maximum Supply Voltage  
Maximum Supply Voltage  
4.6  
2.3  
3.8  
V
V
V
1,7  
1,7  
1,7  
VDDxxx_IO Low-Voltage Differential I/O Supply  
Maximum Input Voltage  
Minimum Input Voltage  
Storage Temperature  
Input ESD protection  
VIH  
VIL  
3.3V LVCMOS Inputs  
Any Input  
4.6  
V
V
°C  
1,7,8  
1,7  
GND - 0.5  
-65  
Ts  
-
150  
1,7  
ESD prot  
Human Body Model  
2000  
V
1,7  
Electrical Characteristics - Input/Supply/Common Output Parameters  
PARAMETER  
Ambient Operating Temp  
Supply Voltage  
SYMBOL  
CONDITIONS  
MIN  
MAX  
UNITS Notes  
Tambient  
-
0
70  
°C  
V
1
1
1
VDDxxx_3.3  
VDDxxx_1.8  
Supply Voltage  
Supply Voltage  
3.135  
1.71  
3.465  
1.89  
Supply Voltage  
V
Supply Voltage  
VDDxxx_IO Low-Voltage Differential I/O Supply  
1.05  
3.465  
V
1
Input High Voltage  
Input Low Voltage  
VIHSE  
VILSE  
IIN  
Single-ended inputs  
Single-ended inputs  
VIN = VDD , VIN =GND  
2
VSS - 0.3  
-5  
VDD + 0.3  
V
V
1
1
1
0.8  
5
Input Leakage Current  
uA  
Inputs with pull or pull down  
resistors  
Input Leakage Current  
IINRES  
-200  
2.4  
200  
uA  
1
VIN = VDD , VIN =GND  
Output High Voltage  
Output Low Voltage  
Output High Voltage  
Output Low Voltage  
VOHSE  
VOLSE  
VOHDIF  
VOLDIF  
Single-ended outputs, IOH = -1mA  
Single-ended outputs, IOL = 1 mA  
Differential Outputs  
V
V
V
V
1
1
1
1
0.4  
0.9  
0.4  
0.7  
Differential Outputs  
Low Threshold Input-  
High Voltage (Test Mode)  
Low Threshold Input-  
High Voltage  
Low Threshold Input-  
Low Voltage  
VIH_FS_TEST  
VIH_FS  
3.3 V +/-5%  
3.3 V +/-5%  
3.3 V +/-5%  
2
VDD + 0.3  
1.5  
V
V
V
1
1
1
0.7  
VIL_FS  
VSS - 0.3  
0.35  
Operating Supply Current  
IDD_DEFAULT  
IDD_LCDEN  
3.3V supply, LCDPLL off  
80  
mA  
mA  
1
1
3.3V supply, LCDPLL enabled  
100  
0.8V supply, Differential IO current,  
all outputs enabled  
IDD_IO  
25  
1
mA  
mA  
mA  
1
1
1
IDD_PD3.3  
IDD_PDIO  
3.3V supply, Power Down Mode  
0.8V IO supply, Power Down Mode  
VDD = 3.3 V  
Power Down Current  
0.1  
Input Frequency  
Pin Inductance  
Fi  
15  
7
MHz  
nH  
pF  
2
1
1
1
1
Lpin  
CIN  
Logic Inputs  
Output pin capacitance  
X1 & X2 pins  
1.5  
30  
5
Input Capacitance  
COUT  
CINX  
6
pF  
7
pF  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
33  
kHz  
1
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
6
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
AC Electrical Characteristics - Input/Common Parameters  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
MAX  
UNITS Notes  
From VDD Power-Up or de-  
assertion of PD# to 1st clock  
SRC output enable after  
PCI_STOP# de-assertion  
Differential output enable after  
PD# de-assertion  
Clk Stabilization  
TSTAB  
1.8  
15  
ms  
ns  
us  
ns  
1
1
1
1
Tdrive_SRC  
Tdrive_PD#  
Tdrive_CPU  
TDRSRC  
TDRPD  
300  
10  
CPU output enable after  
CPU_STOP# de-assertion  
TDRSRC  
Tfall_PD#  
TFALL  
TRISE  
5
5
ns  
ns  
1
1
Fall/rise time of PD#, PCI_STOP#  
and CPU_STOP# inputs  
Trise_PD#  
AC Electrical Characteristics - Low Power Differential Outputs  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Rise/Fall Time Variation  
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
SYMBOL  
CONDITIONS  
MIN  
MAX  
4
UNITS NOTES  
tSLR  
Differential Measurement  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
1
V/ns  
V/ns  
ps  
1,2  
tFLR  
1
4
1,2  
tSLVAR  
125  
1150  
1
VHIGH  
mV  
mV  
mV  
mV  
mV  
%
1
VLOW  
Includes undershoot  
-300  
300  
300  
1
VSWING  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
1
VXABS  
550  
140  
55  
1,3,4  
VXABSVAR  
DCYC  
1,3,5  
45  
1
1
1
1
1
1
1
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
CPU[1:0] Skew  
CPUJC2C  
SRCJC2C  
DOTJC2C  
CPUSKEW10  
CPUSKEW20  
SRCSKEW  
85  
ps  
125  
250  
100  
150  
250  
ps  
ps  
ps  
CPU[2_ITP:0] Skew  
ps  
SRC[3:0] Skew  
ps  
Electrical Characteristics - PCICLK/PCICLK_F  
NOTES  
PARAMETER  
SYMBOL  
CONDITIONS  
see Tperiod min-max values  
33.33MHz output nominal  
33.33MHz output spread  
33.33MHz output nominal/spread  
IOH = -1 mA  
MIN  
MAX  
300  
UNITS  
ppm  
ns  
1,6  
6
Long Accuracy  
ppm  
-300  
30.00900  
30.15980  
30.65980  
Clock period  
Tperiod  
29.99100  
6
ns  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
Tabs  
VOH  
VOL  
29.49100  
2.4  
6
ns  
V
1
IOL = 1 mA  
0.4  
-33  
V
1
V
OH @MIN = 1.0 V  
VOH@MAX = 3.135 V  
OL @ MIN = 1.95 V  
-33  
30  
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
Output High Current  
Output Low Current  
IOH  
1
V
1
IOL  
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
38  
4
1
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
1
1
1
4
1
dt1  
45  
55  
250  
1
Skew  
tskew  
tdelay  
tjcyc-cyc  
VT = 1.5 V  
ps  
1
Intentional PCI-PCI delay  
Jitter, Cycle to cycle  
VT = 1.5 V  
0 nominal  
500  
ps  
1,9  
1
VT = 1.5 V  
ps  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
7
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Electrical Characteristics - USB48MHz  
NOTES  
PARAMETER  
Long Accuracy  
SYMBOL  
ppm  
CONDITIONS  
MIN  
MAX  
100  
UNITS  
ppm  
see Tperiod min-max values  
-100  
1,2  
2
Clock period  
Tperiod  
Tabs  
VOH  
48.00MHz output nominal  
48.00MHz output nominal  
IOH = -1 mA  
20.83125 20.83542  
ns  
ns  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
20.48130 21.18540  
2
2.4  
0.4  
-29  
-23  
29  
V
1
VOL  
IOL = 1 mA  
V
1
V
OH @MIN = 1.0 V  
VOH@MAX = 3.135 V  
OL @ MIN = 1.95 V  
mA  
mA  
mA  
mA  
V/ns  
V/ns  
%
1
Output High Current  
Output Low Current  
IOH  
1
V
1
IOL  
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
27  
1
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
1
1
2
2
1
1
dt1  
45  
55  
350  
1
Jitter, Cycle to cycle  
tjcyc-cyc  
VT = 1.5 V  
ps  
1
Electrical Characteristics - SMBus Interface  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
2.7  
MAX  
5.5  
UNITS Notes  
SMBus Voltage  
VDD  
V
V
1
1
Low-level Output Voltage  
Current sinking at  
VOLSMB = 0.4 V  
VOLSMB  
@ IPULLUP  
0.4  
IPULLUP  
SMB Data Pin  
4
mA  
1
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
TRI2C  
TFI2C  
1000  
300  
ns  
ns  
1
1
1
Clock/Data Fall Time  
Maximum SMBus Operating  
Frequency  
FSMBUS  
Block Mode  
100  
kHz  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
8
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Electrical Characteristics - REF-14.318MHz  
PARAMETER  
SYMBOL  
CONDITIONS  
see Tperiod min-max values  
14.318MHz output nominal  
14.318MHz output nominal  
IOH = -1 mA  
MIN  
-300  
MAX  
UNITS Notes  
Long Accuracy  
ppm  
300  
ppm  
ns  
ns  
V
1,2  
2
Clock period  
Tperiod  
Tabs  
69.8203  
69.8203  
2.4  
69.8622  
70.86224  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
2
VOH  
1
VOL  
IOL = 1 mA  
0.4  
-33  
V
1
VOH @MIN = 1.0 V,  
Output High Current  
Output Low Current  
IOH  
-33  
30  
mA  
mA  
1
1
V
OH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
OL @MAX = 0.4 V  
IOL  
38  
V
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
4
4
V/ns  
V/ns  
%
1
1
1
1
dt1  
45  
55  
Jitter  
tjcyc-cyc  
VT = 1.5 V  
1000  
ps  
Notes on Electrical Characteristics:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through Vswing centered around differential zero  
3 Vxabs is defined as the voltage where CLK = CLK#  
4 Only applies to the differential rising edge (CLK rising and CLK# falling)  
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of  
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets  
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate  
calculations  
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz  
7 Operation under these conditions is neither implied, nor guaranteed.  
8 Maximum input voltage is not to exceed maximum VDD  
9 See PCI Clock-to-Clock Delay Figure  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
9
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
General I2C serial interface information for the 9UMS9001  
How to Write:  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address D2(H)  
• ICS clock will acknowledge  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address D2(H)  
• ICS clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address D3(H)  
• ICS clock will acknowledge  
(see Note 2)  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock will acknowledge each byte one at a time  
• ICS clock sends Byte 0 through byte X (if X(H)  
was written to byte 8).  
• Controller (host) sends a Stop bit  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
ICS (Slave/Receiver)  
Controller (Host)  
ICS (Slave/Receiver)  
T
starT bit  
starT bit  
T
Slave Address D2(H)  
Slave Address D2(H)  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
RT  
Repeat starT  
Slave Address D3(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
10  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Byte 0 FS Readback, SS Enable, STOP Control Register  
Bit Pin  
Name  
FSLC  
FSLB  
Description  
CPU Freq. Sel. Bit MSB  
CPU Freq. Sel. Bit LSB  
Spread spectrum enable for CPU/SRC/PCI outputs  
Turns On LCD PLL  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
Latch  
Latch  
7
6
5
4
3
2
1
0
-
See Frequency Select Table  
CPU_SS_EN  
LCD_Enable  
SRC3_STOP  
SRC2_STOP  
SRC1_STOP  
SRC0_STOP  
SS Disabled  
Off  
SS Enabled  
On  
1
1
0
0
0
0
SRC 3 Stop Control  
SRC 2 Stop Control  
SRC 1 Stop Control  
SRC 0 Stop Control  
Stops with  
PCI_STOP#  
Assertion  
Free Running  
Byte 1 LCD Quick Config and CPU Stop ControlRegister  
Bit Pin  
Name  
CPU_ITP_STOP  
CPU1_STOP  
CPU0_STOP  
LCD_SS_EN  
LCD_SSC_SEL  
LCD_CF2  
Description  
CPU_ITP Stop Control  
CPU1 Stop Control  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
7
6
5
4
3
2
1
0
Stops with  
CPU_STOP#  
assertion  
On  
0
1
1
1
0
0
0
1
Free Running  
CPU0 Stop Control  
Turns on SS for LCD PLL  
Select down or center SSC  
PLL3 Quick Config Bit 2  
PLL3 Quick Config Bit 1  
PLL3 Quick Config Bit 0  
Off  
Down spread  
Center spread  
See Table 2: LCD Quick Configuration  
LCD_CF1  
LCD_CF0  
Byte 2 Output Enable and Stop Control Register  
Bit Pin  
Name  
PCI_F2_STOP  
PCI1_STOP  
PCI0_STOP  
REF_OE  
USB_OE  
PCIF2_OE  
PCI1_OE  
Description  
Free running PCI Stop Control  
PCI1 Stop Control  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
7
6
5
4
3
2
1
0
Stops with  
PCI_STOP#  
assertion  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
0
1
1
1
1
1
1
1
Free Running  
PCI 0 Stop Control  
Output enable for REF  
Output enable for USB  
Output enable for PCI2  
Output enable for PCI1  
Output enable for PCI0  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
PCI0_OE  
Byte 3 Output Enable Register  
Bit Pin  
Name  
CPU_ITP_OE  
CPU1_OE  
CPU0_OE  
Reserved  
SRC3_OE  
SRC2_OE  
SRC1_OE  
SRC0_OE  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
7
6
5
4
3
2
1
0
Output enable for CPU_ITP  
Output enable for CPU1  
Output enable for CPU0  
Reserved  
Output enable for SRC4  
Output enable for SRC4  
Output enable for SRC4  
Output enable for SRC4  
Output Disabled  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
Output Enabled  
1
1
1
0
1
1
1
1
Output Disabled  
Output Disabled  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
Output Enabled  
Output Enabled  
Byte 4 Output Enable and CLKREQ# Control Register  
Bit Pin  
Name  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
7
6
5
4
3
2
1
0
DOT96_OE  
LCD100_OE  
Reserved  
Reserved  
SRC3_CR  
SRC2_CR  
SRC1_CR  
SRC0_CR  
Output enable for DOT96  
Output enable for LCD100  
Reserved  
Output Disabled  
Output Disabled  
Output Enabled  
Output Enabled  
1
1
0
0
0
0
0
0
Reserved  
SRC3 CLKREQ3# Enable  
SRC2 CLKREQ2# Enable  
SRC1 CLKREQ1# Enable  
SRC0 CLKREQ0# Enable  
Not controlled by  
CLKREQ#  
Controlled by  
CLKREQ#  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
11  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Byte 5 Drive Strength Control Register  
Bit Pin  
Name  
Description  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
7
6
5
4
3
2
1
0
PCI_F2 Strength  
PCI1 Strength  
PCI0 Strength  
48MHz Strength  
REF Strength  
IO_VOUT2  
Sets the PCI_F2 output drive strength  
Sets the PCI1 output drive strength  
Sets the PCI0 output drive strength  
Sets the 48MHz output drive strength  
Sets the REF output drive strength  
IO Output Voltage Select (Most Significant Bit)  
IO Output Voltage Select  
1
1
1
1
1
1
0
1
1 Load  
2 Loads  
2 Loads  
3 Loads  
See Table 3: V_IO Selection  
(Default is 0.8V)  
IO_VOUT1  
IO_VOUT0  
IO Output Voltage Select (Least Significant Bit)  
Byte 6 Reserved Register  
Bit Pin  
Name  
Description  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
0
0
1
1
1
Default  
7
6
5
4
3
2
1
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID  
Bit Pin  
Name  
Description  
Type  
R
R
R
R
R
R
R
R
Default  
7
6
5
4
3
2
1
0
Rev Code Bit 3  
Rev Code Bit 2  
Rev Code Bit 1  
Rev Code Bit 0  
Vendor ID bit 3  
Vendor ID bit 2  
Vendor ID bit 1  
Vendor ID bit 0  
X
X
X
X
0
0
0
1
Revision ID  
Vendor specific  
Vendor ID  
ICS is 0001, binary  
Byte 8 Device ID Register  
Bit Pin  
Name  
Description  
Type  
R
R
R
R
RW  
RW  
RW  
RW  
Default  
7
6
5
4
3
2
1
0
Device_ID3  
Device_ID2  
Device_ID1  
Device_ID0  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
1
1
0
0
0
1
Devide ID = 0011 Hex  
56-pin QFN  
Package ID code  
Reserved  
Reserved  
Reserved  
Reserved  
Byte 9 Test Mode Register  
Bit Pin  
Name  
Description  
Type  
0
1
Default  
Stops with  
PCI_STOP#  
assertion  
7
LCD_STOP  
LCD Stop Control  
RW  
Free Running  
0
6
5
4
3
2
1
0
Reserved  
Reserved  
Test Mode Select  
Test Mode Entry  
Reserved  
Reserved  
Reserved  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
0
0
0
0
0
0
Allows test select, ignores Test Sel input pin  
Enters into test mode, ignores input pin  
Reserved  
Outputs HI-Z  
Normal operation  
Outputs = REF/N  
Test mode  
Reserved  
PLL1_SS  
Reserved  
PLL1 Spread Spectrum Mode  
Down-spread  
Center-spread  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
12  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Test Clarification Table  
Comments  
HW  
SW  
TEST  
REF/N or  
HI-Z  
TEST_SEL TEST_MODE ENTRY BIT  
HW PIN  
<2.0V  
>2.0V  
>2.0V  
>2.0V  
HW PIN  
B9b3  
0
X
X
X
B9b4  
0
0
1
0
OUTPUT  
NORMAL  
HI-Z  
REF/N  
REF/N  
X
0
0
1
Power-up w/ TEST_SEL = 1 to enter test mode  
Cycle power to disable test mode  
TEST_MODE -->low Vth input  
TEST_MODE is a real time input  
>2.0V  
<2.0V  
1
X
1
1
0
REF/N  
HI-Z  
X
If TEST_SEL HW pin is 0 during power-up,  
test mode can be invoked through B9b3.  
If test mode is invoked by B9b3, only B9b4  
is used to select HI-Z or REF/N  
<2.0V  
X
1
1
REF/N  
FSLB/TEST_Mode pin is not used.  
Cycle power to disable test mode, one shot control  
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)  
B9b4: 1= REF/N, Default = 0 (HI-Z)  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
13  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
(Ref. )  
Seating Plane  
(ND - 1)x  
e
&
NE  
ND  
(Ref. )  
Even  
A1  
Index Area  
L
A3  
E2  
N
N
e
(Typ.)  
2
If N &  
NE  
D
Anvil  
Singulation  
are Even  
1
2
1
(N - 1)x  
e
E
OR  
E
(Ref. )  
E2  
2
Sawn  
Singulation  
Top View  
D
b
e
Thermal  
Base  
(Ref.)  
D2  
A
N &  
NE  
Odd  
D
2
D2  
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
C
C
0.08  
THERMALLY ENHANCED, VERY THIN, FINE PITCH  
QUAD FLAT / NO LEAD PLASTIC PACKAGE  
DIMENSIONS  
DIMENSIONS  
SYMBOL  
MIN.  
0.8  
0
0.25 Reference  
0.18 0.3  
0.50 BASIC  
MAX.  
1.0  
ICS 56L  
TOLERANCE  
A
A1  
A3  
b
SYMBOL  
0.05  
N
ND  
56  
14  
NE  
14  
e
D x E BASIC  
D2 MIN. / MAX.  
E2 MIN. / MAX.  
L MIN. / MAX.  
8.00 x 8.00  
4.35 / 4.65  
5.05 / 5.35  
0.30 / 0.50  
Ordering Information  
Part / Order Number  
9UMS9001AKLF  
9UMS9001AKLFT  
Shipping Package  
Tubes  
Package  
56-pin MLF  
56-pin MLF  
Temperature  
0 to +70° C  
0 to +70° C  
Tape and Reel  
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“A” is the device revision designator (will not correlate with the datasheet revision).  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
14  
9UMS9001  
PC MAIN CLOCK - CK540  
Advance Information  
Revision History  
Rev.  
Issue Date  
Who Description  
1. Removed CK505 reference is Device ID byte of SMBus  
Page #  
2. Moved SMBus AFTER electrical characteristics  
3. Made Data sheet Rev A device.  
A
B
8/28/2008  
7/19/2010  
RDW 4. Move to Final  
RDW 1. Corrected Pin type for Pins 8, 21, 23.  
8, 9, 10  
2
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
IDT Singapore Pte. Ltd.  
1 Kallang Sector #07-01/06  
KolamAyer Industrial Park  
Singapore 349276  
IDT Europe Limited  
321 Kingston Road  
Leatherhead, Surrey  
KT22 7TU  
United States  
800 345 7015  
+408 284 8200 (outside U.S.)  
Phone: 65-6-744-3356  
Fax: 65-6-744-1764  
England  
Phone: 44-1372-363339  
Fax: 44-1372-378851  
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks  
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks  
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
IDT® PC MAIN CLOCK - CK540  
1247B—07/19/10  
15  
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