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5PB1206NDGK

型号：

5PB1206NDGK

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

379 K

下载PDF手册
3-Channel High-Performance TCXO/LVCMOS  
Clock Buffer Family  
5PB12xx  
DATASHEET  
Description  
Features  
The 5PB12xx is a high-performance TCXO/LVCMOS clock  
fanout buffer family with individual OE pin for each output.  
The CLKIN pin can accept either a square wave (LVCMOS)  
or clipped sine wave (such as TCXO clipped sine wave  
output) as input.  
• Extremely low operating and standby current consumption  
• Low RMS additive phase jitter  
• Family supports 1.8V to 3.3V power supply voltage:  
• For 1.8V supply: 5PB1203, 5PB1204, 5PB1206  
• For 2.5V / 3.3V supply: 5PB1213, 5PB1214, 5PB1216  
There are 3 different fan-out versions available: 1:3, 1:4 and  
1:6.  
• Three, four, and six outputs with individual Output Enable  
pin  
The 5PB12xx has industry-leading low jitter and extremely  
low current consumption, making it ideal for smart mobile  
devices.  
• One input  
• OE_OSC control pin to enable/disable reference TCXO/XO  
• Small 10-pin, 16-pin and 20-pin packages available  
• Industrial -40º to +105ºC temperature range  
Typical Applications  
• Smart Mobile Handsets  
• RF and baseband peripheral clock distribution  
• Automotive  
Block Diagram  
CLKOUT1  
CLKOUT2  
CLKIN  
OE_OSC  
OE1  
OE2  
Control  
Logic  
CLKOUT6  
OE6  
5PB12xx FEBRUARY 28, 2018  
1
©2018 Integrated Device Technology, Inc.  
5PB12xx DATASHEET  
Pin Assignments  
19  
18  
17  
20  
16  
15  
14  
13  
12  
16  
1
2
3
4
5
15  
14  
13  
12  
11  
OE2  
OE3  
VDD  
VDD  
CLKOUT3  
GND  
VDD  
1
2
3
4
5
10  
9
1
2
3
4
VDD  
OE2  
VDD  
CLKOUT2  
CLKOUT1  
OE2  
CLKOUT3  
CLKOUT4  
GND  
11  
10  
9
CLKOUT2  
CLKOUT3  
GND  
8
CLKIN  
OE_OSC  
OE3  
GND  
OE3  
7
GND  
OE6  
6
OE1  
5
6
7
8
CLKOUT5  
5PB1203 / 5PB1213  
10-pin 2mm x 2mm DFN  
6
7
8
9
10  
5PB1204 / 5PB1214  
16-pin, 2.5mm x 2.5mm VFQFPN  
5PB1206 / 5PB1216  
20-pin, 3mm x 3mm VFQFPN  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Pin Description  
5PB1203  
5PB1213  
5PB1204  
5PB1214  
5PB1206  
5PB1216  
Connect 1.8V to 5PB1203/5PB1204/5PB1206.  
Connect 2.5V or 3.3V to 5PB1213/5PB1214/5PB1216.  
VDD  
2
2, 7, 12  
3, 9, 15  
Power  
GND  
1
3
3, 9, 14  
15  
4, 12, 18  
20  
Power  
Input  
Power supply ground.  
CLKIN  
Reference input pin. Connect to LVCMOS input or TCXO.  
Input Crystal Oscillator enable pin. Follow Enable Function Truth Table.  
If all OE pins are low then OE_OSC is low. Otherwise OE_OSC is high,  
enabling reference crystal oscillator.  
OE_OSC  
4
6
8
Output  
OE1  
OE2  
6
7
16  
1
19  
1
Input  
Input  
Output Enable pin for CLKOUT1. Active High. Internal 120kΩ pull-down.  
Output Enable pin for CLKOUT2. Active High. Internal 120kΩ pull-down.  
Output Enable pin for CLKOUT3. Active High. Internal 120kΩ pull-down.  
Output Enable pin for CLKOUT4. Active High. Internal 120kΩ pull-down.  
Output Enable pin for CLKOUT5. Active High. Internal 120kΩ pull-down.  
Output Enable pin for CLKOUT6. Active High. Internal 120kΩ pull-down.  
Clock Output 1. Same frequency as CLKIN.  
OE3  
5
4
2
Input  
OE4  
—
—
—
8
5
6
Input  
OE5  
—
—
13  
11  
10  
8
7
Input  
OE6  
5
Input  
CLKOUT1  
CLKOUT2  
CLKOUT3  
CLKOUT4  
CLKOUT5  
CLKOUT6  
17  
16  
14  
13  
11  
10  
Output  
Output  
Output  
Output  
Output  
Output  
9
Clock Output 2. Same frequency as CLKIN.  
10  
—
—
—
Clock Output 3. Same frequency as CLKIN.  
Clock Output 4. Same frequency as CLKIN.  
—
—
Clock Output 5. Same frequency as CLKIN.  
Clock Output 6. Same frequency as CLKIN.  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
2
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
Enable Function Truth Table  
Input  
Output  
OE1 OE2 OE3 OE4 OE5 OE6 OE_OSC CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6  
0
1
0
0
0
0
0
0
0
0
0
0
0
1
Hi-Z  
CLOCK  
CLOCK  
…
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
1
1
0
0
0
0
1
CLOCK  
…
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
…
1
…
1
…
1
…
1
…
1
…
1
…
1
…
…
…
…
CLOCK  
CLOCK  
CLOCK  
CLOCK  
CLOCK  
CLOCK  
External Components  
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be  
connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33series terminating resistor may  
be used on each clock output if the trace is longer than 1 inch.  
To achieve the low output skew that the 5PB12xx is capable of, careful attention must be paid to board layout. Essentially, all  
four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will  
be degraded. For example, using a 30series termination on one output (with 33on the others) will cause at least 15ps of  
skew.  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 5PB12xx. These ratings, which are standard values  
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions  
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
Item  
Rating  
Supply Voltage, VDD  
3.8V  
Output Enable and All Inputs/Outputs  
Ambient Operating Temperature (extended)  
Storage Temperature  
-0.5 V to VDD + 0.5 V  
-40 to +105C  
-65 to +150C  
125C  
Junction Temperature  
Soldering Temperature  
260C  
FEBRUARY 28, 2018  
3
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
DC Electrical Characteristics  
(VDD = 1.8V, 2.5V, 3.3V)  
VDD = 1.8V ±5%, for 5PB1203 / 1204 / 1206, ambient temperature -40° to +105°C, unless stated otherwise.  
Parameter  
Symbol  
VDD  
VIH  
Conditions  
Min.  
1.71  
Typ.  
Max.  
1.89  
Units  
V
Operating Voltage  
Input High Voltage, CLKIN  
Input Low Voltage, CLKIN  
Input High Voltage, OE  
Input Low Voltage, OE  
Output High Voltage  
LVCMOS input. Note 1  
VDD/2 + 200  
VDD  
mV  
mV  
V
VIL  
LVCMOS input. Note 1  
VDD/2 - 200  
VDD  
VIH  
0.7xVDD  
0.8xVDD  
VIL  
0.3xVDD  
V
VOH  
VOL  
ZO  
IOH = -4mA  
IOL = 4mA  
V
Output Low Voltage  
0.2xVDD  
V
Nominal Output Impedance  
Input Capacitance  
17  
5
CIN  
pF  
Operating Supply Current  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
5.10  
0.02  
9.30  
2.51  
11.90  
2.5  
5PB1203  
5PB1204  
5PB1206  
0.03  
4
IDD  
mA  
4
VDD = 2.5V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise.  
Parameter  
Symbol  
VDD  
VIH  
Conditions  
Min.  
2.375  
Typ.  
Max.  
2.625  
Units  
V
Operating Voltage  
Input High Voltage, CLKIN  
Input Low Voltage, CLKIN  
Input High Voltage, OE  
Input Low Voltage, OE  
Output High Voltage  
LVCMOS input. Note 1  
VDD/2 + 200  
VDD  
mV  
mV  
V
VIL  
LVCMOS input. Note 1  
VDD/2 - 200  
VDD  
VIH  
0.7xVDD  
0.8xVDD  
VIL  
0.3xVDD  
V
VOH  
VOL  
ZO  
IOH = -4mA  
IOL = 4mA  
V
Output Low Voltage  
0.2xVDD  
V
Nominal Output Impedance  
Input Capacitance  
17  
5
CIN  
ICLK, OE pin  
pF  
Operating Supply Current  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
6.68  
0.05  
10.2  
3.47  
16.5  
3.50  
5PB1213  
5PB1214  
5PB1216  
0.5  
5
IDD  
mA  
5
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
4
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
VDD = 3.3V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise  
Parameter  
Symbol  
VDD  
VIH  
Conditions  
Min.  
3.135  
Typ.  
Max.  
3.465  
Units  
V
Operating Voltage  
Input High Voltage, CLKIN  
Input Low Voltage, CLKIN  
Input High Voltage, OE  
Input Low Voltage, OE  
Output High Voltage  
LVCMOS input. Note 1  
VDD/2 + 200  
VDD  
mV  
mV  
V
VIL  
LVCMOS input. Note 1  
VDD/2 - 200  
VDD  
VIH  
0.7xVDD  
0.8xVDD  
VIL  
0.3xVDD  
V
VOH  
VOL  
ZO  
IOH = -4mA  
IOL = 4mA  
V
Output Low Voltage  
0.2xVDD  
V
Nominal Output Impedance  
Input Capacitance  
17  
5
CIN  
ICLK, OE pin  
pF  
Operating Supply Current  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
CLKIN = 26MHz, all outputs enabled  
CLKIN = Low or High, all outputs disabled  
9.10  
0.22  
13.4  
4.28  
21.4  
4.60  
5PB1213  
5PB1214  
5PB1216  
0.5  
7
IDD  
mA  
7
Notes: 1. Nominal switching threshold is VDD/2.  
FEBRUARY 28, 2018  
5
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
AC Electrical Characteristics  
(VDD = 1.8V, 2.5V, 3.3V)  
VDD = 1.8V ±5%; for 5PB1203 / 1204 / 1206, ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
0
200  
1.0  
1.0  
2.5  
MHz  
ns  
Output Rise Time  
tOR  
tOF  
0.36 to 1.44V, CL = 5pF  
0.6  
0.6  
2.0  
420  
Output Fall Time  
1.44 to 0.36V, CL = 5pF  
Note 1  
ns  
Propagation Delay  
Note 1  
1.5  
ns  
Buffer Additive Phase Jitter, RMS  
26MHz TCXO clipped sine wave input,  
Integration Range: 12kHz to 20MHz  
fs  
125MHz LVCMOS input,  
Integration Range: 12kHz to 20MHz  
42  
20  
fs  
Output to Output Skew  
Device to Device Skew  
tSKEWO−O Note 2, Rising edges at VDD/2  
tSKEWD-D Rising edges at VDD/2  
50  
200  
3
ps  
ps  
Delay for Output Enable / Disable  
Time ENABLEx to BCLKn  
tEN/ DIS  
t
CL < 5pF  
cycles  
Start-up Time  
tSTART-UP  
VINpp  
2
ms  
V
TCXO Clock Clipped Sine Wave  
Input Voltage Swing Level  
VDD = 1.8V, should connect to CLKIN  
through AC coupling and bias circuit  
0.8  
VDD = 2.5V ±5%; for 5PB1213 / 1214 / 1216, ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
0
200  
1.0  
1.0  
2.7  
MHz  
ns  
Output Rise Time  
tOR  
tOF  
0.5 to 2.0V, CL = 5pF  
0.6  
0.6  
2.2  
280  
Output Fall Time  
2.0 to 0.5V, CL = 5pF  
Note 1  
ns  
Propagation Delay  
Note 1  
1.7  
ns  
Buffer Additive Phase Jitter, RMS  
26MHz TCXO clipped sine wave input,  
Integration Range: 12kHz to 20MHz  
fs  
125MHz LVCMOS input,  
Integration Range: 12kHz to 20MHz  
30  
20  
fs  
Output to Output Skew  
Device to Device Skew  
tSKEWO−O Note 2, Rising edges at VDD/2  
tSKEWD-D Rising edges at VDD/2  
50  
200  
3
ps  
ps  
Delay for Output Enable / Disable  
Time ENABLEx to BCLKn  
tEN/ DIS  
t
CL < 5pF  
cycles  
Start-up Time  
tSTART-UP Part start-up time for valid outputs after  
VDD ramp-up  
2
ms  
V
TCXO Clock Clipped Sine Wave  
Input Voltage Swing Level  
VINpp  
VDD = 2.5V, should connect to CLKIN  
through AC coupling and bias circuit  
0.8  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
6
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
VDD = 3.3V ±5%; for 5PB1213 / 1214 / 1216, ambient Temperature -40° to +105°C, unless stated otherwise  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
0
200  
1.0  
1.0  
2.4  
MHz  
ns  
Output Rise Time  
tOR  
tOF  
0.66 to 2.64V, CL = 5pF  
0.6  
0.6  
1.9  
377  
Output Fall Time  
2.64 to 0.66V, CL = 5pF  
Note 1  
ns  
Propagation Delay  
Note 1  
1.4  
ns  
Buffer Additive Phase Jitter, RMS  
26MHz TCXO clipped sine wave input,  
Integration Range: 12kHz to 20MHz  
fs  
125MHz LVCMOS input,  
Integration Range: 12kHz to 20MHz  
18  
20  
fs  
Output to Output Skew  
Device to Device Skew  
tSKEWO−O Note 2, Rising edges at VDD/2  
tSKEWD-D Rising edges at VDD/2  
50  
200  
3
ps  
ps  
Delay for Output Enable / Disable  
Time ENABLEx to BCLKn  
tEN/ DIS  
t
CL < 5pF  
cycles  
Start-up Time  
tSTART-UP Part start-up time for valid outputs after  
VDD ramp-up  
2
ms  
V
TCXO Clock Clipped Sine Wave  
Input Voltage Swing Level  
VINpp  
VDD = 3.3V, should connect to CLKIN  
through AC coupling and bias circuit  
0.5  
Notes:  
1. With rail to rail input clock.  
2. Between any 2 outputs with equal loading.  
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.  
Test Load and Circuit  
50ohms  
5 inche  
s
Rs=33ohm  
CL = 5pF  
AC Coupling and Bias Circuit  
Component  
Value  
VDD  
C1  
R1  
R2  
1µF  
10k  
10k  
R1  
VDD  
C1  
TCXO  
IDT  
5PB12xx  
R2  
FEBRUARY 28, 2018  
7
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1203 / 5PB1213 10-pin DFN)  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
8
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1203 / 5PB1213 10-pin DFN), cont.  
FEBRUARY 28, 2018  
9
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1204 / 5PB1214 16-pin VFQFPN)  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
10  
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1204 / 5PB1214 16-pin VFQFPN), cont.  
FEBRUARY 28, 2018  
11  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1206 / 5PB1216 20-pin VFQFPN)  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
12  
FEBRUARY 28, 2018  
5PB12xx DATASHEET  
Package Outline Drawings (5PB1206 / 5PB1216 20-pin VFQFPN), cont.  
FEBRUARY 28, 2018  
13  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
5PB12xx DATASHEET  
Ordering Information  
Part / Order Number  
5PB1203NTGK  
5PB1203NTGK8  
5PB1213NTGK  
5PB1213NTGK8  
5PB1204CMGK  
5PB1204CMGK8  
5PB1214CMGK  
5PB1214CMGK8  
5PB1206NDGK  
5PB1206NDGK8  
5PB1216NDGK  
5PB1216NDGK8  
Shipping Packaging  
Package  
Temperature  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
-40 to +105°C  
Cut Tape  
Tape and Reel  
Cut Tape  
10-pin DFN  
10-pin DFN  
10-pin DFN  
Tape and Reel  
Cut Tape  
10-pin DFN  
16-pin VFQFPN  
16-pin VFQFPN  
16-pin VFQFPN  
16-pin VFQFPN  
20-pin VFQFPN  
20-pin VFQFPN  
20-pin VFQFPN  
20-pin VFQFPN  
Tape and Reel  
Cut Tape  
Tape and Reel  
Tube  
Tape and Reel  
Tube  
Tape and Reel  
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.  
Marking Diagrams  
XXX  
YWW$  
206K  
204K  
Y**  
203K  
YW**  
16-pin VFQFPN  
10-pin DFN  
20-pin VFQFPN  
XXX  
YWW$  
216K  
213K  
YW**  
214K  
Y**  
20-pin VFQFPN  
10-pin DFN  
16-pin VFQFPN  
Notes:  
1. “**” is the lot number.  
2. “YWW”, “YW”, or “Y” are the last digit(s) of the year and week that the part was assembled.  
3. “$” denotes mark code.  
4. “K” denotes extended temperature range device.  
5. “XXX” denotes last three characters of Asm lot.  
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY  
14  
FEBRUARY 28, 2018  
Revision History  
Date  
Description of Change  
February 28, 2018  
1. Updated CLKIN input high and low voltage ratings in DC characterization tables.  
2. Updated Absolute Maximum supply voltage (VDD) from 3.465V to 3.8V.  
April 10, 2017  
July 11, 2016  
1. Updated Operating Supply Current and Operating Voltage values in DC electrical characteristics tables.  
2. Updated Propagation Delay and Output skew values in AC electrical characteristics tables.  
3. Updated package outline drawings.  
4. Updated legal disclaimer.  
Initial release.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		5PB1102 [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102CMGI [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102CMGI8 [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102CMGK [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102CMGK8 [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102PGG [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102PGGI [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102PGGI8 [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102PGGK [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

IDT

 		5PB1102PGGK8 [ 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family ] 21 页

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