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9ZXL1951DNHGI8

型号：

9ZXL1951DNHGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

329 K

下载PDF手册
19-Output DB1900ZL Derivative for  
PCIe Gen1–4 and QPI/UPI  
9ZXL1951D  
Datasheet  
Description  
Features  
▪ LP-HCSL outputs with 85Ω Zout; eliminates 76 termination  
The 9ZXL1951D is a second-generation, enhanced performance  
DB1900ZL derivative buffer. The part is a pin-compatible upgrade  
to the 9ZXL1951A, offering a much improved phase jitter  
performance. It has 8 OE# pins that can be configured via SMBus  
to control up to 16 of the device's 19 outputs, and is packaged in a  
6 x 6 mm QFN package for maximum space savings. A fixed  
external feedback maintains low drift for critical QPI/UPI  
applications.  
resistors, saves 130mm2 area  
▪ 8 OE# pins configurable to control up to 16 outputs; easy power  
management  
▪ 9 selectable SMBus addresses; multiple devices can share  
same SMBus segment  
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL  
topologies  
▪ Hardware/SMBus control of PLL bandwidth and bypass;  
PCIe Clocking Architectures  
Supported  
change mode without power cycle  
▪ Spread spectrum compatible; tracks spreading input clock for  
▪ Common Clocked (CC)  
EMI reduction  
▪ Independent Reference (IR) with and without spread spectrum  
▪ 100MHz PLL mode; UPI support  
▪ DIF input and DIF outputs on outer row of pins; easy board  
routing  
Recommended Applications  
▪ 6 x 6 mm dual-row 80-GQFN; smallest 19-output Z-buffer  
▪ Servers, Storage, Networking, SSDs  
Output Features  
Key Specifications  
19 Low-Power (LP) HCSL output pairs with 85Ω Zout  
▪ Cycle-to-cycle jitter: < 50ps  
▪ Output-to-output skew: < 50ps  
▪ Input-to-output delay: Fixed at 0ps  
▪ Input-to-output delay variation: < 50ps  
▪ Phase jitter: PCIe Gen4 < 0.5ps rms  
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms  
▪ Phase jitter: IF-UPI < 1.0ps rms  
Block Diagram  
VDDR3.3  
VDDA3.3  
VDDO3.3 x 4  
FBOUT_NC#  
FBOUT_NC  
PLL  
DIF_IN#  
DIF_IN  
DIF18#  
DIF18  
vSADR0_tri  
vSADR1_tri  
19  
outputs  
SMBus  
Engine  
Factory  
Configuration  
SMBCLK  
SMBDAT  
DIF0#  
DIF0  
^vHIBW_BYPM-LOBW#  
CKPWRGD_PD#  
^OE[5:12]#  
Control Logic  
EPAD/GND  
©2018 Integrated Device Technology, Inc.  
1
July 3, 2018  
9ZXL1951D Datasheet  
Pin Assignments  
Figure 1. Pin Assignments for 6 × 6 mm 80-GQFN Package – Top View  
1
2
3
4
5
6
7
8
9
10  
11  
12  
DIF16#  
DIF16  
DIF15#  
DIF15  
DIF14#  
DIF14  
NC  
DIF13#  
DIF13  
DIF12#  
DIF12  
DIF11#  
A
B
C
D
E
F
A
B
C
D
E
F
^v HIBW_BYP  
M_LOBW#  
v SADR0_tri v SADR1_tri  
DIF17  
DIF17#  
DIF18  
DIF18#  
NC  
VDDO3.3  
NC  
NC  
NC  
VDDA3.3  
NC  
^OE12#  
VDDO3.3  
^OE11#  
NC  
DIF11  
DIF10#  
DIF10  
NC  
NC  
NC  
^OE10#  
NC  
9ZXL1951D  
6 x 6 x 0.5 mm  
80-GQFN Package  
Top View  
FBOUT_NC#  
DIF9#  
DIF9  
FBOUT_NC  
DIF_IN  
^OE9#  
G
H
J
G
H
J
EPAD is GND  
CKPWRGD_  
PD#  
DIF_IN# VDDR3.3  
DIF8#  
DIF8  
DIF0  
DIF0#  
DIF1  
NC  
NC  
^OE8#  
^OE7#  
DIF7#  
DIF7  
K
L
K
L
VDDO3.3  
NC  
SMBDAT SMBCLK  
NC  
NC  
^OE5#  
NC  
^OE6#  
VDDO3.3  
DIF1#  
DIF2  
DIF2#  
DIF3  
DIF3#  
NC  
DIF4  
DIF4#  
DIF5  
DIF5#  
DIF6  
DIF6#  
M
M
1
2
3
4
5
6
7
8
9
10  
11  
12  
©2018 Integrated Device Technology, Inc.  
2
July 3, 2018  
9ZXL1951D Datasheet  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
A
1
2
3
4
5
6
7
8
9
DIF16#  
DIF16  
DIF15#  
DIF15  
DIF14#  
DIF14  
NC  
Output Differential complementary clock output.  
Output Differential true clock output.  
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
Output Differential complementary clock output.  
Output Differential true clock output.  
Output Differential complementary clock output.  
Output Differential true clock output.  
—
No connection.  
DIF13#  
DIF13  
Output Differential complementary clock output.  
Output Differential true clock output.  
10 DIF12#  
11 DIF12  
12 DIF11#  
Output Differential complementary clock output.  
Output Differential true clock output.  
Output Differential complementary clock output.  
Output Differential true clock output.  
1
2
3
4
5
6
DIF17  
VDDO3.3  
NC  
Power Power supply for outputs, nominal 3.3V.  
—
—
No connection.  
No connection.  
NC  
VDDA3.3  
NC  
Power 3.3V power for the PLL core.  
—
No connection.  
SMBus address bit. This is a tri-level input that works in conjunction with other  
SADR pins to decode SMBus addresses. It has an internal 120kΩ pull-down  
resistor. See the SMBus Addressing table.  
B
B
7
8
9
vSADR0_tri  
Input  
SMBus address bit. This is a tri-level input that works in conjunction with other  
SADR pins to decode SMBus addresses. It has an internal 120kΩ pull-down  
resistor. See the SMBus Addressing table.  
vSADR1_tri  
Input  
Tri-level input to select High BW, Bypass or Low BW Mode. This pin is biased to  
VDD/2 (Bypass Mode) with internal pull-up/pull-down resistors. See PLL Operating  
Mode table for details.  
Latched  
In  
B
B
^vHIBW_BYPM_LOBW#  
Active low input for enabling output 12. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
10 ^OE12#  
Input  
B
B
C
C
11 VDDO3.3  
12 DIF11  
Power Power supply for outputs, nominal 3.3V.  
Output Differential true clock output.  
1
2
DIF17#  
NC  
Output Differential complementary clock output.  
—
No connection.  
Active low input for enabling output 11. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
C
11 ^OE11#  
Input  
©2018 Integrated Device Technology, Inc.  
3
July 3, 2018  
9ZXL1951D Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
12 DIF10#  
Name  
Type  
Description  
C
Output Differential complementary clock output.  
Output Differential true clock output.  
D
D
D
D
E
E
1
2
DIF18  
NC  
—
—
No connection.  
No connection.  
11 NC  
12 DIF10  
Output Differential true clock output.  
1
2
DIF18#  
NC  
Output Differential complementary clock output.  
—
No connection.  
Active low input for enabling output 10. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
E
11 ^OE10#  
12 NC  
Input  
E
F
—
—
No connection.  
1
NC  
No connection.  
Complementary half of differential feedback output. This pin should NOT be  
F
2
FBOUT_NC#  
Output connected to anything outside the chip. It exists to provide delay path matching to  
get 0 propagation delay.  
F
F
11 NC  
—
No connection.  
12 DIF9#  
Output Differential complementary clock output.  
G
1
DIF_IN  
Input  
HCSL true input.  
True half of differential feedback output. This pin should NOT be connected to  
G
G
2
FBOUT_NC  
Output anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
Active low input for enabling output 9. This pin has an internal pull-up resistor.  
11 ^OE9#  
12 DIF9  
Input  
1 =disable outputs, 0 = enable outputs.  
G
H
Output Differential true clock output.  
1
DIF_IN#  
Input  
HCSL complementary input.  
3.3V power for differential input clock (receiver). This VDD should be treated as an  
analog power rail and filtered appropriately.  
H
2
VDDR3.3  
Power  
3.3V input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters Power  
Down Mode.  
H
11 CKPWRGD_PD#  
12 DIF8#  
Input  
H
J
Output Differential complementary clock output.  
Output Differential true clock output.  
1
2
DIF0  
NC  
J
—
No connection.  
Active low input for enabling output 8. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
J
11 ^OE8#  
12 DIF8  
Input  
J
K
K
Output Differential true clock output.  
1
2
DIF0#  
NC  
Output Differential complementary clock output.  
—
No connection.  
©2018 Integrated Device Technology, Inc.  
4
July 3, 2018  
9ZXL1951D Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type  
Description  
Active low input for enabling output 7. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
K
11 ^OE7#  
12 DIF7#  
Input  
K
L
L
L
L
L
L
L
Output Differential complementary clock output.  
Output Differential true clock output.  
1
2
3
4
5
6
7
DIF1  
VDDO3.3  
NC  
Power Power supply for outputs, nominal 3.3V.  
—
I/O  
Input  
—
No connection.  
SMBDAT  
SMBCLK  
NC  
Data pin of SMBUS circuitry.  
Clock pin of SMBUS circuitry.  
No connection.  
NC  
—
No connection.  
Active low input for enabling output 5. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
L
L
L
8
9
^OE5#  
NC  
Input  
—
No connection.  
Active low input for enabling output 6. This pin has an internal pull-up resistor.  
1 = disable outputs, 0 = enable outputs.  
10 ^OE6#  
Input  
L
L
11 VDDO3.3  
12 DIF7  
Power Power supply for outputs, nominal 3.3V.  
Output Differential true clock output.  
M
M
M
M
M
M
M
M
M
M
M
M
—
1
2
3
4
5
6
7
8
9
DIF1#  
DIF2  
DIF2#  
DIF3  
DIF3#  
NC  
Output Differential complementary clock output.  
Output Differential true clock output.  
Output Differential complementary clock output.  
Output Differential true clock output.  
Output Differential complementary clock output.  
—
No connection.  
DIF4  
DIF4#  
DIF5  
Output Differential true clock output.  
Output Differential complementary clock output.  
Output Differential true clock output.  
10 DIF5#  
11 DIF6  
12 DIF6#  
EPAD  
Output Differential complementary clock output.  
Output Differential true clock output.  
Output Differential complementary clock output.  
GND  
Connect EPAD to ground.  
©2018 Integrated Device Technology, Inc.  
5
July 3, 2018  
9ZXL1951D Datasheet  
Pow er Management  
Table 2. Pow er Management and Output Control Truth Table  
Inputs  
Outputs  
DIFx FBOUT_NC  
PLL State  
OEx bit  
Byte[2:0]  
OE Pin CFG bit  
Byte[4,8]  
CKPWRGD_PD#  
DIF_IN  
X
OEx# Pin  
0
1
X
0
1
1
1
X
X
0
1
1
X
X
X
0
Low/Low  
Low/Low  
Running  
Running  
Low/Low  
Low/Low  
Running  
Running  
Running  
Running  
Off  
On  
On  
On  
On  
Running  
1
Running  
1
Table 3. Pow er Connections  
Pin Number  
Description  
VDD  
GND  
B5  
H2  
Analog PLL  
Analog input  
DIF clocks  
EPAD  
B2, B11, L2, L11  
Table 4. PLL Operating Mode Table  
HIBW_BYPM_LOBW#  
Byte0, bits (7:6)  
Low (PLL Low BW)  
Mid (Bypassed and Off)  
High (PLL High BW)  
00  
01  
11  
©2018 Integrated Device Technology, Inc.  
6
July 3, 2018  
9ZXL1951D Datasheet  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the  
device. Functional operation of the 9ZXL1951D at absolute maximum ratings is not implied. Exposure to absolute maximum rating  
conditions may affect device reliability.  
Table 5. Absolute Maximum Ratings  
Parameter  
Symbol  
Conditions  
Minimum  
Typical Maximum Units Notes  
Supply Voltage  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
Storage Temperature  
Junction Temperature  
Input ESD Protection  
V
3.9  
V
V
1,2  
1
DDx  
V
GND - 0.5  
IL  
V
Except for SMBus interface.  
SMBus clock and data pins.  
V
+ 0.5  
DD  
V
1,3  
1
IH  
V
3.9  
150  
125  
V
IHSMB  
T
-65  
°C  
°C  
V
1
S
T
1
J
ESD Prot Human Body Model.  
2500  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 3.9V.  
Electrical Characteristics  
TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions.  
Table 6. SMBus  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
VILSMB  
0.8  
VDDSMB  
0.4  
V
V
VIHSMB  
2.1  
VOLSMB At IPULLUP.  
IPULLUP At VOL.  
VDDSMB  
V
4
mA  
V
Nominal Bus Voltage  
2.7  
3.6  
1000  
300  
1
1
1
5
SCLK/SDATA Rise Time  
SCLK/SDATA Fall Time  
SMBus Operating Frequency  
tRSMB  
tFSMB  
fSMB  
(Max VIL - 0.15V) to (Min VIH + 0.15V).  
(Min VIH + 0.15V) to (Max VIL - 0.1V).  
SMBus operating frequency.  
ns  
ns  
kHz  
400  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
5 The differential input clock must be running for the SMBus to be active.  
©2018 Integrated Device Technology, Inc.  
7
July 3, 2018  
9ZXL1951D Datasheet  
Table 7. DIF_IN Clock Input Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input Crossover Voltage –  
DIF_IN  
VCROSS Cross over voltage.  
VSWING Differential value.  
150  
900  
mV  
1
Input Swing – DIF_IN  
Input Slew Rate – DIF_IN  
Input Leakage Current  
Input Duty Cycle  
300  
0.4  
-5  
mV  
V/ns  
μA  
1
dv/dt  
IIN  
Measured differentially.  
8
5
1,2  
VIN = VDD , VIN = GND.  
dtin  
Measurement from differential waveform.  
45  
0
55  
125  
%
1
1
Input Jitter – Cycle to Cycle  
JDIFIn Differential measurement.  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through ±75mV window centered around differential zero.  
Table 8. Input/Supply/Common Parameters  
Parameter  
Symbol  
VDD  
Conditions  
Minimum Typical Maximum Units Notes  
Supply Voltage  
x
Supply voltage for core and analog.  
3.135  
-40  
3.3  
25  
3.465  
85  
V
Ambient Operating  
Temperature  
TAMB  
VIH  
Industrial range.  
°C  
Single-ended inputs, except SMBus, tri-level  
inputs.  
Input High Voltage  
Input Low Voltage  
2
VDD + 0.3  
0.8  
V
V
Single-ended inputs, except SMBus, tri-level  
inputs.  
VIL  
GND - 0.3  
Input High Voltage  
Input Mid Voltage  
Input Low Voltage  
VIH  
VIM  
VIL  
IIN  
Tri-level inputs.  
2.2  
1.2  
VDD + 0.3  
V
V
Tri-level inputs.  
VDD/2  
1.8  
0.8  
5
Tri-level inputs.  
GND - 0.3  
-5  
V
Single-ended inputs, VIN = GND, VIN = VDD.  
Single-ended inputs.  
μA  
Input Current  
V
IN = 0 V; inputs with internal pull-up resistors.  
IINP  
-100  
100  
μA  
VIN = VDD; inputs with internal pull-down  
resistors.  
Fibyp  
Fipll  
Lpin  
CIN  
VDD = 3.3V, Bypass Mode.  
1
400  
102  
7
MHz  
MHz  
nH  
Input Frequency  
Pin Inductance  
VDD = 3.3V, 100MHz PLL Mode.  
98.5  
100.00  
1
1
Logic inputs, except DIF_IN.  
1.5  
1.5  
5
pF  
Capacitance  
CINDIF_IN DIF_IN differential clock inputs.  
2.7  
6
pF  
1,4  
1
COUT  
Output pin capacitance.  
pF  
From VDD power-up and after input clock  
stabilization or de-assertion of PD# to 1st  
clock.  
Clk Stabilization  
TSTAB  
1.0  
1.8  
ms  
1,2  
©2018 Integrated Device Technology, Inc.  
8
July 3, 2018  
9ZXL1951D Datasheet  
Table 8. Input/Supply/Common Parameters (Cont.)  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input SS  
Modulation  
Frequency PCIe  
Allowable frequency for PCIe applications  
(Triangular modulation).  
fMODINPCIe  
30  
4
31.500  
33  
10  
kHz  
DIF start after OE# assertion.  
DIF stop after OE# deassertion.  
OE# Latency  
tLATOE#  
5
clocks 1,2,3  
Tdrive_PD#  
Tfall  
tDRVPD  
DIF output enable after PD# de-assertion.  
Fall time of control inputs.  
49  
300  
5
μs  
ns  
ns  
1,3  
2
tF  
Trise  
tR  
Rise time of control inputs.  
5
2
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Control input must be monotonic from 20% to 80% of input swing.  
3 Time from deassertion until outputs are > 200mV.  
4 DIF_IN input.  
©2018 Integrated Device Technology, Inc.  
9
July 3, 2018  
9ZXL1951D Datasheet  
Table 9. HCSL/LP-HCSL Outputs  
Industry  
Limit  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
dV/dt  
dV/dt  
Scope averaging on, fast setting.  
Scope averaging on, slow setting.  
2
1
2.6  
1.8  
4
3
1 – 4  
1 – 4  
V/ns 1,2,3  
V/ns 1,2,3  
Slew Rate  
Slew Rate  
Matching  
ΔdV/dt  
Single-ended measurement.  
4.3  
20  
20  
%
1,4,7  
Maximum Voltage  
Minimum Voltage  
Vmax  
Vmin  
Measurement on single ended  
signal using absolute value.  
(scope averaging off).  
660  
751  
-1.9  
850  
150  
1150  
-300  
7
7
mV  
-150  
Crossing Voltage  
(abs)  
Vcross_abs Scope averaging off.  
250  
381  
15  
550  
140  
250 – 550 mV  
140 mV  
1,5,7  
1,6,7  
Crossing Voltage  
(var)  
Δ-Vcross Scope averaging off.  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 Measured from differential waveform.  
3 Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the  
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge  
(i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)  
allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.  
7 At default SMBus settings.  
Table 10. Current Consumption  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
IDDVDD  
All outputs 100MHz, CL = 2pF; Zo = 85Ω.  
171  
45  
200  
55  
mA  
mA  
Operating Supply  
Current  
PLL Mode, all outputs 100MHz, CL = 2pF;  
Zo = 85Ω.  
IDDVDDA/R  
1
IDDVDDPD  
All differential pairs low-low  
1
4
2
6
mA  
mA  
Powerdown Current  
IDDVDDA/RPD All differential pairs low-low  
1 In Bypass Mode (PLL off), IDDVDDA/R is 12mA.  
©2018 Integrated Device Technology, Inc.  
10  
July 3, 2018  
9ZXL1951D Datasheet  
Table 11. Skew and Differential Jitter Parameters  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum Units Notes  
Input-to-output skew in PLL Mode nominal  
value at 25°C, 3.3V.  
1,2,4,  
5,8  
CLK_IN, DIF[x:0]  
tSPO_PLL  
-100  
2.3  
-14  
2.9  
0
100  
3.5  
50  
ps  
ns  
ps  
ps  
ps  
Input-to-output skew in Bypass Mode nominal  
value at 25°C, 3.3V.  
1,2,3,  
5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
Input-to-output skew variation in PLL Mode  
across voltage and temperature.  
1,2,3,  
5,8  
tDSPO_PLL  
-50  
Input-to-output skew variation in Bypass Mode  
across commercial voltage and temperature.  
1,2,3,  
5,8  
CLK_IN, DIF[x:0] tDSPO_BYPIND  
CLK_IN, DIF[x:0] tDSPO_BYPCOM  
-250  
-300  
0
250  
300  
5
Input-to-output skew variation in Bypass Mode  
across industrial voltage and temperature.  
1,2,3,  
5,8  
0
Random differential tracking error between two  
9ZX devices in Hi BW Mode.  
ps  
(rms)  
1,2,3,  
5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF[x:0]  
tDTE  
Random differential spread spectrum tracking  
error between two 9ZX devices in Hi BW Mode.  
1,2,3,  
5,8  
tDSSTE  
75  
ps  
ps  
dB  
dB  
Output-to-output skew across all outputs  
(common to Bypass and PLL Mode).  
1,2,3,  
8
tSKEW_ALL  
jpeak-hibw  
jpeak-lobw  
39  
1.3  
1.3  
50  
PLL Jitter  
Peaking  
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
0
0
2.5  
2
7,8  
7,8  
PLL Jitter  
Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
pllHIBW  
pllLOBW  
tDC  
LOBW#_BYPASS_HIBW = 1.  
LOBW#_BYPASS_HIBW = 0.  
Measured differentially, PLL Mode.  
2
2.6  
1.0  
50  
4
MHz  
MHz  
%
8,9  
8,9  
1
0.7  
45  
1.4  
55  
Duty Cycle  
Distortion  
Measured differentially, Bypass Mode at  
100MHz.  
tDCD  
-0.5  
0.0  
0.5  
%
1,10  
PLL Mode.  
14  
50  
50  
ps  
ps  
1,11  
1,11  
Jitter, Cycle to  
Cycle  
tjcyc-cyc  
Additive Jitter in Bypass Mode.  
0.1  
1 Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5 Measured with scope averaging on to find mean value.  
6 ‘t’ is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8 Guaranteed by design and characterization, not 100% tested in production.  
9 Measured at 3db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass  
mode.  
11 Measured from differential waveform.  
©2018 Integrated Device Technology, Inc.  
11  
July 3, 2018  
9ZXL1951D Datasheet  
Table 12. Filtered Phase Jitter Parameters – PCIe Common Clocked (CC) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
ps  
tjphPCIeG1-CC  
PCIe Gen 1  
14  
30  
86  
1,2,3  
(p-p)  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
(PLL BW of 5–16MHz or 8–5MHz,  
CDR = 5MHz)  
ps  
1,2  
0.24  
0.7  
3
(rms)  
tjphPCIeG2-CC  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5–16MHz or 8–5MHz,  
CDR = 5MHz)  
Phase Jitter,  
PLL Mode  
ps  
1,2  
1.1  
1.5  
0.4  
3.1  
(rms)  
PCIe Gen 3  
ps  
1,2  
tjphPCIeG3-CC (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
0.26  
1
(rms)  
PCIe Gen 4  
tjphPCIeG4-CC (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
ps  
1,2  
0.26  
0
0.4  
0.5  
(rms)  
ps  
1,2,3,  
4
tjphPCIeG1-CC  
PCIe Gen 1  
0.05  
(p-p)  
PCIe Gen 2 Low Band  
10kHz < f < 1.5MHz  
(PLL BW of 5–16MHz or 8–5MHz,  
CDR = 5MHz)  
ps  
(rms)  
1,2,3,  
4
0
0
0.05  
0.05  
tjphPCIeG2-CC  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
(PLL BW of 5–16MHz or 8–5MHz,  
CDR = 5MHz)  
Additive Phase  
Jitter, Bypass  
Mode  
Not  
ps  
1,2,3,  
4
applicable (rms)  
PCIe Gen 3  
ps  
(rms)  
1,2,3,  
4
tjphPCIeG3-CC (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
0
0
0.05  
0.05  
PCIe Gen 4  
tjphPCIeG4-CC (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
ps  
(rms)  
1,2,3,  
4
1 Applies to all differential outputs, when driven by 9SQL495x or equivalent, guaranteed by design and characterization.  
2 According to the PCIe Base Specification Rev 4.0 version 1.0.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1–12  
.
4 For RMS values additive jitter is calculated by solving the following equation for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c”  
is rms total jitter.  
©2018 Integrated Device Technology, Inc.  
12  
July 3, 2018  
9ZXL1951D Datasheet  
Table 13. Filtered Phase Jitter Parameters – PCIe Independent Reference (IR) Architectures  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
PCIe Gen 2  
(PLL BW of 16MHz, CDR = 5MHz)  
ps  
tjphPCIeG2-SRIS  
0.9  
0.6  
0
1
2
1,2,5  
(rms)  
Phase Jitter,  
PLL Mode  
PCIe Gen 3  
ps  
tjphPCIeG3-SRIS (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
0.65  
0.15  
0.03  
0.7  
1,2,5  
(rms)  
PCIe Gen 2  
(PLL BW of 16MHz, CDR = 5MHz)  
ps  
tjphPCIeG2-SRIS  
1,4,5  
(rms)  
Additive  
Phase Jitter,  
Bypass Mode  
Not  
applicable  
PCIe Gen 3  
tjphPCIeG3-SRIS (PLL BW of 2–4MHz or 2–5MHz,  
CDR = 10MHz)  
ps  
0.0  
1,4,5  
(rms)  
1 Applies to all differential outputs, when driven by 9SQL495x or equivalent, guaranteed by design and characterization.  
2 According to the PCIe Base Specification Rev 4.0 version 1.0.  
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1–12  
.
4 For RMS values additive jitter is calculated by solving the following equation for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c”  
is rms total jitter.  
5 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock  
architectures. According to the PCIe Base Specification Rev 4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter  
limits are not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to  
populate this table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.  
Table 14. Filtered Phase Jitter Parameters – QPI/UPI  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
QPI & UPI  
(100MHz or 133MHz, 4.8Gb/s,  
6.4Gb/s 12UI)  
0.16  
0.4  
0.5  
1,2  
tjphQPI_UPI  
QPI & UPI  
(100MHz, 8.0Gb/s, 12UI)  
0.08  
0.07  
0.15  
0.03  
0.3  
0.2  
1
1,2  
1,2  
Phase Jitter,  
PLL Mode  
ps  
(rms)  
QPI & UPI  
(100MHz, > 9.6Gb/s, 12UI)  
0.1  
0.17  
0.14  
0.2  
tjphIF-UPI  
IF-UPI  
1,4,5  
©2018 Integrated Device Technology, Inc.  
13  
July 3, 2018  
9ZXL1951D Datasheet  
Table 14. Filtered Phase Jitter Parameters – QPI/UPI  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum Typical Maximum  
Units Notes  
QPI & UPI  
(100MHz or 133MHz, 4.8Gb/s,  
6.4Gb/s 12UI)  
0.00  
0.00  
0.01  
0.01  
1,2,3  
Not  
applicable  
Additive  
Phase Jitter,  
Bypass Mode  
tjphQPI_UPI  
QPI & UPI  
(100MHz, 8.0Gb/s, 12UI)  
ps  
(rms)  
1,2,3  
QPI & UPI  
(100MHz, > 9.6Gb/s, 12UI)  
0.00  
0.06  
0.01  
0.08  
1,2,3  
tjphIF-UPI  
IF-UPI  
1,4  
1 Applies to all differential outputs, guaranteed by design and characterization.  
2 Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent.  
3 For RMS values, additive jitter is calculated by solving for b where [b = sqrt(c2 - a2)] where “a”’ is rms input jitter and “c” is rms total jitter.  
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.  
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.  
Table 15. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz  
Industry  
Limits  
Parameter  
Symbol  
Conditions  
Minimum  
Typical Maximum  
Units  
Notes  
Phase Jitter, PLL  
Mode  
PLL High BW, SSC  
Off, 100MHz  
fs  
(rms)  
tjph12k-20MHi  
tjph12k-20MLo  
tjph12k-20MByp  
181  
199  
106  
250  
250  
150  
1,2  
1,2  
Phase Jitter, PLL  
Mode  
PLL Low BW, SSC  
Off, 100MHz  
Not  
applicable  
fs  
(rms)  
Additive Phase Jitter,  
Bypass Mode, SSC  
Off, 100MHz  
fs  
(rms)  
1,2,3  
Bypass Mode  
1 Applies to all outputs when driven by Wenzel clock source.  
2 12kHz to 20MHz brick wall filter.  
3 Additive jitter for RMS values is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.  
©2018 Integrated Device Technology, Inc.  
14  
July 3, 2018  
9ZXL1951D Datasheet  
Test Loads  
Low-Power HCSL Output Test Load  
(standard PCIe source-terminated test load)  
CL  
L
Test  
Points  
Differential Zo  
CL  
Table 16. Parameters for Low -Power HCSL Output Test Load  
Rs (Ω)  
Zo (Ω)  
L (Inches)  
CL (pF)  
Internal  
85  
12  
2
Alternate Terminations  
The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”  
Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.  
Pow er-up Timing  
Figure 2. Power-up Timing Diagram  
VDDx 3.3V  
> 0  
CKPWRGD_PD#  
©2018 Integrated Device Technology, Inc.  
15  
July 3, 2018  
9ZXL1951D Datasheet  
SMBus Addressing  
Table 17. 9ZXL1951 SMBus Addressing  
SADR(1:0)_tri  
SMBus Address (Read/Write bit = 0)  
00  
0M  
01  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
M0  
MM  
M1  
10  
1M  
11  
©2018 Integrated Device Technology, Inc.  
16  
July 3, 2018  
9ZXL1951D Datasheet  
General SMBus Serial Interface Information  
How to Write  
How to Read  
▪ Controller (host) sends a start bit  
▪ Controller (host) will send a start bit  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the write address  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the beginning byte location = N  
▪ IDT clock will acknowledge  
▪ Controller (host) sends the byte count = X  
▪ IDT clock will acknowledge  
▪ Controller (host) will send a separate start bit  
▪ Controller (host) sends the read address  
▪ IDT clock will acknowledge  
▪ Controller (host) starts sending Byte N through Byte N+X-1  
▪ IDT clock will acknowledge each byte one at a time  
▪ Controller (host) sends a stop bit  
▪ IDT clock will send the data byte count = X  
▪ IDT clock sends Byte N+X-1  
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to  
Index Block Write Operation  
Byte 8)  
Controller (Host)  
IDT (Slave/Receiver)  
▪ Controller (host) will need to acknowledge each byte  
▪ Controller (host) will send a not acknowledge bit  
▪ Controller (host) will send a stop bit  
T
starT bit  
Slave Address  
WR WRite  
Index Block Read Operation  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
Slave Address  
WR  
Beginning Byte = N  
WRite  
ACK  
ACK  
O
O
O
O
O
O
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
Byte N + X - 1  
ACK  
ACK  
P
stoP bit  
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
O
O
O
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
©2018 Integrated Device Technology, Inc.  
17  
July 3, 2018  
9ZXL1951D Datasheet  
SMBus Table: PLL Mode and Frequency Select Register  
Byte 0  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
B9  
PLL Mode 1  
PLL Mode 0  
DIF18_En  
DIF17_En  
DIF16_En  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Output Enable  
R
Latch  
See PLL Operating Mode Readback  
table  
B9  
R
Latch  
D1/E1  
B1/C1  
A2/A1  
RW  
RW  
RW  
Low/Low  
Low/Low  
Low/Low  
Enable  
Enable  
Enable  
1
1
1
0
0
0
Output Enable  
Output Enable  
Reserved  
Reserved  
Reserved  
SMBus Table: Output Control Register  
Byte 1  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
L12/K12  
M11/M12  
M9/M10  
M7/M8  
M4/M5  
M2/M3  
L1/M1  
DIF7_En  
DIF6_En  
DIF5_En  
DIF4_En  
DIF3_En  
DIF2_En  
DIF1_En  
DIF0_En  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
1
1
1
1
1
Enabled or Pin  
Control  
(see Byte 4 or  
Byte 8)  
Low/Low  
J1/K1  
SMBus Table: Output Control Register  
Byte 2  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
A4/A3  
A6/A5  
DIF15_En  
DIF14_En  
DIF13_En  
DIF12_En  
DIF11_En  
DIF10_En  
DIF9_En  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
Output Enable  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
1
1
1
1
1
A9/A8  
Enabled or Pin  
Control  
(see Byte 4 or  
Byte 8)  
A11/A10  
B12/A12  
D12/C12  
G12/F12  
J12/H12  
Low/Low  
DIF8_En  
©2018 Integrated Device Technology, Inc.  
18  
July 3, 2018  
9ZXL1951D Datasheet  
SMBus Table: PLL SW Override Control Register  
Byte 3  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
1
1
0
—
—
—
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
Enable S/W control of PLL BW RW  
HW Latch  
SMBus Control  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
RW  
RW  
See PLL Operating Mode Readback  
table  
Note: Setting bit 3 to '1' allows the user to override the Latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL  
Operating Mode Readback table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. If the user changes these bits,  
a warm reset of the system will have to accomplished.  
SMBus Table: OE Pin Configuration A Register  
Byte 4  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
B10  
C11  
E11  
G11  
J11  
K11  
L10  
L8  
OE12#_CFGA  
OE11#_CFGA  
OE10#_CFGA  
OE09#_CFGA  
OE08#_CFGA  
OE07#_CFGA  
OE06#_CFGA  
OE05#_CFGA  
Controls DIF12  
Controls DIF11  
Controls DIF10  
Controls DIF9  
Controls DIF8  
Controls DIF7  
Controls DIF6  
Controls DIF5  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
1
1
1
1
1
1
1
1
Does not Control  
Controls  
SMBus Table: Vendor & Revision ID Register  
Byte 5  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
R
R
R
R
R
R
R
R
0
0
1
1
0
0
0
1
REVISION ID  
D rev = 0011  
—
—
—
—
—
—
—
—
VENDOR ID  
©2018 Integrated Device Technology, Inc.  
19  
July 3, 2018  
9ZXL1951D Datasheet  
SMBus Table: Device ID  
Byte 6  
Pin #  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
1
1
0
0
0
1
0
x
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
1951 is C4 Hex  
SMBus Table: Byte Count Register  
Byte 7  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
0
0
0
—
—
—
—
—
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
Writing to this register  
configures how many bytes will RW  
Default value is 8 hex, so 9 bytes (0  
to 8) will be read back by default.  
be read back.  
RW  
RW  
SMBus Table: OE Pin Configuration B Register  
Byte 8  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
B10  
C11  
E11  
G11  
J11  
K11  
L10  
L8  
OE12#_CFGB  
OE11#_CFGB  
OE10#_CFGB  
OE09#_CFGB  
OE08#_CFGB  
OE07#_CFGB  
OE06#_CFGB  
OE05#_CFGB  
Controls DIF13  
Controls DIF14  
Controls DIF15  
Controls DIF0  
Controls DIF1  
Controls DIF2  
Controls DIF3  
Controls DIF4  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
0
0
0
0
0
0
0
Does not Control  
Controls  
©2018 Integrated Device Technology, Inc.  
20  
July 3, 2018  
9ZXL1951D Datasheet  
Package Drawings  
Figure 3. 80-GQFN Package Drawings– page 1  
©2018 Integrated Device Technology, Inc.  
21  
July 3, 2018  
9ZXL1951D Datasheet  
Figure 4. 80-GQFN Package Drawings– page 2  
©2018 Integrated Device Technology, Inc.  
22  
July 3, 2018  
9ZXL1951D Datasheet  
Marking Diagram  
1. “YYWW” is the last digits of the year and week that the part was assembled.  
2. “$” denotes mark code.  
IDT9ZXL1  
951DNHGI  
YYWW$  
3. “I” denotes industrial temperature.  
4. “LOT” denotes the lot sequence code.  
LOT  
Ordering Information  
Orderable Part Number  
Package  
Carrier Type  
Temperature  
9ZXL1951DNHGI  
9ZXL1951DNHGI8  
6 × 6 × 0.5 mm 80-GQFN  
6 × 6 × 0.5 mm 80-GQFN  
Tray  
-40° to +85°C  
-40° to +85°C  
Tape and Reel  
“G” designates PB-free configuration, RoHS compliant.  
“D” is the device revision designator (will not correlate with the datasheet revision).  
©2018 Integrated Device Technology, Inc.  
23  
July 3, 2018  
9ZXL1951D Datasheet  
Revision History  
Revision Date  
Description of Change  
Added missing Absolute Maximum Ratings table.  
July 3, 2018  
December 1, 2017  
September 29, 2017  
May 1, 2017  
Removed “5V tolerant” reference in pins L4 and L5 descriptions.  
▪ Updated Slew Rate Matching conditions.  
▪ Updated front page text for family consistency.  
▪ Updated Filtered Phase Jitter Parameters - QPI/UPI table to add IF-UPI.  
▪ Test load updated to standard test load drawing for family.  
April 3, 2017  
▪ Updated package outline drawings to latest version (revision 03).  
▪ Updated package outline drawings to latest version (revision 02).  
Initial release.  
March 31, 2017  
March 27, 2017  
Corporate Headquarters  
Sales  
Tech Support  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.IDT.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,  
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same  
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability  
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not  
convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-  
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property  
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  
©2018 Integrated Device Technology, Inc.  
24  
July 3, 2018  
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