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IX6611

型号：

IX6611

品牌：

IXYS[ IXYS CORPORATION ]

页数：

15 页

PDF大小：

1863 K

下载PDF手册
IX6611  
IGBT Gate Driver  
Features  
Description  
• Input Compatible with Pulse Transformer  
• 10A Peak Source and Sink Current Gate Drive  
• Separate Source and Sink Outputs  
• Negative Gate Drive Capability  
• Over Current Protection  
The IX6611 is a secondary side, intelligent, high  
speed gate driver designed to drive IXYS IGBTs as  
well as power MOSFET devices. The IX6611 gate  
driver contains the necessary circuit blocks for pulse  
transformer isolated applications. High frequency,  
narrow pulses are used for bidirectional data transfer  
across the isolation boundary to avoid duty cycle  
restrictions and to prevent transformer saturation. The  
IX6611 includes the necessary monitor/protection  
functions such as Supply Under Voltage Lockout,  
Supply Over Voltage Lockout, Thermal Shut down,  
external IGBT Over Current and Over Voltage  
protection.  
with Adjustable Blanking Time  
• Advanced Active Clamping Protection  
• Under Voltage Lockout Protection  
• Over Voltage Lockout Protection  
• Two One-Amp Pulse Transformer drivers  
for Fault Communication  
Applications  
• AC and DC Motor Drives  
• UPS Systems  
• High Voltage DC/DC Converters  
The IX6611 is designed to operate over a temperature  
range of -40°C to +125°C. The IX6611 is available in a  
16-lead SOIC with an exposed thermal pad.  
Ordering Information  
Part  
Description  
IX6611T  
IX6611TR  
IX6611  
16-Pin SOIC in Tubes (50/Tube)  
16-Pin SOIC Tape & Reel (1000/Reel)  
Tested Die  
Figure 1. IX6611 Block Diagram  
VCC  
VCC  
3
VDD  
VDD  
REF0  
REF1  
REF2  
IBLANK  
REF3  
REF4  
300mV  
REF1  
OVLO  
COMP  
ACL  
ICM  
14  
13  
ACL  
COMP  
EN  
3.1V  
EN  
VREF  
VDD  
LEVEL  
SHIFT  
300mV  
RICM  
OC  
COMP  
UVLO  
COMP  
REF2  
ON  
OFF  
COM  
4
VCC VCC  
COM  
VEE  
LEB  
COMP  
VEE  
6
5
IBLANK  
VEE  
VDD  
VDD  
VCC  
REF0  
FLT1  
CBLANK  
12  
8
OUTPUT  
FAULT PULSE  
GENERATOR  
FAULT  
CONTROL  
LOGIC  
5V REGULATOR  
REFERENCED  
TO VEE  
VEE  
VDD  
FLT2  
7
VEE  
VDD  
VDD  
VCC  
VEE  
VEE  
VEE  
VEE  
VEE  
PVCC  
THSD  
VEE  
NC 11  
VCC  
PVCC  
2
1
VDD  
VDD  
VCC  
VCC  
IN  
RCVP  
9
VEE  
OUTP  
PULSE  
RECOVERY  
LOGIC  
PGATE  
NGATE  
VEE  
ON  
GATE  
CONTROL  
LOGIC  
LEVEL  
SHIFT  
OFF  
VEE  
VCC  
VDD  
16  
OUTN  
RCVN 10  
INB  
VEE  
VEE  
VEE  
VEE  
15 PVEE  
VEE  
VEE  
PVEE  
DS-IX6611-R00A  
PRELIMINARY  
1
IX6611  
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.1 Package Pinout Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.2 Pin Configuration and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.3 Absolute Maximum Ratings @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.4 ESD Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.5.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.5.2 Power Supply Terminals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.5.3 V Regulator (Logic Supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
DD  
1.5.4 Input Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.5.5 Input Interface/Pulse Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1.5.6 Thermal Shutdown Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1.5.7 UVLO Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1.5.8 OVLO Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1.5.9 Leading Edge Blanking Circuit (LEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
1.5.10 Over Current Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
1.5.11 Active Clamp Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
1.5.12 Fault Outputs and Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
1.5.13 IGBT Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1 Detailed Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1.1 Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1.2 Pulse Recovery Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1.3 Gate Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1.4 IGBT Drive Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.5 Over Current Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.6 Leading Edge Blanking Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.7 Active Clamp Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.8 Thermal Shutdown (THSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.9 Output Fault Pulse Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.1.10 5V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
3.1.11 Under Voltage and Over Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
3.1.12 Fault Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.3 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
4.5 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
4.5.1 IX6611T 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
4.5.2 IX6611TTR Tape & Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
2
PRELIMINARY  
R00A  
IX6611  
1. Specifications  
1.1 Package Pinout Pin Description  
OUTP - 1  
PVCC - 2  
VCC - 3  
16 - OUTN  
15 - PVEE  
14 - ACL  
13 - ICM  
COM - 4  
FLT1 - 5  
12 - CBLANK  
11 - NC  
V
EE - 6  
FLT2 - 7  
DD - 8  
10 - RCVN  
9 - RCVP  
V
1.2 Pin Configuration and Definitions  
Pin#  
Name  
Description  
1
2
OUTP Gate driver source output terminal  
PVCC  
Gate driver positive power supply input terminal (connects to the power converter secondary)  
VCC  
3
4
Device positive power supply input terminal (connects to the power converter secondary)  
Device common ground terminal (connects to the power converter secondary and the IGBT emitter terminal)  
Fault signal transformer primary positive terminal  
COM  
FLT1  
VEE  
5
6
Device negative power supply input terminal (connects to the power converter secondary)  
Fault signal transformer primary negative terminal  
7
FLT2  
VDD  
5V regulator output terminal referenced to VEE (connects to an external bypass capacitor)  
8
9
RCVP Positive input terminal (connects to the pulse transformer secondary positive terminal)  
RCVN Negative input terminal (connects to the pulse transformer secondary negative terminal)  
10  
11  
12  
13  
14  
15  
16  
NC  
No connection  
CBLANK  
Over current comparator blanking time capacitor terminal  
ICM  
ACL  
Current sense input terminal (connects to the IGBT current sense resistor)  
Active clamping detect input terminal (connects to the external IGBT collector terminal through a blocking diode)  
Gate driver negative power supply input terminal (connects to the power converter secondary)  
PVEE  
OUTN Gate driver sink output terminal  
R00A  
PRELIMINARY  
3
IX6611  
1.3 Absolute Maximum Ratings @ 25°C  
Parameter  
Supply voltage range  
Symbol  
(VCC-VEE), (PVCC-PVEE  
(VCC-VCOM), (PVCC-VCOM  
Limit  
Units  
)
-0.3 to 40  
-0.3 to 32  
V
V
Positive supply voltage VCC , PVCC  
Negative supply voltage VEE , PVEE  
Driver output voltages  
)
(VEE-VCOM), (PVEE-VCOM  
)
- 10 to 0  
V
(PVEE-0.3) to (PVCC+0.3)  
OUTP, OUTN  
V
V
DD-VEE  
Regulator output terminal voltage  
Analog input terminal voltages  
Analog input terminal voltages  
Fault output terminal voltages  
Input terminal voltages  
-0.3 to 7  
V
(VCOM-0.3) to (VCC+0.3)  
(VEE-0.3) to VCC+0.3)  
(VEE-0.3) to VCC+0.3)  
(VEE-0.3) to (VEE+7)  
ICM  
V
ACL  
V
FLT1, FLT2, CBLANK  
V
RCVP, R C VN  
V
tJ  
Operating junction temperature range  
Storage temperature  
-55 to +150  
-65 to +150  
°C  
°C  
TSTG  
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device.  
Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not  
implied.  
1.4 ESD Warning  
ESD (electrostatic discharge) sensitive device. Electrostatic charges can readily accumulate on test equipment and  
the human body in excess of 4000 Volts. This energy can discharge without detection. Although the IX6611 features  
proprietary ESD protection circuitry, permanent damage might be sustained if subjected to high energy electrostatic  
discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality.  
4
PRELIMINARY  
R00A  
IX6611  
1.5 Electrical Characteristics  
T =-40°C to +125°C unless otherwise noted.  
A
1.5.1 Thermal Characteristics  
Parameter  
Symbol  
Rating  
Units  
JA  
Thermal resistance, junction to ambient  
41  
°C/W  
1.5.2 Power Supply Terminals  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
VCC  
VCC-VCOM  
VEE-VCOM  
PVCC-VCOM  
PVEE-VCOM  
Logic power supply voltage range  
13  
15  
-5  
25  
0
V
V
V
V
VEE  
Logic power supply voltage range  
-10  
PVCC  
PVEE  
ICCQ  
ICOMQ  
IEEQ  
ICC  
Output driver positive power supply voltage range  
Output driver negative power supply voltage range  
Static power supply current  
13  
15  
-5  
25  
0
-10  
-
-
-
-
-
-
3
5
VCC= PVCC=15V, VEE= PVEE= -5V  
No load, static output condition  
0.2  
3
0.5  
5
mA  
mA  
Dynamic power supply current  
15  
0.2  
15  
20  
0.5  
20  
VCC= PVCC=15V, VEE= PVEE= -5V, CL=10nF  
Normal mode, FOUT=50kHz  
ICOM  
IEE  
1.5.3  
V
Regulator (Logic Supply)  
DD  
V
=PV =15V, V =PV = -5V. V regulator voltage is referenced to V . Examples: If V =-5V, then V =0V; or  
CC  
CC  
EE  
EE  
DD  
EE  
EE  
DD  
If V =-10V, then V =-5V; or If V =0V, then V =+5V.  
EE  
DD  
EE  
DD  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
VDD  
VCC=15V, VEE=- 5V IDD=5mA  
Regulator output voltage  
-1  
0
0.5  
V
(VCC–VEE)=15V to 25V  
@ VEE=-10V  
VDD  
Input line regulation  
-
0.2  
-
V
@ IDD=5mA  
VCC=15V, VEE=-5V  
VDD_IDD  
Output load regulation  
-
-
0.5  
0.3  
-
-
V
IDD=1mA to 10mA  
CVDD_ESR  
1mA < IDD < 10mA  
Output bypass capacitor ESR  
1.5.4 Input Terminals  
V
=PV =15V, V =PV =-5V.  
CC EE EE  
CC  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
Measured at RCVP and RCVN terminals  
@ VDD=0V  
Receive input pull-down current @ VDD=0V  
IRCVN_DD, IRCVP_DD  
3
5
10  
mA  
Analog input leakage current @ VCC & VCOM  
Analog input leakage current @ VCOM  
IACL_CC, IACL_COM  
IICM_COM  
Measured at ACL terminal  
Measured at ICM terminal  
-1  
-1  
-
-
1
1
A  
A  
R00A  
PRELIMINARY  
5
IX6611  
1.5.5 Input Interface/Pulse Recovery  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
RRCVP_IN  
,
Measured at terminals RCVP, R C VN with  
respect to VEE  
Receive input resistance  
0.5  
1
1.5  
k  
RRCVN_IN  
VRCVP_IH  
VRCVN_IH  
VRCVP_IL  
VRCVN_IL  
Receive input high voltage  
2.2  
-
-
V
Measured with respect to VEE at RCVP and  
RCVN terminals by monitoring the state  
change at the IGBT driver output terminals  
(OUTP and OUTN). @ VDD=0V  
Receive input low voltage  
Receive input hysteresis  
-
-
1
-
V
V
VHST  
0.5  
1
Measured at RCVP and RCVN terminals by  
monitoring the state change at the IGBT driver  
output terminals @ VDD=0V  
TDET_RCVP  
TDET_RCVN  
Minimum input pulse width detect  
100  
200  
-
ns  
1.5.6 Thermal Shutdown Circuit  
V
=PV =15V, V =PV =-5V. Not production tested. Specifications are characterized and guaranteed by design.  
CC EE EE  
CC  
Parameter  
Symbol  
tSHDN_RISE  
tSHDN_HYS  
Conditions  
Min Typ Max Units  
Thermal shutdown rising threshold  
Thermal shutdown hysteresis  
130  
-
145  
20  
160  
-
°C  
°C  
-
1.5.7 UVLO Circuit  
FLT1 output is connected to a 50kpullup resistor.  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
(VCC-VCOM) UVLO rising threshold  
UVLO_VTH-RISE  
VCOM=0V, VEE=PVEE=0 to -10V  
8
9.5  
11  
V
UVLO rising threshold is measured by  
monitoring state change at FLT1 terminal  
(VCC-VCOM) UVLO hysteresis  
UVLO_VHYST  
-
1.5  
-
V
1.5.8 OVLO Circuit  
FLT1 and FLT2 outputs are connected to 50kpullup resistors.  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
(VCC-VCOM) OVLO rising threshold  
OVLO_VTH-RISE  
VCOM=0V, VEE=PVEE=0 to -10V  
26  
28  
30  
V
OVLO rising threshold is measured by  
monitoring state change at FLT1 and FLT2  
terminals  
(VCC-VCOM) OVLO hysteresis  
OVLO_VHYST  
-
2
-
V
6
PRELIMINARY  
R00A  
IX6611  
1.5.9 Leading Edge Blanking Circuit (LEB)  
=PV =15V, V =PV = -5V.  
V
CC  
CC  
EE  
EE  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
Measured at CBLANK terminal during the  
blanking period  
IBLNK_SRC  
Blanking source current  
180  
225  
300  
A  
Force CBLANK to VDD during the IGBT driver  
off state  
IBLNK_SNK_DC  
Blanking sink current (DC test)  
Blanking time (see note)  
11  
18  
25  
mA  
IGBT driver turn-on to turn-off delay time is  
measured with ICM terminal set at 500mV and  
CBLANK terminal open  
tBLNK_OPEN  
200  
2
400  
3.5  
600  
5
ns  
VBLANK=3V  
IGBT driver turn-on to turn-off delay time is  
tBLNK_220pF measured with ICM terminal set at 500mV and  
Blanking time (see note)  
s  
CBLANK=220pF  
Note: All timing measurements are from 90% input stimulus change to the 10% output response change.  
1.5.10 Over Current Comparator  
V
=PV =15V, V =PV = -5V.  
CC EE EE  
CC  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
VOCTH is measured during the ON time of the  
driver at ICM terminal by monitoring the state  
change at the IGBT driver output  
Over current comparator threshold with respect to  
COM  
VOCTH  
240  
300  
360  
mV  
Step input at the ICM terminal with 50mV  
overdrive (delay time is measured from ICM  
input to gate drive output)  
Over current comparator response time  
(see note)  
tOCR  
-
150  
250  
ns  
Measured at ICM terminal during blanking  
time  
RICM  
Over current comparator input series resistor  
1
-
2
3
-
k  
Over current comparator input shorting switch  
on-resistance  
RON_ICM  
Specification guaranteed by design  
75  
Note: Timing measurements are from 90% input stimulus change to the 10% output response change.  
1.5.11 Active Clamp Comparator  
V
=PV =15V, V =PV = -5V.  
CC EE EE  
CC  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
VACLTH is measured during the OFF time of  
the driver at ACL terminal by monitoring the  
state change at the IGBT driver output,  
IGBT driver output is connected to 50to  
COM terminal  
ACL comparator threshold with respect to VEE  
VACLTH  
2.6  
3.1  
3.6  
V
Step input with 500mV overdrive at the ACL  
terminal (Information parameter)  
ACL comparator response time (see note)  
TACLR  
-
-
150  
300  
-
-
ns  
ns  
Step input at the ACL terminal with 500mV  
overdrive (delay time is measured from ACL  
input to IGBT driver output, IGBT driver output  
is connected to 50to COM terminal)  
ACL comparator to driver output tri-state delay time  
(see note)  
TACL_TRI  
Note: Timing measurements are from 90% input stimulus change to the 10% output response change.  
R00A  
PRELIMINARY  
7
IX6611  
1.5.12 Fault Outputs and Control Logic  
=PV =15V, V =PV = -5V.  
V
CC  
CC  
EE  
EE  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
VDD=0V, measured at FLT1 and FLT2  
Fault signal transformer primary switch sink  
resistance  
RFLT1, RFLT2  
-
1
2
W
terminals @ ISINK = 100mA  
VDD=0V, measured at FLT1 and FLT2  
IPK_FLT1  
,
Fault signal transformer primary switch peak sink  
current  
0.7  
1
-
A
terminals 200ns pulse  
(Characterized but not production tested)  
IPK_FLT2  
VDD=0V, measured at FLT1 and FLT2  
VOL_FLT1  
,
Fault signal transformer primary switch low level  
output voltage  
terminals with 5pull-up resistance  
connected to VDD  
-
0.5  
-
1.5  
-
V
V
VOL_FLT2  
VDSMAX_FLT1  
Fault signal transformer primary switch off-state max  
drain voltage  
@ IDS_LEAK=1uA  
15  
VDSMAX_FLT2  
Measured at FLT1 and FLT2 terminals with  
100pull-up and CL=50pF resistance  
TPW_FLT1  
TPW_FLT2  
Fault signal pulse width  
100  
200  
400  
ns  
connected to VDD  
(characterized but not production tested)  
1.5.13 IGBT Driver Output  
V
=PV =15V, V =PV = -5V.  
CC EE EE  
CC  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
ISOURCE=100mA  
Measured at OUTP terminal  
ISINK=100mA  
VOHP  
VCC-0.15  
High level output voltage  
-
-
V
VOLN1  
ROH  
Low level output voltage  
Output source resistance  
Output sink resistance  
-
-
-
-
0.15  
1.7  
1.5  
V
Measured at OUTN terminal  
ISOURCE=100mA  
0.8  
0.7  
Measured at OUTP terminal  
ISINK=100mA  
ROL  
Measured at OUTN terminal  
@ TA=25°C, CLOAD=330nF  
IPK_SRC  
,
Output peak source and sink current  
Continuous output current  
-
-
10  
2
-
-
A
A
Measured at OUTP and OUTN  
terminals  
IPK_SNK  
@ TA=25°C, measured at OUTP  
and OUTN terminals  
(limited by package power dissipation)  
information parameter  
IDC  
CLOAD=10nF  
tON_DLY  
On-time propagation delay  
Off-time propagation delay  
-
-
50  
50  
125  
125  
ns  
ns  
Measured from RCVP to OUTP  
CLOAD=10nF  
tOFF_DLY  
Measured from RCVN to OUTN  
RLOAD=50 , CLOAD=No load  
tTRI_DLY  
IPLEAK  
INLEAK  
High impedance state delay time  
High impedance PFET leakage  
High impedance NFET lockage  
-
-
-
300  
<1  
-
ns  
A  
A  
-
-
10  
20  
<2  
8
PRELIMINARY  
R00A  
IX6611  
2. Timing Diagrams  
Figure 2. UVLO Condition FAULT1 Timing Diagram  
tDET_RCVP  
RCVP  
tDET_RCVN  
RCVN  
tON_DLY  
tOFF_DLY  
DRIVEROUT  
UVLO_VHYST  
POWER SUPPLY  
(VCC-VCOM  
UVLO_VTH-FALL  
UVLO_VTH-RISE  
)
FLT1  
tPW_FLT1  
Figure 3. OVLO Condition FLT1 & FLT2 Timing Diagram  
tDET_RCVP  
RCVP  
tDET_RCVN  
RCVN  
tON_DLY  
tOFF_DLY  
DRIVEROUT  
POWER SUPPLY  
OVLO_VTH-RISE  
OVLO_VTH-FALL  
(VCC-VCOM  
)
OVLO_VHYST  
FLT1  
tPW_FLT1  
tPW_FLT2  
FLT2  
R00A  
PRELIMINARY  
9
IX6611  
Figure 4. Over Current Condition FLT2 Timing Diagram  
tDET_RCVP  
RCVP  
tDET_RCVN  
RCVN  
tBLNK  
tON_DLY  
tOFF_DLY  
DRIVEROUT  
vOCTH  
ICM  
tOCR  
tPW_FLT2  
tOCR  
tPW_FLT2  
FLT2  
Figure 5. Active Clamp Condition Timing Diagram  
tDET_RCVP  
RCVP  
tDET_RCVN  
RCVN  
tON_DLY  
TRI-STATE  
TRI-STATE  
tOFF_DLY  
DRIVEROUT  
tACL_TRI  
VACLTH  
VACLTH  
ACL  
10  
PRELIMINARY  
R00A  
IX6611  
Figure 6. IX6611 Typical Application Diagram  
HV  
VCC  
PVCC VCC  
R1  
ACL  
3
VDD  
VDD  
REF0  
REF1  
REF2  
IBLANK  
REF3  
REF4  
300mV  
REF1  
VP=+15V  
OVLO  
COMP  
14  
13  
ACL  
COMP  
22µF  
R2  
ICM  
3.1V  
EN  
COM  
VIN  
VREF  
VDD  
LEVEL  
SHIFT  
EN  
300mV  
RICM  
4
OC  
COMP  
VEE VEE  
UVLO  
COMP  
22µF  
VN=-5V  
REF2  
COM  
ON  
RSENSE  
COM  
VCC  
OFF  
VCC VCC  
VEE  
LEB  
COMP  
6
5
IBLANK  
VCC  
VEE  
VEE  
VDD  
PVEE  
VDD  
CBLANK  
REF0  
FLT1  
12  
8
OUTPUT  
FAULT PULSE  
GENERATOR  
FAULT  
CONTROL  
LOGIC  
5V REGULATOR  
REFERENCED  
TO VEE  
VDD  
50  
50  
VDD  
VDD  
50  
VEE  
VEE  
VEE  
FLT2  
NC  
7
VDD  
VCC  
VEE  
VEE  
VEE  
VEE  
VEE  
VEE  
PVCC  
THSD  
VEE  
11  
PVCC  
VCC  
2
1
VDD  
VDD  
RCVP  
RCVN  
OUTP  
VCC  
VCC  
IN  
9
VEE  
RON  
50  
50  
PULSE  
RECOVERY  
LOGIC  
3.3V  
VEE  
ON  
PGATE  
NGATE  
GATE  
CONTROL  
LOGIC  
LEVEL  
SHIFT  
50  
OFF  
OUTN  
PVEE  
VEE  
VCC  
VDD  
VEE  
16  
15  
ROFF  
10  
INB  
VEE  
VEE  
VEE  
VEE  
VEE  
VEE  
PVEE  
3. Theory of Operation  
The IX6611 integrated circuit is designed to provide gate drive for high power IGBT modules. The device converts the  
incoming isolated PWM logic signals into a +15V/-5V bipolar gate drive signal with a typical 10A peak drive current  
capability.  
3.1 Detailed Circuit Description  
3.1.2 Pulse Recovery Logic  
The Pulse Recovery Logic block receives the leading  
edge pulse and trailing edge pulse signals from the  
Input Interface and reconstructs the complementary  
IN and INB drive signals. These complementary  
signals are level shifted to drive the Gate Control Logic  
block.  
3.1.1 Input Interface  
The Input Interface block of the gate driver is designed  
to be compatible with pulse transformers. The receiver  
inputs, RCVP and RCVN, are connected to the pulse  
transformer secondary through a diode/resistor  
network as shown on the typical application diagram  
Figure 6 on page 11. The Input Interface contains  
high speed Schmitt trigger buffers with 1V typical  
hysteresis. To reject noise and high frequency  
interference, a well matched full differential  
architecture is used for the Schmitt trigger buffer  
receivers.  
3.1.3 Gate Control Logic  
The Gate Control Logic block inserts a fixed dead time  
between the incoming IN and INB signals to generate  
non-overlapping PGATE drive and NGATE drive  
signals. This dead time is sufficient to prevent  
R00A  
PRELIMINARY  
11  
IX6611  
shoot-through in the large output P-channel and  
N-channel devices.  
Traditional de-saturation protection can also be  
implemented using a large ratio resistor divider  
connected across the collector and the emitter. A  
noise filter (RC) at the current sense input may be  
required due to low sense voltage.  
The Gate Control Logic block also receives power  
supply status, IGBT over-current status, and IGBT  
collector over-voltage status signals. Based on these  
signals the output stage is conditioned accordingly as  
shown in Figure 2 on page 9, Figure 3 on page 9,  
Figure 4 on page 10 and Figure 5 on page 10.  
3.1.6 Leading Edge Blanking Circuit  
To prevent false tripping of the OC Comparator, its  
input is grounded for a fixed amount of time during the  
turn-on of the IGBT.  
If a supply under-voltage or a supply over-voltage fault  
event is detected during the leading edge of the input  
PWM gate drive cycle, then the driver is disabled for  
the entire duration of the cycle. Normal operation  
resumes at the beginning of the next cycle only if there  
is no supply fault condition.  
Leading Edge Blanking Circuit sets the blanking time  
and it is programmable through an external capacitor.  
The OC Comparator input is also grounded during the  
off time of the driver.  
If an IGBT over-current fault occurs during the ON  
time of the PWM cycle, then the IGBT driver output is  
forced low for the remainder of the cycle. Normal  
operation resumes at the beginning of the next PWM  
gate drive cycle.  
3.1.7 Active Clamp Comparator  
IX6611 contains an Active Clamp Comparator (ACL  
COMP) with a 3.1V threshold that can be used for  
implementing an advanced active clamping technique  
as shown in application circuit diagram Figure 6 on  
During the OFF time of the IGBT driver, if an IGBT  
collector over-voltage fault occurs, then for the  
remainder of the cycle the output PFET is turned off  
and the output NFET state is controlled by the ACL  
comparator as shown in the Figure 5 on page 10.  
Normal operation resumes at the beginning of the next  
PWM gate drive cycle.  
page 11. ACL COMP threshold is with respect to V  
.
EE  
During the turn off of the IGBT, the ACL comparator  
can detect an over voltage, if the collector voltage  
rises above the breakdown voltage of the diode  
connected at the collector. In the over voltage  
condition the ACL comparator forces the gate driver  
output to a tri-state condition and the IGBT starts to  
turn on due to the break down diode current charging  
the IGBT gate. Once the IGBT turns on, its collector  
3.1.4 IGBT Drive Outputs  
IX6611 contains separate 10A peak source and sink  
outputs. Separated sink and source outputs allow  
independent gate charge and discharge control  
without an external diode. The internal dead-time  
circuit eliminates the cross conduction of the source  
and sink outputs.  
voltage falls, the diode recovers from break down, and  
the ACL comparator turns on the NMOS output and  
forces the IGBT gate low. This sequence may repeat  
several times until the energy in the external  
inductance is dissipated.  
ACL comparator is active only when the driver output  
PFET is OFF.  
3.1.5 Over Current Comparator  
IX6611 contains an Over Current Comparator (OC  
COMP) with a 300mV threshold. This comparator is  
used for sensing over-current conditions in the  
external IGBT.  
3.1.8 Thermal Shutdown (THSD)  
IX6611 contains a Thermal Shutdown circuit to protect  
the device against the damage due to excessive die  
temperature. When the junction temperature exceeds  
150°C, the input signals to the gate driver and the ACL  
comparator are disabled and the gate driver output is  
forced low. Device resumes normal operation when  
the junction temperature falls below 130°C.  
Emitter current sense can be implemented either by  
using a low value current shunt or an IGBT with a  
secondary current sense output.  
The current-sense method works well for high gain  
IGBTs that do not have inherent short circuit  
protection. Careful application board layout is  
mandatory due to low sense voltage.  
3.1.9 Output Fault Pulse Generator  
An IGBT over current fault event can occur any time  
during the ON time of the gate drive signal. When an  
12  
PRELIMINARY  
R00A  
IX6611  
over current occurs the Output Faults Pulse Generator  
creates a narrow 200ns pulse that will be used by the  
Fault Control Logic to communicate the fault condition  
to the primary side across the barrier.  
The UVLO circuit is operational at V no greater than  
CC  
3V and it keeps the gate driver output low until V is  
CC  
raises above the UVLO threshold.  
3.1.12 Fault Control Logic  
3.1.10 5V Regulator  
Fault information is communicated to the primary side  
through the pulse transformer interface. Fault Control  
Logic provides the gate drive to the high current  
switches connected to the primary terminals of the  
pulse transformer. Narrow pulses are used to drive the  
high current switches. Based on the fault type, the fault  
control logic selects the narrow pulses either from the  
input interface or from the output fault pulse generator  
and drives the appropriate high current switch.  
The 5V regulator provides power to the internal low  
voltage circuits that are referenced to VEE. Regulator  
is powered from V and V and its output voltage is  
CC  
EE  
referenced to V . An external bypass capacitor is  
EE  
required to provide the transient currents.  
3.1.11 Under Voltage and Over Voltage Lockout  
IX6611 contains an Under Voltage Lockout  
Comparator (UVLO COMP) and an Over Voltage  
Lockout Comparator (OVLO COMP). These  
comparators monitor the positive power supply  
UVLO fault condition is communicated to the primary  
side by driving the FLT1 high current switch on the  
leading edge of the PWM gate drive ON cycle.  
terminal “V ” with respect to “COM” terminal. At the  
CC  
OVLO fault condition is communicated to the primary  
side by driving the FLT1 high current switch on the  
leading edge and the FLT2 high current switch on the  
trailing edge of the PWM gate drive ON cycle. The  
primary side recognizes the OVLO fault condition if  
and only if both FLT1 and FLT2 flags are set.  
beginning of each PWM cycle, if the difference in  
power supply voltage (V -V  
) is below the UVLO  
CC COM  
threshold or above the OVLO threshold the gate driver  
output is disabled (driven low) for that PWM cycle.  
Once the PWM cycle starts with no power supply  
faults then the gate driver is enabled and the UVLO  
and OVLO faults are ignored for the reminder of the  
cycle. Power supply fault are not latched. Normal  
operation resumes automatically on the next PWM  
input cycle after the power supply recovers from the  
fault condition.  
IGBT Over Current condition is communicated to the  
primary side by driving the FLT2 high current switch  
with a pulse from the output fault pulse generator.  
R00A  
PRELIMINARY  
13  
IX6611  
4. Manufacturing Information  
4.1 Moisture Sensitivity  
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Corporation  
classified all of its plastic encapsulated devices for moisture sensitivity according to the  
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product  
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee  
proper operation of our devices when handled according to the limitations and information in that standard as well as  
to any limitations set forth in the information or standards referenced below.  
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced  
product performance, reduction of operable life, and/or reduction of overall reliability.  
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled  
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.  
Device  
Moisture Sensitivity Level (MSL) Classification  
IX6611T  
MSL 1  
4.2 ESD Sensitivity  
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.  
4.3 Soldering Profile  
Provided in the table below is the Classification Temperature (T ) of this product and the maximum dwell time the  
C
body temperature of this device may be above (T - 5)ºC. The classification temperature sets the Maximum Body  
C
Temperature allowed for this device during lead-free reflow processes. For through hole devices, and any other  
processes, the guidelines of J-STD-020 must be observed.  
Classification Temperature (TC)  
Dwell Time (tp)  
Device  
Max Reflow Cycles  
IX6611T  
260°C  
30 seconds  
3
4.4 Board Wash  
IXYS Corporation recommends the use of no-clean flux formulations. Board washing to reduce or  
remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to  
prevent damage to the device. These precautions include, but are not limited to: using a low pressure wash and  
providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing  
process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature  
and duration necessary to remove the moisture trapped within the package is the responsibility of the user  
(assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be  
used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based.  
14  
PRELIMINARY  
R00A  
IX6611  
4.5 Package Mechanical Dimensions  
4.5.1 IX6611T 16-Pin SOIC  
PIN  
16  
Recommended PCB Land Pattern  
3.90 BSC  
2.40  
(0.094)  
6.00 BSC  
(0.236 BSC)  
(0.154 BSC)  
(See Note 3)  
5.30  
(0.209)  
1.50  
(0.059)  
Pin 1  
0.31 - 0.51  
(0.012 - 0.020)  
1.27 BSC  
(0.05 BSC)  
0.10 - 0.25  
(0.004 - 0.010)  
4.55  
(0.179)  
0.60  
(0.024)  
1.25 MIN  
1.27  
(0.05)  
9.90 BSC  
(0.39 BSC)  
(See Note 2)  
(0.049 MIN)  
1.70 MAX  
(0.067 MAX)  
0.25 - 0.50 x 45º  
(0.010 - 0.020 x 45º)  
DIMENSIONS  
mm  
(inches)  
0 - 0.15  
(0 - 0.006)  
0.10  
(0.004)  
3.86 - 4.57  
(0.152 - 0.180)  
8º MAX  
NOTES:  
1. JEDEC Outline MS-12 BC REV.F (Thermal)  
2. Dimension does not include mold flash, protrusions,  
or gate burrs. Mold flash, protrusions, and gate burrs  
shall not exceed 0.15mm per side.  
3. Dimension does not include inter-lead flash or  
protrusions. Inter-lead flash and protrusions shall not  
exceed 0.25mm per side.  
0.40 - 1.27  
(0.016 - 0.050)  
1.68 - 2.41  
(0.066 - 0.095)  
4.5.2 IX6611TTR Tape & Reel  
TBD  
For additional information please visit our website at: www.ixys.com  
IXYS Corporation makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to  
specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Corporation Standard  
Terms and Conditions of Sale, IXYS Corporation assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied  
warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.  
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other  
applications intended to support or sustain life, or where malfunction of IXYS Corporation's product may result in direct physical harm, injury, or death to a person or severe  
property or environmental damage. IXYS Corporation reserves the right to discontinue or make changes to its products at any time without notice.  
Specification: DS-IX6611-R00A  
©Copyright 2016, IXYS  
All rights reserved. Printed in USA.  
6/9/2016  
R00A  
PRELIMINARY  
15  
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