PALCE20V8
Pin Configuration
PLCC/LCC
Top View
DIP/QSOP
Top View
CLK/I
1
2
3
4
5
6
24
23
22
V
0
CC
I
13
I
1
I
2
I/O
4
3
2
1
2827 26
25
7
I
I/O
3
21
20
19
18
17
6
I
3
5
I/O
6
I
4
I/O
I/O
I
I
5
5
6
7
8
9
10
11
4
I/O
5
24
23
22
21
20
19
I
5
4
I/O
4
I
6
I/O
I/O
7
8
3
NC
NC
I/O
I
7
2
I
6
3
I/O
I
I
9
9
1
16
15
14
13
I
8
I/O
2
I/O
1
7
I
8
10
11
12
I/O
0
121314 1516 1718
I
I
12
10
OE/I
GND
11
20V8–3
20V8–2
Selection Guide
tPD ns
tS ns
tCO ns
ICC mA
Generic Part Number
PALCE20V8−5
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l
115
115
115
90
Mil/Ind
5
3
4
5
PALCE20V8−7
7.5
10
15
25
15
25
7
PALCE20V8−10
PALCE20V8−15
PALCE20V8−25
PALCE20V8L−15
PALCE20V8L−25
10
15
25
15
25
10
12
15
12
15
10
12
20
12
20
7
10
12
20
12
20
130
130
130
65
10
12
10
12
90
55
55
65
Shaded area contains preliminary information.
Electronic Signature
Functional Description (continued)
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
Security Bit
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Power-Up Reset
Input and I/O Pin Pull-Ups
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, VCC, or
Ground to improve noise immunity and reduce ICC
.
Document #: 38-03026 Rev. **
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