请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

XWM8146CDW/V

型号：

XWM8146CDW/V

描述：

12位（8 + 4位）的线性传感器图像处理器[ 12-bit(8+4-bit) Linear Sensor Image Processor ]

品牌：

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数：

17 页

PDF大小：

195 K

下载PDF手册
WM8146  
12-bit (8+4-bit) Linear Sensor Image Processor  
Product Preview, January 2000 Rev 1.1  
DESCRIPTION  
FEATURES  
•
•
•
•
•
•
•
•
•
•
•
•
No missing codes guaranteed  
6MSPS sample rate  
Colour pixel by pixel or line by line sampling  
Monochrome sampling  
Selectable reset level clamp voltage  
Pixel by pixel or line by line clamping  
Correlated double sampling  
5-bit programmable gain amplifier  
8-bit + sign offset adjustment  
5V or 3.3V digital interface compatibility  
Serial control interface  
The WM8146 is a 12-bit analogue front end/digitiser IC,  
which processes and digitises the analogue output signals  
from linear CCD sensors at pixel sample rates of up to  
6MSPS.  
The device includes three analogue signal processing  
channels each of which contains Reset Level Clamping,  
Correlated Double Sampling and Programmable Gain and  
Offset adjust functions. The output from each of these  
channels is time multiplexed into a single high-speed 12-bit  
Analogue to Digital Converter. The digital output data is  
available in 8+4-bit wide multiplexed format, with no missing  
codes.  
28-pin SOIC package  
The WM8146 is controlled via  
a configurable serial  
interface, which is compatible with all of Wolfson’s imaging  
devices.  
APPLICATIONS  
Powered from an analogue supply voltage of 5V and a  
digital interface supply of either 5V or 3.3V, the WM8146  
typically only consumes 175mW when operating from 5V  
supplies.  
•
•
•
•
Flatbed scanners  
Multi-function peripherals  
Copier scanners  
CCD sensor interfaces  
BLOCK DIAGRAM  
VRLC  
(26)  
AVDD  
(21)  
VRT  
(24)  
VRB  
(23)  
VMID  
(25)  
AGND1 AGND2  
(22) (2)  
VSMP  
(5)  
MCLK  
(7)  
RLC  
(6)  
DGND  
(8)  
DVDD1  
(3)  
DVDD2  
(10)  
MUX  
TIMING CONTROL  
CL  
RS  
VS  
VMID  
OFFSET  
RINP (1)  
S/H  
+
+
PGA  
S/H  
(4)  
OEB  
WM8146  
CDS  
5-BIT REG  
8-BIT  
+
VMID  
SIGN DAC  
(13) OP[0]  
(14)  
OP[1]  
OFFSET  
(15)  
OP[2]  
M
U
X
GINP(28)  
S/H  
8+4  
MUX  
(16) OP[3]  
12-bit  
ADC  
+
+
PGA  
(17)  
(18)  
(19)  
(20)  
OP[4]  
OP[5]  
OP[6]  
OP[7]  
S/H  
CDS  
5-BIT REG  
8-BIT  
+
SIGN DAC  
VMID  
OFFSET  
S/H  
BINP(27)  
+
+
PGA  
S/H  
CONFIGURABLE  
SERIAL CONTROL  
INTERFACE  
(11)SDI  
CDS  
5-BIT REG  
8-BIT  
SIGN DAC  
+
(12)  
VMID  
SCK  
(9) SEN  
WOLFSON MICROELECTRONICS LTD  
Product Preview data sheets contain  
specifications for products in the formative  
phase of development. These products may  
be changed or discontinued without notice.  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
http://www.wolfson.co.uk  
1999 Wolfson Microelectronics Ltd  
.
WM8146  
Product Preview  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
0 to 70oC  
28-pin SOIC  
RINP  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
GINP  
BINP  
XWM8146CDW/V  
AGND2  
DVDD1  
OEB  
VRLC  
VMID  
VRT  
VSMP  
RLC  
VRB  
MCLK  
DGND  
AGND1  
AVDD  
WM8146  
SEN  
DVDD2  
SDI  
9
20  
19  
18  
17  
16  
15  
OP[7]  
OP[6]  
OP[5]  
OP[4]  
OP[3]  
OP[2]  
10  
11  
12  
13  
14  
SCK  
OP[0]  
OP[1]  
PIN DESCRIPTION  
PIN  
1
NAME  
RINP  
TYPE  
DESCRIPTION  
Analogue input  
Supply  
Red channel input video.  
Analogue ground (0V).  
2
AGND2  
DVDD1  
3
Supply  
Digital supply (5V) for logic and clock generator. This must be operated at the same  
potential as AVDD.  
4
5
6
OEB  
VSMP  
RLC  
Digital input  
Digital input  
Digital input  
Output Hi-Z control, all digital outputs disabled when OEB = 1.  
Video sample synchronisation pulse.  
Selects reset level clamp on a pixel-by-pixel basis – active high. Tie high to use on  
every pixel.  
7
MCLK  
Digital input  
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or  
any multiple of 2 thereafter depending on input sample mode).  
8
DGND  
SEN  
Supply  
Digital ground (0V).  
9
Digital input  
Supply  
Enables the serial interface when high.  
Digital supply (5V/3.3V), all digital I/O pins.  
Serial interface data input.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
DVDD2  
SDI  
Digital input  
Digital input  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Supply  
SCK  
Serial interface clock.  
OP[0]  
OP[1]  
OP[2]  
OP[3]  
OP[4]  
OP[5]  
OP[6]  
OP[7]  
AVDD  
AGND1  
VRB  
Digital multiplexed output data bus.  
OEB = 0: ADC output data is available in (8+4bit) multiplexed format on pins OP[7] to  
OP[0]. See Operational Timing diagrams for details.  
OEB = 1: Output is Hi=Z.  
Analogue supply (5V). This must be operated at the same potential as DVDD1.  
Analogue ground (0V).  
Supply  
Analogue output Lower reference point of ADC reference string  
This pin must be connected to AGND via a decoupling capacitor.  
Analogue output Upper reference point of ADC reference string  
This pin must be connected to AGND via a decoupling capacitor.  
Analogue output Buffered mid-point of ADC reference string  
This pin must be connected to AGND via a decoupling capacitor.  
Analogue output Selectable analogue output voltage for RLC.  
This pin must be connected to AGND via a decoupling capacitor.  
Blue channel input video.  
Green channel input video.  
24  
25  
26  
VRT  
VMID  
VRLC  
27  
28  
BINP  
GINP  
Analogue input  
Analogue input  
PP Rev 1.1 January 2000  
2
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount  
assembly.  
CONDITION  
MIN  
MAX  
Analogue supply voltage: AVDD  
Digital supply voltages: DVDD1 − 2  
Digital ground: DGND  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND + 7V  
GND + 7V  
GND + 0.3V  
GND + 0.3V  
DVDD2 + 0.3V  
AVDD + 0.3V  
AVDD + 0.3V  
Analogue grounds: AGND1 − 2  
Digital inputs, digital outputs and digital I/O pins  
Analogue inputs (RINP, GINP, BINP)  
Other pins  
Operating temperature range: TA  
Storage temperature  
°
°
+70 C  
0 C  
°
°
+150 C  
-65 C  
Lead temperature (soldering, 10 sec)  
Lead temperature (soldering, 2 mins)  
°
+260 C  
+183°C  
Notes: 1. GND denotes the voltage of any ground pin.  
2. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages  
between these pins will degrade performance.  
RECOMMENDED OPERATING CONDITIONS  
CONDITION  
SYMBOL  
TA  
MIN  
0
TYP  
MAX  
70  
UNITS  
Operating temperature range  
Analogue supply voltage  
Digital core supply voltage  
Digital I/O supply voltage  
°C  
V
AVDD  
DVDD1  
4.75  
4.75  
5.0  
5.0  
5.25  
5.25  
V
5V I/O  
DVDD2  
DVDD2  
4.75  
2.97  
5.0  
3.3  
5.25  
3.63  
V
V
3.3V I/O  
PP Rev 1.1 January 2000  
3
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST  
MIN  
TYP  
MAX  
UNIT  
CONDITIONS  
Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)  
NO MISSING CODES GUARANTEED  
Full-scale transition error  
±25  
±25  
±100  
±100  
+1.5  
mV  
mV  
Zero-scale transition error  
Differential non-linearity  
References  
DNL  
LSB  
Upper reference voltage  
Lower reference voltage  
DAC reference voltage  
RLC switching impedance  
Reset level clamp options  
VRT  
VRB  
AVDD = 5V  
AVDD = 5V  
AVDD = 5V  
3.47  
1.47  
2.47  
3.5  
1.5  
2.5  
500  
1.5  
2.5  
3.5  
500  
3.53  
1.53  
2.53  
V
V
V
Ω
V
V
V
Ω
VMID  
VRLC  
AVDD = 5V  
1.46  
2.46  
3.46  
250  
1.54  
2.54  
3.54  
750  
Voltage set by register  
configuration  
Impedance VRT to VRB  
Input Multiplexer  
2
CDS mode full scale input range  
x denotes the channel selected  
Vp-p  
Gx  
(VVS-VRS  
)
Channel to channel gain matching  
1
%
Offset DAC (monotonicity guaranteed)  
Resolution  
8 (+sign)  
VMID-20  
0
bits  
mV  
Zero code voltage  
VMID+20  
Full scale voltage error  
Differential non-linearity  
Integral non-linearity  
Step size  
20  
0.5  
1
mV  
DNL  
INL  
0.1  
0.25  
4.9  
LSB  
LSB  
DACRNG=0  
DACRNG=1  
DACRNG=0  
DACRNG=1  
mV/step  
mV/step  
7.4  
Output voltage  
+/-1.25  
+/-1.875  
V
V
Programmable Gain Amplifier (monotonicity guaranteed)  
Resolution  
5
bits  
V/V  
V/V  
%
Max gain, each channel  
Min gain, each channel  
Gain error, each channel  
DIGITAL SPECIFICATIONS  
Digital Inputs  
GMAX  
GMIN  
8.25  
0.5  
1
High level input voltage  
VIH  
VIL  
0.8  
DVDD2  
V
V
Low level input voltage  
0.2  
DVDD2  
High level input current  
Low level input current  
Input capacitance  
IIH  
IIL  
CI  
1
1
µA  
µA  
pF  
5
Digital Outputs  
High level output voltage  
VOH  
VOL  
IOZ  
IOH = 1mA  
IOL = 1mA  
DVDD2 -  
0.5  
V
V
Low level output voltage  
DGND +  
0.5  
High impedance output current  
1
µA  
PP Rev 1.1 January 2000  
4
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
Test Conditions  
AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST  
MIN  
TYP  
MAX  
UNIT  
CONDITIONS  
Supply Currents  
Total supply current − active  
35  
5
mA  
mA  
Supply current − full power down  
mode  
INPUT VIDEO SAMPLING  
tPER  
tMCLKH tMCLKL  
MCLK  
tVSMPH  
tVSMPSU  
VSMP  
INPUT  
tVSU  
tVH  
tRSU  
tRH  
VIDEO  
Figure 1 Input Video Timing  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
MCLK period  
tPER  
83.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MCLK high period  
MCLK low period  
tMCLKH  
tMCLKL  
tVSMPSU  
tVSMPH  
tVSU  
37.5  
37.5  
10  
VSMP set-up time  
VSMP hold time  
10  
Video level set-up time  
Video level hold time  
Reset level set-up time  
Reset level hold time  
10  
tVH  
15  
tRSU  
10  
tRH  
15  
Notes: 1.  
t
VSU and tRSU denote the set-up time required after the input video signal has settled.  
2.  
Parameters are measured at 50% of the rising/falling edge.  
OUTPUT DATA TIMING  
MCLK  
tPD  
OP[7:0]  
Figure 2 Output Data Timing  
PP Rev 1.1 January 2000  
5
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
OEB  
tPZE  
tPEZ  
OP[7:0]  
Hi-Z  
Hi-Z  
Figure 3 Output Data Enable Timing  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
tPD  
TEST CONDITIONS  
MIN  
TYP  
MAX  
75  
UNITS  
ns  
Output propagation delay  
Output enable time  
Output disable time  
IOH = 1mA, IOL = 1mA  
tPZE  
50  
ns  
tPEZ  
25  
ns  
SERIAL INTERFACE  
tSPER  
tSCKL tSCKH  
SCK  
tSSU  
tSH  
SDI  
tSCE  
tSEW tSEC  
SEN  
Figure 4 Serial Interface Timing  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SCK period  
tSPER  
83.3  
ns  
SCK high  
tSCKH  
tSCKL  
tSSU  
tSH  
37.5  
37.5  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK low  
SDI set-up time  
SDI hold time  
10  
SCK to SEN set-up time  
SEN to SCK set-up time  
SEN pulse width  
tSCE  
tSEC  
tSEW  
20  
20  
50  
Note: Parameters are measured at 50% of the rising/falling edge.  
PP Rev 1.1 January 2000  
6
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
DEVICE DESCRIPTION  
GENERAL OPERATION  
A block diagram of the device showing the signal path is presented on Page 1.  
The WM8146 samples the three inputs (RINP, GINP and BINP) simultaneously. The device then  
processes the sampled video signal with respect to the video reset level or the reference level VMID  
using three processing channels.  
Each processing channel consists of an input sampling block with optional reset level clamping  
(RLC) and correlated double sampling (CDS), a 5-bit programmable gain amplifier (PGA) and an 8-  
bit (+sign) programmable offset DAC.  
For colour operation, the resulting analogue outputs from the three channels are multiplexed into a  
12-bit ADC. For monochrome operation the resulting analogue output from the selected channel only  
is multiplexed into the ADC. The ADC then converts the analogue signal to a 12-bit digital word. The  
digital output from the ADC is presented on an 8-bit wide output bus, in 8+4-bit multiplexed format.  
Internal control registers determine the configuration of the device, including the gain and offset  
applied to each channel. These registers are programmable via the serial interface.  
RESET LEVEL CLAMPING (RLC)  
CONFIGURATION  
To ensure that the signal applied to the WM8146 lies within its input range, the CCD output signal is  
usually level shifted by a.c. coupling through a capacitor, CIN. The RLC circuit clamps the WM8146  
side of this capacitor to a selected voltage during the CCD reset level. The RLC voltage VRLC, is  
selected by control bits RLC[1:0] in setup register 3.  
A typical input configuration demonstrating reset level clamping and CDS circuitry is shown in Figure  
5. A clamp pulse, CL, is generated from MCLK and VSMP by the timing control block. When CL is  
active the voltage on the WM8146 side of CIN, at RINP, is forced to the RLC voltage VRLC by switch  
1. When the CL pulse turns off, the voltage at RINP initially remains at VRLC but any subsequent  
variation in sensor voltage (from reset to video level) will couple through CIN to RINP.  
Reset level clamping is compatible with both CDS and non-CDS operating modes, as selected by  
switch 2.  
RLC  
MCLK VSMP  
TIMING CONTROL  
FROM CONTROL  
INTERFACE  
CL  
RS  
VS  
CIN  
+
-
S/H  
TO PGA  
+
RINP  
2
S/H  
1
RLC  
CDS  
INPUT SAMPLING  
BLOCK FOR RED  
CHANNEL  
CDS  
FROM CONTROL  
INTERFACE  
VRLC  
VRLC  
VMID  
AGND  
Figure 5 Reset Level Clamping and CDS Circuitry  
PP Rev 1.1 January 2000  
7
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
TIMING  
Figure 6 illustrates the use of the RLC pin, MCLK and VSMP to control the timing of the CL pulse for  
a typical CCD waveform. The CL pulse is applied during the reset period.  
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during  
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal  
CL pulse on the next reset level. The position of CL can be adjusted by using control bits  
CDSREF[1:0], as shown in Figure 7.  
The VRLC pin outputs the analogue RLC voltage selected via control set-up register 3 bits RLC[1:0].  
MCLK  
VSMP  
1
X
X
0
X
X
0
RLC  
Programmable Delay  
CL  
(CDSREF = 01)  
INPUT VIDEO  
RGB  
RGB  
RGB  
No RLC on this Pixel  
RLC on this Pixel  
Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL  
CDS/NON-CDS PROCESSING  
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel  
common mode noise. For CDS operation, the video level is processed with respect to the video reset  
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must  
be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from  
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by  
programming control bits CDSREF[1:0], as shown in Figure 7 .  
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed  
with respect to the reference voltage VMID.  
MCLK  
VSMP  
VS  
RS/CL (CDSREF = 00)  
RS/CL (CDSREF = 01)  
RS/CL (CDSREF = 10)  
RS/CL (CDSREF = 11)  
Figure 7 Reset Sample and Clamp Timing  
PP Rev 1.1 January 2000  
8
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
OFFSET ADJUST AND PROGRAMMABLE GAIN  
The output from the CDS block is a differential signal, which is amplified by a 5-bit PGA then added  
to the output of an 8-bit (+sign) offset DAC to compensate for sensor d.c. offsets. The gain and offset  
for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[4:0].  
The following diagram shows the signal path through the device.  
OUTPUT  
INVERT  
BLOCK  
INPUT  
SAMPLING  
BLOCK  
TO MULTIPLEXER  
FOR 8-BIT OUTPUT  
D2  
OFFSET DAC  
BLOCK  
PGA  
BLOCK  
ADC BLOCK  
V1  
V2  
V3  
D1  
V 3  
x (4096/VFS) +2047  
X
+
VIN  
+
+
digital  
analog  
-
CDS  
CDS  
= 1  
D2  
=
D1 if INVOP = 0  
D2 =4095-D1 if INVOP  
= 1  
VRESET  
PGA gain  
= 0.5+(PGA[4:0]*0.25)  
=
0
A
VMID  
Offset  
DAC  
V IN is RINP or GINP or BINP  
V RESET is VIN sampled during reset clamp  
V MID is AVDD/2  
(1-2*DSIGN)*(DAC[7:0]/255)*(V MID/2  
+ VMID/4*DACRNG)  
CDS, DAC[7:0], DSIGN, DACRNG, PGA[4:0]  
and INVOP are set by programming internal  
control registers.  
CDS=1 for CDS,  
0 for non-CDS  
Figure 8 Signal Flow Diagram  
The following equations enable the user to calculate the settings required for the PGAs and offset  
DACs.  
INPUT SAMPLING AND REFERENCING  
If CDS=1, the previously sampled reset level, VRESET, is subtracted from the input video signal VIN  
(i.e. CDS operation).  
V1 = VIN - VRESET  
If CDS=0, the simultaneously sampled VMID is subtracted instead (i.e. non-CDS operation).  
V1 = VIN - VMID  
GAIN ADJUST  
The signal is then multiplied by the PGA gain, approximately 0.5 to 8.25 in 32 equal gain steps.  
V2 = V1 * G  
= V1 * (0.5+(PGA[4:0]*0.25))  
OFFSET (BLACK-LEVEL) ADJUST  
The resultant signal is added to the Offset DAC output which has a range of VMID/2 (or 1.5*VMID/2 if  
the DACRNG bit is set).  
V3 = V2 + VDAC  
= V2 + [(1-2*DSIGN) * DAC_CODE/255 * (VMID/2 + VMID/4 * DACRNG)]  
ANALOGUE TO DIGITAL CONVERSION  
The analogue signal is then converted to a 12-bit unsigned number. This is equivalent to a  
multiplication by 4096/(VFS), where VFS = 2V .  
D1 == INT{ (V3/VFS) * 4096 } + 2047  
At this stage, the input to the ADC should be between -1V and +1V, so D1[11:0] should lie between  
-2047 and +2048. If the input is over-range, it will be clipped to within the range (-2047,2048).  
2047 is added to the ADC output, to give code 2047 for zero input signal to the ADC. This is  
equivalent to the +VMID shown in the block diagram on page 1.  
PP Rev 1.1 January 2000  
9
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
DIGITAL POLARITY ADJUST  
The polarity of the digital output may be inverted by control bit INVOP. If INVOP=0, negative-going  
input video will give negative-going digital output. If INVOP=1, negative-going video will give positive-  
going digital output.  
D2 = D1  
…
…
(INVOP=0)  
(INVOP=1)  
D2 = 4095 – D1  
DIGITAL CONTROL AND I/O FUNCTIONS  
OUTPUT DATA  
Data appears on the pins OP[7:0] and changes after every negative-going MCLK edge, as shown in  
Figure 9 .  
tPD  
MCLK  
A
B
OP[7:0]  
Figure 9 WM8146 Output Timing  
A = d11, d10, d9, d8, d7, d6, d5, d4  
Pin OP[7] to OP[0]  
Pin OP[7] to OP[0]  
B = d3, d2, d1, d0, 0, CC[1], CC[0], OVRNG  
Where  
CC1/CC0: These bits show from which channel the current output was taken. 00 = RED,  
01 = GREEN, 10 = BLUE.  
OVRNG: This bit indicates if the current output pixel has exceeded the maximum or minimum range  
during processing. 1 = out of range, 0 = within range.  
CONTROL INTERFACE  
The internal control registers are programmable via the serial digital control interface.  
REGISTER WRITE  
The serial interface involves three dedicated pins, SCK, SDI, SEN (refer to Figure 10). A six-bit  
address is clocked in through SDI MSB first followed by an eight-bit data word, also MSB first. Each  
bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is  
applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have  
address bit a4 equal to 0.  
SCK  
a5  
0
a3  
a2  
a1  
a0  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
SDI  
Address  
Data Word  
SEN  
Figure 10 Register Write Timing  
TIMING REQUIREMENTS  
To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock  
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces  
PP Rev 1.1 January 2000  
10  
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum  
sample rates for the various modes are shown in Table 1.  
POWER SUPPLY  
The WM8146 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)  
supplies.  
OPERATING MODES  
Table 1 summarises the most commonly used modes, the clock waveforms required and the register  
contents required for CDS and non-CDS operation.  
MODE DESCRIPTION  
CDS  
MAX  
SENSOR  
INTERFACE  
DESCRIPTION  
TIMING  
REQUIRE-  
MENTS  
REGISTER  
CONTENTS  
WITH  
REGISTER  
CONTENTS  
WITH  
AVAILABLE SAMPLE  
RATE  
CONTROL  
BIT CDS=1  
CONTROL  
BIT CDS=0  
1
Colour  
Pixel-by-Pixel  
Yes  
2MSPS  
The 3 input channels  
are sampled in  
MCLK max =  
12MHz  
SetReg1:  
03(hex)  
SetReg1:  
01(hex)  
parallel. The signal is  
then gain and offset  
adjusted before being  
multiplexed into a  
single data stream and  
converted by the ADC,  
giving an output data  
rate of 6MSPS max.  
As mode 1 except:  
Only one input  
MCLK:VSMP  
ratio is 6:1  
2
Monochrome/  
Colour  
Yes  
2MSPS  
MCLK max =  
12MHz  
SetReg1:  
07(hex)  
SetReg1:  
05(hex)  
Line-by-Line  
channel at a time  
is continuously  
SetReg3 bits  
7:6  
SetReg3  
bits 7:6  
MCLK:VSMP  
ratio is 6:1  
sampled.  
determine  
determine  
which input is which input  
to be  
is to be  
sampled  
sampled  
3
4
Fast  
Monochrome/  
Colour  
Yes  
No  
4MSPS  
6MSPS  
Identical to mode 2  
Identical to mode 2  
MCLK max =  
12MHz  
MCLK:VSMP  
ratio is 3:1  
Identical to  
Identical to  
mode 2  
mode 2 plus  
SetReg3: bits  
5:4 must be  
set to 0(hex)  
Line-by-Line  
Maximum  
speed  
MCLK max =  
12MHz  
CDS not  
possible  
SetReg1:  
45(hex)  
Monochrome/  
Colour  
SetReg3  
bits 7:6  
MCLK:VSMP  
ratio is 2:1  
Line-by-Line  
determine  
which input  
is to be  
sampled  
5
6
Slow Colour  
Pixel-by-Pixel  
Yes  
Yes  
1.5MSPS Identical to mode 1  
1.5MSPS Identical to mode 2  
MCLK max =  
12MHz  
MCLK:VSMP  
ratio is  
Identical to  
mode 1  
Identical to  
mode 1  
2n:1, n ≥ 4  
Slow  
Monochrome/  
Colour  
MCLK max =  
12MHz  
MCLK:VSMP  
ratio is  
Identical to  
mode 2  
Identical to  
mode 2  
Line-by-Line  
2n:1, n ≥ 4  
Table 1 WM8146 Operating Modes  
PP Rev 1.1 January 2000  
11  
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
OPERATING MODE TIMING DIAGRAMS  
The following diagrams output data, MCLK, VSMP and input video requirements for operation of the  
most commonly used modes as shown in Table 1 . The diagrams are identical for both CDS and  
non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X  
denotes invalid data.  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT  
VIDEO  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
OP[7:0]  
Figure 11 Mode 1 Operation  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP[7:0]  
Figure 12 Mode 2 Operation  
23.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
OP[7:0]  
Figure 13 Mode 3 Operation  
PP Rev 1.1 January 2000  
12  
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0]  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
Figure 14 Mode 4 Operation  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT  
VIDEO  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
BA  
BB  
RA  
RB  
GA  
GB  
X
X
X
X
X
X
X
X
OP[7:0]  
Figure 15 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0])  
RA  
RB  
RA  
RB  
RA  
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Figure 16 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)  
PP Rev 1.1 January 2000  
13  
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
DEVICE CONFIGURATION  
REGISTER MAP  
Table 2 describes the location of each control bit used to determine the operation of the WM8146.  
The register map is programmed by writing the required codes to the appropriate addresses via the  
serial interface.  
Address  
<a5:a0>  
000001  
000010  
000011  
000100  
000101  
100000  
100001  
100010  
100011  
100100  
100101  
100110  
100111  
101000  
101001  
101010  
101011  
Description  
Def  
(hex)  
03  
00  
11  
BIT  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Setup Register 1  
Setup Register 2  
Setup Register 3  
Software Reset  
VSMP6M  
MONO  
INVOP  
CDS  
ENADC  
CHAN[1]  
CHAN[0]  
CDSREF[1]  
CDSREF[0]  
RLC[1]  
RLC[0]  
00  
00  
00  
00  
00  
00  
Setup Register 4  
DAC Value (Red)  
DAC Value (Green)  
DAC Value (Blue)  
DAC Value (R+G+B)  
DAC Sign (Red)  
DAC Sign (Green)  
DAC Sign (Blue)  
DAC Sign (R+G+B)  
PGA Gain (Red)  
PGA Gain (Green)  
PGA Gain (Blue)  
PGA Gain (R+G+B)  
DACRNG  
DAC[1]  
DAC[1]  
DAC[1]  
DAC[1]  
DAC[7]  
DAC[7]  
DAC[7]  
DAC[7]  
DAC[6]  
DAC[6]  
DAC[6]  
DAC[6]  
DAC[5]  
DAC[5]  
DAC[5]  
DAC[5]  
DAC[4]  
DAC[4]  
DAC[4]  
DAC[4]  
DAC[3]  
DAC[3]  
DAC[3]  
DAC[3]  
DAC[2]  
DAC[2]  
DAC[2]  
DAC[2]  
DAC[0]  
DAC[0]  
DAC[0]  
DAC[0]  
DSIGN  
DSIGN  
DSIGN  
DSIGN  
PGA[0]  
PGA[0]  
PGA[0]  
PGA[0]  
00  
00  
00  
00  
00  
PGA[4]  
PGA[4]  
PGA[4]  
PGA[4]  
PGA[3]  
PGA[3]  
PGA[3]  
PGA[3]  
PGA[2]  
PGA[2]  
PGA[2]  
PGA[2]  
PGA[1]  
PGA[1]  
PGA[1]  
PGA[1]  
00  
00  
00  
Table 2 Register Map  
PP Rev 1.1 January 2000  
14  
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
REGISTER MAP DESCRIPTION  
REGISTER  
BIT  
NO  
BIT NAME(S)  
DEFAULT  
DESCRIPTION  
Setup  
Register 1  
0
1
ENADC  
CDS  
1
1
ADC standby control : 0=standby, 1=active  
Select correlated double sampling mode:  
0=single ended mode, 1=CDS mode  
2
6
MONO  
0
0
Mono/colour select: 0=colour, 1=monchrome operation  
VSMP6M  
Required when VSMP at 6MSPS:  
0=other mode, 1=VSMP at 6MSPS  
Setup  
2
INVOP  
0
Digitally inverts the polarity of input data.  
Register 2  
0= negative going video gives negative going output,  
1=negative-going video gives positive going output data.  
Setup  
Register 3  
1:0  
5:4  
RLC[1:0]  
01  
01  
Reset Level Clamp Voltage:  
00 = 1.5V; 01 = 2.5V; 10 = 1.5V; 11 = Reserved  
CDS mode reset timing adjust  
00 = advance 1 MCLK period  
01 = Normal  
CDSREF[1:0]  
10 = Retard 1 MCLK period  
11 = Retard 2 MCLK periods  
Monochrome mode channel select  
00 = Red channel select  
7:6  
CHAN[1:0]  
00  
01 = Green channel select  
10 = Blue channel select  
11 = Reserved  
Software  
Reset  
Write any value to the Software Reset register to cause all  
cells to be reset.  
Setup  
Register 4  
1
0
DACRNG  
DSIGN  
0
0
Offset DAC Output Range:  
0 = DAC Output range =VMID/2 = +/-1.25V  
1 = DAC output Range = 1.5*VMID/2 = +/-1.875V  
Polarity of Offset DAC output  
Registers  
100100 to  
0 = Positive Output (Offset added)  
100111  
1 = Negative Output (Offset removed)  
Table 3 Register Control Bits  
PP Rev 1.1 January 2000  
15  
WOLFSON MICROELECTRONICS LTD  
WM8146  
Product Preview  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD1 (5V)  
C1  
DVDD2 (3.3V or 5V)  
3
8
C2  
C3  
C4  
DVDD1  
DVDD2  
DGND  
10  
AVDD (5V)  
21  
22  
2
AVDD  
AGND1  
AGND2  
C6  
C5  
AGND  
24  
25  
23  
AGND  
VRT  
VMID  
VRB  
1
RINP  
GINP  
BINP  
VIDEO  
INPUTS  
28  
27  
C7  
C8  
C9  
C10 C11 C12  
26  
VRLC  
C13  
C14  
AGND  
WM8146  
AGND  
20  
19  
18  
17  
16  
15  
14  
13  
OP[7]  
OP[6]  
OP[5]  
OP[4]  
OP[3]  
OP[2]  
OP[1]  
OP[0]  
7
5
6
MCLK  
VSMP  
RLC  
TIMING  
SIGNALS  
OUTPUT  
DATA  
BUS  
12  
11  
9
SCK  
SDI  
SEN  
INTERFACE  
CONTROLS  
4
OEB  
NOTES: 1. C1-14 should be fitted as close to WM8146 as possible.  
2. AGND and DGND should be connected as close to WM8146 as possible.  
Figure 17 External Components Diagram  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1  
C2  
100nF  
10µF  
De-coupling for DVDD1.  
Reservoir capacitor for DVDD1.  
De-coupling for DVDD2.  
C3  
100nF  
10µF  
C4  
Reservoir capacitor for DVDD2  
De-coupling for AVDD.  
C5  
100nF  
10µF  
C6  
Reservoir capacitor for AVDD  
De-coupling for VRB..  
C7  
100nF  
10µF  
C8  
Reservoir capacitor for VRB.  
De-coupling for VMID  
C9  
100nF  
22µF  
C10  
C11  
C12  
C13  
C14  
Reservoir capacitor for VMID.  
De-coupling for VRT  
100nF  
10µF  
Reservoir capacitor for VRT  
De-coupling capacitor for VRLC  
Reservoir capacitor VRLC  
100nF  
10µF  
Table 4 External Components Descriptions  
PP Rev 1.1 January 2000  
16  
WOLFSON MICROELECTRONICS LTD  
Product Preview  
WM8146  
PACKAGE DIMENSIONS  
D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch  
DM016.B  
e
B
28  
15  
ZONE A  
ZONE B  
E
H
L
h x 45o  
1
14  
D
α
C
A1  
SEATING PLANE  
-C-  
A
0.10 (0.004)  
Dimensions  
(mm)  
Dimensions  
(Inches)  
Symbols  
MIN  
2.35  
0.10  
0.33  
0.23  
17.70  
MAX  
2.65  
0.30  
0.51  
0.32  
18.10  
MIN  
MAX  
A
A1  
B
C
D
e
0.0926  
0.0040  
0.0130  
0.0091  
0.6969  
0.1043  
0.0118  
0.0200  
0.0125  
0.7125  
1.27 BSC  
0.0500 BSC  
E
h
H
L
7.40  
0.25  
10.00  
0.40  
0o  
7.60  
0.75  
10.65  
1.27  
8o  
0.2914  
0.0100  
0.3940  
0.0160  
0o  
0.2992  
0.0290  
0.4190  
0.0500  
8o  
α
REF:  
JEDEC.95, MS-013  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).  
D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE  
A OR ZONE B.  
PP Rev 1.1 January 2000  
17  
WOLFSON MICROELECTRONICS LTD  
厂商 型号 描述 页数 下载

WOLFSON

 		XWM8148CFT/V 12位/ 12MSPS CCD / CIS模拟前端/数字转换器[ 12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser ] 43 页

WOLFSON

 		XWM8170CFT/V 3.3V集成信号处理器的面阵CCD的[ 3.3V Integrated Signal Processor for Area Array CCDs ] 41 页

WOLFSON

 		XWM8181CDW 12位2MSPS串行输出CIS / CCD数字转换器[ 12-bit 2MSPS Serial Output CIS/CCD Digitiser ] 14 页

WOLFSON

 		XWM8190CDW/V （ 8 + 6 ）位输出14位CIS / CCD AFE /数字转换器[ (8+6) Bit Output 14-bit CIS/CCD AFE/Digitiser ] 25 页

WOLFSON

 		XWM8191CFT 14位6MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser ] 27 页

WOLFSON

 		XWM8192 （88）位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ] 24 页

WOLFSON

 		XWM8192CDW/V （88）位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ] 24 页

CIRRUS

 		XWM8194CDW/V [ Analog Circuit, 1 Func, CMOS, PDSO28, 7.50 MM, 1.27 MM PITCH, MS-013AE, SOIC-28 ] 27 页

WOLFSON

 		XWM81955CFT/RV 14位12MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser ] 33 页

WOLFSON

 		XWM8195CFT 14位12MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser ] 31 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.201711s