WV3EG265M64EFSU-D4
White Electronic Designs
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°c ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Parameter
Symbol Conditions
DDR333 @ DDR266 @ DDR266 @
Unit
CL = 2.5
CL = 2
CL = 2.5
One device bank active; Active-Precharge; tRC = tRC(MIN)
;
tCK = tCK(MIN); DQ, DM and DQS inputs change once per clock
cycle; Address and control inputs change once every two
clock cycles
Operating current
Operating current
IDD0*
1360
1240
1240
mA
One device bank; Active-Read-Precharge; BL = 4;
tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control
inputs change once per clock cycle
IDD1*
1600
360
1480
360
920
760
1480
360
920
760
mA
mA
mA
mA
Percharge power-
down standby current
All device banks are idle; Power-down mode; tCK = tCK(MIN)
CKE = LOW
;
IDD2P**
IDD2F**
IDD3P**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN)
;
Idle standby current
CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM
1000
840
Active power-down
standby current
One device bank active; Power-down mode; tCK = tCK(MIN)
CKE = LOW
;
CS# = HIGH; CKE = HIGH; One device bank active;
Active standby
current
tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs change
twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N**
IDD4R*
IDD4W*
1080
1640
1720
1000
1480
1400
1000
1480
1400
mA
mA
mA
Burst = 2; Reads; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); IOUT = 0mA
Operating current
Operating current
Burst = 2; Writes; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; tCK = tCK(MIN); DQ, DM and DQS inputs change twice per
clock cycle
Auto refresh current
Self refresh current
IDD5**
IDD6**
tRC = tRFC(MIN)
CKE < 0.2V
4920
360
4760
360
4760
360
mA
mA
Four device bank interleaving Reads Burst = 4 with auto
precharge; tRC = tRFC(MIN); tCK = tCK(MIN); Address and control
inputs change only during Active READ, or WRITE commands
Orerating current
IDD7*
3560
3120
3120
mA
NOTE:
I
DD specification is based on Micron components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operating condition and all other module ranks in IDD2P (CKE low) mode.
** Value calculated reflects all module ranks in this operating condition.
AC OPERATING TEST CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK3 inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF +0.31
Max
Unit
V
V
V
V
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
0.7
0.5*VCCQ-0.2
October 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
