WV3EG232M64STSU-D4
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Conditions
Parameter
Symbol
DDR333 @
CL = 2.5 Max
Unit
Operating current
- One bank Active-
Precharge
IDD0*
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
404
mA
Operating current
IDD1*
One bank open, BL=4, Reads - Refer to the following page for detailed test
condition
416
40
mA
mA
mA
- One bank operation
Percharge power-
down standby current
IDD2P**
IDD2F**
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
Precharge Floating
standby current
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
200
Active power - down
standby current
IDD3P**
one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for
88
mA
mA
DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and
DM
Active standby
current
IDD3N**
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC
= tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ, DQS and DM inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
360
Operating current
- burst read
IDD4R*
Burst length = 2; reads; continguous burst; One bank active; address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; 50ꢀ of data changing at every burst; lout = 0mA
436
488
mA
mA
Operating current
- burst write
IDD4W*
Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50ꢀ of
input data changing at every burst
Auto refresh current
IDD5**
IDD6**
IDD7A*
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
1544
40
mA
mA
mA
Self refresh current;
CKE =< 0.2V
External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B
Orerating current
- Four bank operation
Four bank interleaving with BL=4 -Refer to the following page for detailed test
condition
1248
NOTE:
I
DD specification is based on NANYA components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September 2005
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
