WV3EG264M72ESFR-D4
White Electronic Designs
ADVANCED
DDR IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TCASE < +70°C; VCCQ = +2.5V 0.2V, VCC = +2.5V 0.2V
Symbol Conditions
335
262
265
Unit
IDD0
Operating current - One bank Active-Precharge;
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
1,215
1,215
1,080
mA
IDD1
Operating current - One bank operation;
1,485
90
1,485
90
1,350
90
mA
mA
One bank open, BL = 4, Reads - Refer to the following page for detailed test condition
IDD2P
Percharge power-down standby current;
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
IDD2F
Precharge Floating standby current;
810
810
720
mA
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
IDD3P
Active power - down standby current;
630
900
630
900
540
810
mA
mA
one bank active; power-down mode; CKE = < VIL(max); tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM
IDD3N
Active standby current;
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC = tRASmax; tCK
=
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing
twice per clock cycle; address and other control inputs changing once per clock cycle
IDD4R
Operating current - burst read;
1.530
1,440
1.530
1,440
1,350
1,260
mA
mA
Burst length = 2; reads; continguous burst; One bank active; address and control inputs
changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for
DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst;
lOUT = 0 m A
IDD4W
Operating current - burst write;
Burst length = 2; writes; continuous burst; One bank active address and control inputs
changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for
DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
IDD5
Auto refresh current;
5,220
90
5,220
90
5,040
90
mA
mA
mA
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
IDD6
Self refresh current;
CKE = < 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
IDD7A
Orerating current - Four bank operation;
Four bank interleaving with BL = 4 -Refer to the following page for detailed test condition
3,690
3,645
3,195
Typical case: VCC = 2.5V, T = 25°C
Worst case: VCC = 2.7V, T = 10°C
Note: IDD specifications are based on Micron components. Other DRAM manufacturers specificaitons may be different.
August 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
