WV3EG6437S-D4
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
403
335
UNITS
PARAMETER
SYMBOL
tAC
MIN
-0.65
0.45
0.45
5
MAX
+0.65
0.55
0.55
10
MIN
-0.7
0.45
0.45
MAX
+0.7
0.55
0.55
Access window of DQs from CK/CK#
CK high-level width
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCH
CK low-level width
tCL
CL = 3
tCK (3)
tCK (2.5)
tDH
Clock cycle time
CL = 2.5
6
12
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.40
0.40
1.75
-0.55
0.35
0.35
0.40
0.40
1.75
-0.60
0.35
0.35
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
+0.65
+0.60
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.40
1.28
0.45
1.25
0.72
0.20
0.20
0.75
0.20
0.20
tCH(MIN) or tCL(MIN)
tCH(MIN) or (MIN)
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
+0.65
+0.70
tLZ
-0.65
0.60
-0.70
tIHF
0.75
0.75
tISF
0.60
tIHS
0.70
0.80
tISS
0.70
0.75
tIPW
2.20
2.20
tMRD
tQH
10
10
tHP - tQHS
tHP - tQHS
tQHS
tRAS
tRAP
tRC
0.50
0.55
70K
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
40
15
70K
42
18
55
60
tRFC
tRCD
tRP
70
72
ACTIVE to READ or WRITE delay
15
18
PRECHARGE command period
15
18
DQS read preamble
tRPRE
tRPST
tRRD
tWPRE
tWPRES
0.90
0.40
10
1.10
0.60
0.9
0.4
12
1.10
0.60
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
0.25
0
0.25
0
DQS write preamble setup time
Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
