WV3HG264M72EER-D7
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V
Symbol Parameter Condition
806
665
534
403
Unit
Operating
one bank
active-
tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid
CC CC CC
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC0*
1337
1292
1292
mA
TBD
precharge;
Operating
one bank
active-
read-
precharge;
IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is
CC
CC
CC
ICC1*
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING; Data pattern is same as ICC4W
1472
644
1427
644
1427
644
mA
mA
TBD
TBD
.
Precharge
power-
down
All banks idle; tCK = tCK(I ); CKE is LOW; Other control and address bus inputs are
CC
ICC2P**
STABLE; Data bus inputs are FLOATING
current;
Precharge
quite
standby
current;
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
CC
ICC2Q**
1130
1220
1040
1130
1040
1130
mA
mA
TBD
TBD
Precharge
ICC2N** standby
current;
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
CC
inputs are STABLE; Data bus inputs are SWITCHING
Fast PDN Exit
MRS(12) = 0
Active
power-
down
current;
1040
716
1040
716
1040
716
mA
mA
TBD
TBD
All banks open; tCK = tCK(I ), CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
CC
ICC3P**
Slow PDN Exit
FLOATING
MRS(12) = 1
Active
ICC3N** standby
current;
All banks open; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS#
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
CC
CC
CC
1490
1832
1877
3200
144
1400
1652
1697
3020
144
1400
1562
1562
3020
144
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
Operating All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I
ICC4W* burst write tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid commands;
;
)
CC
CC
CC
current;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;
ICC4R* burst read tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between
CC
CC
CC
current;
valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.
Burst auto tCK = tCK(I ); Refresh command at every tRC(I ) interval; CKE is HIGH; CS# is HIGH
CC
CC
ICC5**
refresh
current;
between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self
CK and CK# at 0V; CKE < 0.2V; Other control and address bus
Normal
ICC6**
refresh
current;
inputs are FLOATING; Data bus inputs are FLOATING
Operating
bank
interleave
read
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I ) - 1*tCK(I
;
)
CC
CC
tCK = tCK(I ); tRC = tRC(I ); tRRD = tRRD MIN(I ) = 1*tCK(I ); CKE is HIGH; CS# is HIGH
CC
CC
CC
CC
ICC7*
2552
2552
2552
mA
TBD
between valid commands; Address bus inputs are STABLE during DESELECTs; Data
bus inputs are SWITCHING
current;
Notes:
I
CC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
August 2006
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
