WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge;
806
665
534
403
Units
t
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid
816
776
736
mA
TBD
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
896
856
816
mA
TBD
ICC2P** Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
192
140
720
192
560
640
192
560
640
mA
mA
mA
TBD
TBD
TBD
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
480
192
400
192
400
192
mA
mA
TBD
TBD
Slow PDN Exit MRS(12) = 1
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
800
720
720
mA
mA
mA
TBD
TBD
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,336 1,136 1,016
1,336 1,136 1,016
3,520 3,440 3,360
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
mA
mA
TBD
TBD
TBD
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
ICC6**
ICC7*
Normal
160
160
160
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
2,496 2,336 2,176
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
February 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
